embedded systems laboratory informatics institute federal university of rio grande do sul porto...

Embedded Systems Laboratory Informatics Institute

Federal University of Rio Grande do SulPorto Alegre – RS – Brazil

SRC TechCon 2005Portland, Oregon, USA

Dealing withMultiple Simultaneous Faults

in Future Technologies

Carlos A. L. Lisbôa Erik Schüler

Luigi Carro

Carlos A. L. Lisbôa SRC TechCon 2005 - October, 26, 2005 - Paper # 20.4 2

Why Multiple Simultaneous Faults ?

• Future technologies (2010 and beyond)

• very small transistors and fewer electrons to form the

channel ( SETs)

• transient pulses due to radiation attack will last longer

than the propagation delays of gates

• devices will be more sensitive to the effects of

electromagnetic noise, neutrons and alpha particles

Single Event Upset Origin

1 0 1 0 0 0 0 1

0 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0

Why Should One Study Multiple Faults ?

Change in paradigm:

Gates will behave statistically,

producing correct outputs only a

fraction of the time.

• New paradigm: multiple simultaneous faults• new fault tolerance techniques will be required

(TMR will no longer provide enough protection)

How to Deal with Multiple Faults ?

• New paradigm: multiple simultaneous faults• new fault tolerance techniques will be required (TMR

will no longer provide enough protection)

• How to deal with this problem ?

• new materials and manufacturing technologies

must be developed

OR• new design approaches must be taken

• New paradigm: multiple simultaneous faults• new fault tolerance techniques will be required (TMR

will no longer provide enough protection)

• How to deal with this problem ?

•new design approaches must be taken (our bet !)

Research Approaches

• Use of stochastic operators

• Use of bit stream operators

• Ensuring voter reliability to use n-MR while dealing with multiple simultaneous faults

• Next steps: 2005 - 2007 time frame

Research Evolution

OK for someDSP

Applications

ing fo

StochasticOperators

Small footprintand fast

Tolerant to multiple faults in n-MR solutions

AnalogVoter

Bit StreamOperators

Looking for

tolerant converter

Using Stochastic Operators

• SEU induced transient errors are of random nature

• Stochastic operators rely on randomness to produce approximate results

• The injection of random faults in the input signals processed by stochastic operators did not impact the precision of the results

0 faults 2 faults 4 faults 8 faults0.1412 0.2580 0.1768 0.2196

Stochastic AdderConventional

0.0000

% Errors in 1,000 additions

• The injection of random faults in the input signals processed by stochastic operators did not impact the precision of the results

• Several application areas (DSP) can deal with approximate values and still produce acceptable results (outputs)

• Benefit: reduced area of the operators

Stochastic multiplier circuit

1000100110011010

10010001000010111000000100001010

Stochastic Adder Circuit

01100010101

010111011001S1

01010101101

0010100110101

How does it work ?

Come and see the posters !

No free drinks, but the answer to this question is granted !

Using Bit Stream Operators

• Computation principles similar to those of the stochastic adder and multiplier

• Operators can produce bit streams which represent the exact results of the operation

Proposed Multiplication Algorithm - bit stream product(the count of 1’s in the stream is equal to the product value)

F12 F11 F10

x F22 F21 F20

F20.F12 F20.F11 F20.F10

F21.F12 F21.F11 F21.F10

F22.F12 F22.F11 F22.F10

b48 .. b33 b32 .. b17 b16 .. b5 b4 .. b1 b0

b48 .. b48 b47 .. b47 ... b0 .. b0 1 1 1 1 0 0 0

8 times 8 times 8 times +4total count of 1’s = 8 * product + 4

• Redundancy is added to the bit streams in order to stand to multiple bit flips

Adding robustness to the bit stream through redundancy

• Conversion of bit streams to binary coded values is delayed as much as possible, and conversion circuits must use TMR or n-MR for protection against faults

• Issues to be further investigated: size of bit streams and area of the conversion circuits

No free food, but some more info on this subject will be provided !

How does it work ?

Come and see the posters !

correct output

What is Wrong with TMR ?

• TMR protects only against single faults in one of the modules

Module 1

Module 2

Module 3

correct output

Module 2 wrong output

Module 1

Module 3

correct output

• TMR protects only against single faults in one of the modules

Module 2 correct output

• TMR does not protect against double faults in different modules

Module 1

Module 3

wrong output

correct output

• When a single fault occurs in the voter circuit, the voter output may be wrong

Module 1

Module 2

Module 3

correct output

correct output ?

Module 1

Module 2

Module 3

correct output

• When a single fault occurs in the voter circuit, the voter output may be wrong

Making TMR (n-MR) more reliable

• Known solutions imply in• area, performance and / or power penalties

• deadlock: how to protect the output generator ?

• Proposed solution:• use TMR to cope with single faults in the modules

• replace the digital voter by an analog voter that• uses a comparator to generate the output

• can support some noise, nevertheless producing the correct result

The Analog Voter

Injection of faultsin the comparator (*)

Minimum Area Comparator

(*) using CMOS 0.35µm

Electrical Simulation: Multiple Faults(SPICE and CMOS 0.35 m)

Dealing with Multiple Simultaneous Faults: n-MR

The Analog Voter with 5 Inputs (for 5-MR)

Dealing with Multiple Simultaneous Faults: n-MR

The Analog Voter with 5 Inputs (for 5-MR)

Simulations with injection of2 simultaneous faults also succeeded

The Analog Voter ... Oops !

Does t

work ??

Let’s

see the

posters !

The Analog Voter

Future Work - Short Term (2005-2006)

• use of signal redundancy with other number representation forms, such as Sigma-Delta

• use of the analog voter as an efficient way to implement robust n-MR circuits

• investigate the application of statistical methods and neural networks to the design of fault tolerant circuits with minimum redundancy

Future Work - Long Term (2006-2007)

• use of logic properties to develop signal redundancy with low cost

• apply the developed techniques to actual processors w/ DSP and VLIW architectures

• apply the developed techniques to actual processors with DSP and VLIW architectures

• discuss the architectural impact of new technologies together with fault tolerance

Research Evolution

StochasticOperators Analog

Bit StreamOperators

previous work (2004-2005) 2005 2006 2007

Research Evolution

Bit StreamOperators

SigmaDelta

previous work (2004-2005) 2005 2006 2007

Research Evolution

Bit StreamOperators

SigmaDelta

Logic Properties

previous work (2004-2005) 2005 2006 2007

Low cost

redundancy

Research Evolution

Bit StreamOperators

SigmaDelta

Logic Properties

previous work (2004-2005) 2005 2006 2007

Application to actualDSP and VLIW processors

Low cost

redundancy

Research Evolution

Bit StreamOperators

SigmaDelta

Logic Properties

DSP / VLIW

previous work (2004-2005) 2005 2006 2007

Questions ?

Looking forward to answer them at the poster booth!

(# 20.4)

Contact: calisboa@inf.ufrgs.br

Thank You !

No free anything, but a nice chat about these matters will be a pleasure !

embedded systems laboratory informatics institute federal university of rio grande do sul porto...

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