digital integrated circuits© prentice hall 1995 combinational logic combinational logic

Digital Integrated Circuits © Prentice Hall 1995Combinational LogicCombinational Logic

COMBINATIONAL LOGIC

Overview

Static CMOS

Conventional Static CMOS Logic

Ratioed Logic

Pass Transistor/Transmission Gate Logic

Dynamic CMOS Logic

Domino

np-CMOS

Combinational vs. Sequential Logic

Circuit

CircuitOut

OutInIn

(a) Combinational (b) Sequential

Output = f(In) Output = f(In, Previous In)

Static CMOS Circuit

At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path.

The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).

This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

Static CMOS

PUN and PDN are Dual Networks

PMOS Only

NMOS Only

NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

Y = X if A and B

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors in Series/Parallel Connection

Y = X if A AND B = A + B

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

Complementary CMOS Logic Style Construction (cont.)

Example Gate: NAND

Example Gate: NOR

Example Gate: COMPLEX CMOS GATE

OUT = D + A• (B+C)

4-input NAND Gate

In1 In2 In3 In4

Standard Cell Layout Methodology

signalsRouting Channel

metal1

polysilicon

Two Versions of (a+b).c

a c b a b c

VDDVDD

(a) Input order {a c b} (b) Input order {a b c}

Logic Graph

Consistent Euler Path

{ a b c}

Example: x = ab+cd

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

(c) stick diagram for ordering {a b c d}

Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively.

No static power consumption:

There never exists a direct path between VDD and

VSS (GND) in steady-state mode.

Comparable rise and fall times:

(under the appropriate scaling conditions)

Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively.

No static power consumption:

There never exists a direct path between VDD and

VSS (GND) in steady-state mode.

Comparable rise and fall times:

(under the appropriate scaling conditions)

Transistor Sizing

• for symmetrical response (dc, ac)• for performance

Focus on worst-case

Input Dependent

Propagation Delay Analysis - The Switch Model

VDDVDDVDD

RpRp Rp

RnRn Rn

(a) Inverter (b) 2-input NAND (c) 2-input NOR

tp = 0.69 Ron CL

(assuming that CL dominates!)

What is the Value of Ron?

Numerical Examples of Resistances for 1.2m CMOS

Analysis of Propagation Delay

2-input NAND

1. Assume Rn=Rp= resistance of minimum sized NMOS inverter

2. Determine “Worst Case Input” transition(Delay depends on input values)

3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pulls

up the output node

- For 2 PMOS devices in parallel, the resistance is lower

4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in series

tpLH = 0.69RpCL

tpHL = 0.69(2Rn)CL

Design for Worst Case

Here it is assumed that Rp = Rn

Influence of Fan-In and Fan-Out on Delay

tp a1FI a2FI2 a3FO+ +=

Fan-Out: Number of Gates Connected2 Gate Capacitances per Fan-Out

FanIn: Quadratic Term due to:

1. Resistance Increasing2. Capacitance Increasing(tpHL)

tp as a function of Fan-In

1 3 5 7 9fan-in

4.0t p

tpLHlinear

quadratic

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Fast Complex Gate - Design Techniques

• Transistor Sizing: As long as Fan-out Capacitance dominates

• Progressive Sizing:

M1 > M2 > M3 > MN

Distributed RC-line

Can Reduce Delay with more than 30%!

Fast Complex Gate - Design Techniques (2)

(a) (b)

• Transistor Ordering

critical pathcritical path

• Improved Logic Design

• Buffering: Isolate Fan-in from Fan-out

Example: Full Adder

A B Ci

Co = AB + Ci(A+B)

28 transistors

A Revised Adder Circuit

A BKill

Generate"1"-Propagate

"0"-Propagate

A B Ci

24 transistors

digital integrated circuits© prentice hall 1995 combinational logic combinational logic

Documents

02 combinational logic

chapter 3 – combinational logic design -...

l2: combinational logic design (construction and · pdf...

slides4 combinational logic

combinational logic circuit

combinational circuits - dinabandhu andrews...

area complexity estimation for combinational logic...

verilog – combinational logic

digital design - combinational logic design chapter 2 -...

combinational logic design combinational functions and

combinational logic design principles. combinational...

combinational logic discussion d2.5. combinational logic...

chapter 0 - review combinational logic circuit,...

combinational logic circuits

combinational logic technologies

combinational logic design principles. combinational...

combinational logic implementation

combinational logic functions

combinational logic design

combinational logic - university of california, … ·...