customization using variable instruction sets

UCB November 8, 2001

Krishna V Palem

Proceler Inc.

Customization Using Variable Customization Using Variable Instruction Sets Instruction Sets

Krishna V PalemCTO

Proceler Inc.

2

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

Designing Instruction Sets

Choice of instructions is determined by several trade-offs– Implementation in a fixed silicon area– Ability of the compiler to exploit its presence– Trade-off between impact on cycle time vs. frequency

Implementation cost is amortized across many applications– Infeasible to tailor support for a small number of low

volume applications Reconfigurable logic enables a new degree of

freedom

3

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

Dynamically Variable Instruction Set Architecture (DVAITA)

C P

Microprocessorcore

Reconfigurable Logic

Soft Micro-architecture

Components

Compiler

Fixed ISA

• Software engineer• C programming• Algorithm Design

DVAITA ISA

Applicationspecific

Soft Processor

Fundamentally alters the hardware/software interface Synthesis

Map

Place

Off-line Construction

4

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

DVAITA

DVAITA is a “soft” ISA– Pre-synthesized, pre-placed instruction implementations

DVAITA compiler– Analysis, program transformation, and scheduling

algorithms – Compilation to a domain specific ISA– Create a customized micro-architecture at compile time

DVAITA Hardware Support Package– Analogy with Board Support Packages (BSP)– Run-time for host-FPGAcommunication– Abstraction for linking the supporting hardware/software

interfaces

5

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

DVAITA Enabled Customization

Customization at the domain level– Soft ISAs for DSP, Telecommunications, Industrial

automation and control, etc. Customization at the program level

– Tailored micro-architecture produced at compile time Customization at the operation level

– Tailored arithmetic and logic operations, for example, power vs. speed

6

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

Compiling Code Segments to Hardware

L1: for (…){L2: for (…) {

.. } ..

}……

L3: for (…){L4: for (…) { L5: for (…) {

…}..

} ..

}

• Datapath• Control • Memory• I/O Interfaces

DVAITA ISA

DVAITA ISA

• Datapath• Control • Memory• I/O Interfaces

7

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

Compile-time generation of Application-specific soft processors

ISAs can be selected on a

domain specific basis

8

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

Application-Specific Soft Processors

C P

Compiler

•C Programming•Algorithm Design

Software Engineer

Microprocessorcore

Reconfigurable Logic

ReconfigurableComputing System

(RCS)

Application-specific soft processors

Communication

Security

Networking

Soft Micro-architectureComponents

9

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

Commercial Hardware Platforms

High-end System-on-a-Chip solutions– Xilinx Virtex 2 with embedded PPC 405– Altera Excalibur with embedded ARM

Low-end System-on-a-Chip solutions– Triscend Configurable System on a Chip (CSoC) with

embedded ARM– Atmel Field Programmable System Level Integrated

Circuits (FPSLIC) with embedded 8-bit custom RISC processor

Board-level products– Mix embedded processors and commercial FPGA

solutions

10

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

More Generally Architecture Assembly

An ISA view

Synthesis and other hardware design off-line

Much closer to compiler optimizations implies faster compile time

Applications

Program

“Compiler” selects assembles and optimizes program

Dynamically variable ISA Architecture implementation

Prebuilt Implementations

Build off-line (synthesis, place

and route)

Data path Storage Interconnect

Also applicable to yield fixed implementations in silicon

11

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

Placing in Perspective

12

UCB – November 8, 2001

Krishna V Palem

Proceler Inc.

The Space for these Technologies

ASIC

CMP NP

COTSPROCESSOR

PICO

Software programmable

Designed with EDA Tools

Custom Microprocessor

CMP:

Network processor

NP:

Speed to market

Perf

orm

ance