cs 201 introduction in computer - csc121 · pdf file3.1 introduction 3.2 the map method ......

CS 121

Digital Logic

Design

Level Minimization-Gate

Chapter 3

Outline

3.1 Introduction

3.2 The Map Method

3.3 Four-Variable Map

3.4 Product of sums simplification

3.5 Don‘t Care Conditions

3.7 NAND and NOR Implementaion

3.8 Other Two-Level Implementaion

3.9 Exclusive-OR function

3.1 Introduction (1-1)

Gate-Level Minimization refers to the design task of finding an optimal gate-level implementation of the Boolean functions describing a digital circuit.

Notes about simplification of Boolean expression:

Minimum number of terms and literals in each term (minimum number of gates and inputs in the digram).

Reduce the complexity of the digital gates.

The simplest expression is not unique.

Simplification Methods:

Algebraic minimization lack on specific rules. (section 2.4).

Karnaugh map or K-map.

A Karnaugh map is a graphical tool for assisting in the general simplification procedure.

Combination of 2, 4, … adjacent squares

The relation is:

Logic circuit ↔ Boolean function ↔ Truth table ↔ K-map ↔ conical form ↔ satndrad form.

Conical form: ( sum of minterms , product of maxterms.

Standrad form: ( simplifier : sum of product , product of sum

3.2 The Map Method (1-12)

Two-variable maps:

Y’ Y

Rules for K-map:

o We can reduce functions by circling 1’s in the K-map

o Each circle represents a minterm reduction

o Following circling, we can deduce minimized and-or form.

Rules to consider

o Every cell containing a 1 must be included at least once.

o The largest possible “power of 2 rectangle” must be enclosed.

o The 1’s must be enclosed in the smallest possible number of rectangles.

Example 1:

F(X,Y) = XY’ + XY

Two-Variable maps (cont.)

From the map, we see that

F (X,Y) = X.

Note: There are implied 0s in other boxes.

This can be justified using algebraic manipulations:

F(X,Y) = XY’ + XY

= X(Y’ +Y)

Example 2: G(x,y) = m1 + m2 + m3

G(x,y) = m1 + m2 + m3

= X’Y + XY’ + XY

From the map, we can see that :

G = X + Y

Example 3: F = Σ(0, 1)

Using algebraic manipulations:

F = Σ(0,1)

= x’y + x’y’

= x’ (y+y’)

= x’ 1 1 X’

x y F 0 0 1 0 1 1 1 0 0 1 1 0

3 variables 8 squares ( minterms).

On a 3-variable K-Map:

◦ One square represents a minterm with three variables

◦ Two adjacent squares represent a product term with two variables

◦ Four “adjacent” terms represent a product term with one variables

◦ Eight “adjacent” terms is the function of all ones (logic 1).

Three-variable maps:

using algebraic manipulations: F = X’Y’Z’ + X’YZ’ + XY’Z’ + XYZ’

= Z’ (X’Y’ + X’Y + XY’ + XY)

= Z’ (X’ (Y’+Y) + X (Y’+Y))

= Z’ (X’+ X)

= Z’

Three-variable maps (cont.):

Example 1:

F(X,Y) = X’Y’Z’ + X’YZ’ + XY’Z’ + XYZ’

Example 2: F=AB’C’ +ABC +ABC +ABC + A’B’C + A’BC’

three-Variable maps (cont.)

From the map, we see that

F=A+BC +BC

00 01 11 10

Example 4 : F (x, y, z)= Σm (2, 3, 6, 7)

using algebraic manipulations:

F(x , y, z) = x’yz + xyz + x’yz’ + xyz’

= yz (x’ + x) + yz’ (x’ + x)

= yz + yz’

= y (z + z’)

00 01 11 10

Example (3-1) , (3-2) :

Example (3-3) , (3-4) :

3.3 Four-Variables Map (1-9)

4 variables 16 squares ( minterms).

On a 4-variable K-Map:

Two adjacent squares represent a term of three literals.

Four adjacent squares represent a term of two literals.

Eight adjacent squares represent a term of one literal.

Note: The larger the number of squares combined, the smaller

the number of literals in the term.

Flat Map Vs. Torus

Example 1 (3-5) :

F(w,x,y,z) = ∑ ( 0,1,2,4,5,6,8,9,12,13,14)

00 01 11 10

W’YZ’

XYZ’

F = y‘ + w‘yz‘ + xyz‘

Example 2 (3-6) :

F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

00 01 11 10

F = B‘D‘ + B‘C‘ + A‘CD‘

1 1 1 B’D’

B’C’

A’CD’

Simplification using Prime Implicants

o A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent

squares in the map .

o If a minterm in a square is covered by only one prime

implicant, that implicant is called Essential .

o Prime Implicants and Essential Prime Implicants can be

determined by inspection of a K-Map.

o Notes:

• Two adjacent 1’s form prime implicant, if they are not within a

group of four adjacent squares.

• Four adjacent 1’s form prime implicant, if they are not within a

group of eight adjacent squares and so on.

Example 1:

F(A,B,C,D) = ∑ (0,2,3,5,7,8,9,10,11,13,15)

Minterms covered by single prime implicant

ESSENTIAL Prime

Implicants

Example 1:

F(A,B,C,D) = ∑ (0,2,3,5,7,8,9,10,11,13,15)

o Essential prim implicants:BD , B’D’

o Prime implicant: CD , B’C, AD , AB’.

o The minterms that not cover by essential implicants are: m3, m9, m11.

The simplified expression is optained from the sum of the essential

implicants and other prime implicants that may be needed to cover

any remaining minterms.

o So this function can be written with these ways:

• F = BD + B’D’ + CD + AD

• F = BD + B’D’ + CD + AB’

• F = BD + B’D’ + B’C + AD

• F = BD + B’D’ + B’C + AB’

Example 2:

F(W,X,Y,Z) = ∑ (0,2,3,8,9,10,11,12,13,14,15)

1 1 1 1

X’Y X’Z’

Note: that all of

these prime

implicants are

essential.

Example 3:

F(W,X,Y,Z) = ∑ (0,2,3,4,7,12,13,14,15)

1 1 1 1

W’Y’Z’

W’X’Y

W’YZ

XYZ XY’Z’

• Essential: WX

• Prime: XYZ ,

XY’Z’ , W’Y’Z’,

W’YZ, W’X’Y ,

W’X’Z’

3.5 Producut-of-Sum simplification (1-9)

1. Mark with 1’s the minterms of F.

2. Mark with 0’s the minterms of F’.

3. Circle 0’s to express F’.

4. Complement the result in step 3 to obtain a

simplified F in product-of-sums form.

Example 1:

Simplify : F= ∑(0,1,2,5,8,9,10) in Product-of-Sums Form

0 0 0 0

AB BD’

• F’ = AB + CD + BD’

• F = (F’)’ = (A’+B’) + (C’+D’) + (B’+D)

Example 2:

Simplify : F(x, y, z) =(0, 2, 5,7)in Product-of-Sums Form

00 01 11 10

X’Z’

• F’ = XZ + X’Z’

• F = (F’)’ = (X’+Z’) + (X+Z)

3.6 Don't Cares Condition (1-4)

Sometimes a function table or map contains entries for which it is known:

The input values for the minterm will never occur, or

The output value for the minterm is not used.

Functions that have unspecified outputs for some input combinations are

called incompletely specified functions.

In these cases, the output value is defined as a “don't care” ( an “x” entry)

assumed to be either 0 or 1.

The choice between 0 and 1 is depending on the way the incompletely

specified function is simplied.

By placing “don't cares” in the function table or map, the cost of the logic

circuit may be lowered.

Example :

A logic function having the binary codes

for the BCD digits as its inputs. Only the

codes for 0 through 9 are used.

The six codes, 1010 through 1111 never

occur, so the output values for these

codes are “x” to represent “don’t cares.”

Example (3.9) : F(W,X,Y,Z) = ∑ (1,3,7,11,15)

d(W,X,Y,Z) = ∑ (0,2,5)

1 1 x x

F = YZ + W’Z

1 1 x x

F = YZ + W’X’

Example (3.9) : F(W,X,Y,Z) = ∑ (1,3,7,11,15)

d(W,X,Y,Z) = ∑ (0,2,5)

1 1 x x

F’ = Z’ + WY’

F = Z ( W’ + Y)

3.7 NAND and NOR Implementation (1-15)

Digital circuits are frequently constructed

with NAND or NOR gates rather than with

AND and OR gates.

NAND gate: a universal gate.

Any digital system can be implemented with it.

NAND Implementation

To facilitate the conversion to NAND logic, there are alternative graphic symbol for it.

NAND Implementation

Procedures of Implementation with two levels of NAND gates:

1. Express simplified function in sum of products form.

2. Draw a NAND gate for each product term that has at least two literals to constitute a group of first-level gates

3. Draw a single gate using AND-invert or invert-OR in the second level

4. A term with a single literal requires an inverter in the first level.

NAND Implementation

Two-Level Implementation

NAND Implementation

F = AB + CD

= [(AB + CD)’]’

= [(AB)’*(CD)’]’

NAND Implementation

Example (3.10): F(X,Y,Z) = ∑ (1,2,3,4,5,7)

00 01 11 10

F = XY’ + X’Y + Z

Procedures of Implementation with multilevel of NAND gates:

1. Convert all AND gates to NAND gates with AND-invert graphic symbols

2. Convert all OR gates to NAND gates with invert-OR graphic symbols

3. Check all the bubbles in the diagrams. For a single bubble, invert aninverter (one-input NAND gate) or complement the input literal

NAND Implementation

Multilevel Implementation

NAND Implementation

EXAMPLE 1:

F = A(CD + B) + BC’

NAND Implementation

EXAMPLE 2:

F = (AB’ + A’B).(C + D’)

The NOR operation is the dual of the NAND operation.

The NOR gate is anothar universal gate to implement

any Boolean function.

NOR Implementation

To facilitate the conversion to NOR logic, there are alternative graphic symbol for it.

NOR Implementation

Procedures of Implementation with two levels of NOR gates:

1. Express simplified function in product of sums form.

2. Draw a NOR gate for each product term that has at least two literals to constitute a group of first-level gates

3. Draw a single gate using OR-invert or invert-AND in the second level

4. A term with a single literal requires an inverter in the first level.

NOR Implementation

Example : F = (A+B).(C+D).E

Procedures of Implementation with multilevel of NOR gates:

1. Convert all OR gates to NOR gates with OR-invert graphic symbols

2. Convert all AND gates to NOR gates with invert-AND graphic symbols

3. Check all the bubbles in the diagrams. For a single bubble, invert aninverter (one-input NAND gate) or complement the input literal

NOR Implementation

Multi-Level Implementation

Example : F = (A B’ + A’B).(C+D’)

3.8 Other Two-Level Implementations (1-7)

16 possible combinations of two-level forms with 4 types of

gates: AND, OR, NAND, and NOR

8 are degenerate forms: degenerate to a single operation.

(AND-AND , AND-NAND, OR-OR , OR-NOR , NAND-NAND ,

NAND-NOR , NOR-AND , NOR-NAND)

8 are generate forms:

NAND-AND = AND-NOR = AND-OR-INVERT

OR-NAND = NOR-OR = OR-AND-INVERT

Nondegeneratd forms Implementation

Nondegeneraetd forms Implementation

NOR NAND OR AND 2nd level

1st level

# NAND (3.4) AND AND

NOR $ OR (3.4) OR

AND (3.6) NAND # NAND

(3.6) OR $ NOR NOR

Discussed before

Generated forms

Discuss now

AND-OR-INVERT

o AND-NOR = NAND-AND = AND-OR-INVERT

o Similar to AND-OR, AND-OR-INVERT requires an

expression in sum of products

Example: F = (AB + CD + E) ‘

OR-AND-INVERT

o AND-NOR = NAND-AND = AND-OR-INVERT

o Similar to OR-AND, OR-AND-INVERT requires an

expression in product of sums

Example: F = [(A+B) . (C+D) . E ] ‘

To Get

Output

Simplify F’ into Implements

the Function

Equivalent

Nondegenerate form

sum-of-products

form by

combining 0’s in

the map

AND-OR-

INVERT NAND-AND AND-NOR

product-of-sums

form by

combining 1’s in

the map and

complementing

OR-AND-

INVERT NOR-OR OR-NAND

Example (3.11) :

F(x,y,z) = ∑ (0,7)

AND-OR-INVERT:

F’ = x’y + xy’ + z

F = ( x’y + xy’ + z ) ‘

-----------------------------

OR-AND-INVERT:

F = x’y’z’ + xyz’

F = [ (x’y’z’ + xyz’)’ ] ‘

F = [ (x+y+z) . (x’+y’+z) ] ‘

3.9 Exclusive-OR Function (1-7)

Exclusive-OR (XOR) denoted by the symbol :

x y = xy‘ + x‘y

Exclusive-OR is equal to 1, when the values of x and y are diffrent.

Exclusive-NOR (XNOR):

(x y )‘ = xy + x‘y‘

Exclusive-NOR is equal to 1, when the values of x and y are same.

Only a limited number of Boolean functions can be expressed in terms of XOR operations, but it is particularly useful in arithmetic operations and error-detection and correction circuits.

Exclusive-OR principles:

x 0 = x

x 1 = x‘

x x = 0

x x‘ = 1

x y‘ = x‘ y = (x y)‘

x y = y x

(x y) z = x (y z)

Implementaion Exclusive-OR

with AND-OR-NOT:

x y = xy‘ + x‘y

Implementaion Exclusive-

OR with NAND:

x y = xy‘ + x‘y

= x (x‘+y‘) + y (x‘+y‘)

= x (xy)‘ + y (xy)‘

= [ (x(xy)‘ + y(xy)‘)‘]‘

= [ (x(xy)‘)‘ + (y(xy)‘)‘ ]‘

The 3-variable XOR function is equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1.

Multiple-variable exclusive OR operation = odd function : odd number of variables be equal to 1.

(A B C) = (AB‘ + A‘B) C‘ + (A‘B‘ + AB) C

= AB‘C‘ + A‘BC‘ + A‘B‘C + ABC

= ∑ (1,2,4,7)

Odd Function:

A B C D= ∑ (1,2,4,7,8,11,13,14)

Exclusive-OR function is useful in systems requiring error-detection and correction circuits.

A parity bit is used for purpose of detection errors during transmission.

Parity bit : an extra bit included with a binary message to make the number of 1’s either odd or even.

The circuit generates the parity bit in transmitter is called parity generator.

The circuit checks the parity bit in receiver is called parity checker.

Parity Generation and Checking:

Example : Three-bit message with even parity

Three-bit Massage Parity bit

X Y Z P

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

o From the truth table , P

constitutes an odd

function.

o It is equal 1 when

numerical value of 1’s in a

minterm is odd

o P = x y z

Example : Three-bit message with even parity

o From the truth table , C

constitutes an odd

function.

o It is equal 1 when

numerical value of 1’s in a

minterm is odd

o C = x y z P

cs 201 introduction in computer - csc121 · pdf file3.1 introduction 3.2 the map method ......

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