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MOS TRANSISTOR MODELING AND CHARACTERIZATION
FOR CIRCUIT SIMULATION
by
Bing Jay Sheu
Memorandum No. UCB/ERL M85/85
26 October 1985
MOS TRANSISTOR MODELING AND CHARACTERIZATION
FOR CIRCUIT SIMULATION
by
Bing Jay Sheu
Memorandum No. UCB/ERL M85/85
26 October 1985
ELECTRONICS RESEARCH LABORATORY
College of EngineeringUniversity of California, Berkeley
94720
MOS Transistor Modeling and Characterization for Circuit Simulation
Ph. D. Bing Jay Sheu Department of EECS
Chairman of Committee
Abstract
This thesis describes the development of an accurate and computationally efficient
metal-oxide-semiconductor transistor model and its associated characterization facility
for advanced integrated-circuit design. Both the strong-inversion and weak-inversion
components of the drain current are included. In order to speed up the circuit-
simulation execution time, the dependence of the drain current on the substrate bias
has been modeled with a numerical approximation. This approximation also simplifies
the expressions for the transistor terminal charges. The charge model was derived
from its drain-current counterpart to preserve consistency of the device physics.
Charge conservation is guaranteed in this model.
The transistor parameters are extracted by an automated parameter extraction
program. Circuit designers need only describe the layout geometries of the transistors
and parasitic elements to execute circuit simulation. Use of the model to analyze dev
ice characteristics from several fabrication processes has resulted in good agreement
between measured and calculated results for transistors with effective channel lengths
as small as one micron. It is anticipated that only minor enhancements are necessary
to extend this model for submicron devices.
-II-
ACKNOWLEDGEMENTS
First and foremost I thank my dissertation advisors. Prof. Ping K. Ko and Prof.
Donald O. Pederson.
I thank my M.S. thesis advisors. Prof. Paul R. Gray and Prof. Chenming Hu.
I thank Dr. Don L. Scharfetter for introducing me into the BSIM project and for his
delightful guidance over one and half years.
I am also grateful to Professors David A. Hodges. A. Richard Newton. Alberto
Sangiovanni-Vincentelli. William G. Oldham. Richard S. Muller. Nathan Cheung, and
Andrew R. Neureuther.
I thank Prof. Michael J. Klass of the Statistics Department to serveon my disserta
tion committee.
Efforts made by Ralph C.-L. Liu. Brian S. Messenger. Joseph R. Pierret. Anthony
H.-C. Fung. Min-Chie Jeng. Peter M. Lee. Dr. Tak K. Young, and Dr. Joseph B. Valdez
are highly appreciated.
Discussions with Tom Quarles. Rick Spickelmier. Resve Saleh. Jeff Burns, and Kar-
tikeya Mayaram were of great help.
Assistance from the fellow students of the CAD group, the circuit design group,
and the solid-state group is highly acknowledged.
This research was supprted by the Semiconductor Research Corporation and by the
University of California's MICRO program.
TABLE OF CONTENTS "'"'
Chapter 1 - INTRODUCTION 1
Chapter 2 - BERKELEY SHORT-CHANNEL IGFET MODEL ..... 5
2.1 MOS Transistor Modeling for Circuit Simulation - An Overview ..... 7
2.1.1 Long-Channel Devices 7
2.1.2 The Semi-Empirical Modeling Approach ..... 8
2.2 BSIM Formulation 9
2.2.1 Strong-Inversion Component 10
2.2.2 Including the Weak-Inversion Component 12
2.2.3 Parameter Pre-Processing „ 13
2.3 Model Derivation 15
2.3.1 Expansion of the Bulk-Doping Term 25
2.3.2 Channel-Charge Modeling 26
2.3.3 Numerical Approximation of the Substrate-Bias Effect 30
Chapter 3 - PARAMETER EXTRACTION 33
3.1 Automated Parameter-Extraction System Hardware 33
3.2 Parameter-Extraction Program 33
3.2.1 Program Features 36
3.2.2 Highlights of Extraction Procedures 37
3.2.3 Subthreshold Parameter Extraction ., 39
3.3 Comparison of Measured and Modeled Results 41
Chapter 4 - THE BSIM CHARGE AND CAPACITANCE MODEI 54
4.1 Capacitance Modeling for Circuit Simulation - The Theory , 54
4.1.1 Choice of State Variables 55
4.1.2 Channel-Charge Partition 57
-IV-
4.1.3 Small-Geometry Effects .....7. 5$
4.1.4 Distributed-Channel Effect „ „ 59
4.2 The BSIM Charge Model .. 64
4.2.1 The 40/60 Channel-Charge Partitioning Method ..... 67
4.2.2 The 0/100 Channel-Charge Partitioning Method ..... 68
4.2.3 The 50/50 Channel-Charge Partitioning Method ..... 69
4.3 The BSIM Capacitance Model 70
4.4 Comparison with Experimental Results « 75
Chapter 5 - SPICE2 IMPLEMENTATION 77
5.1 Basic Considerations t « 77
5.1.1 Process File Format „ 77
5.1.2 New and Modified Linked Lists 80
5.2 Implementation in SPICE2 $1
5.2.1 Functions of the Newly Added Subroutines 81
5.2.2 Modifications to the Original Subroutines $2
5.3 Program Performance 84
Chapter 6 - CONCLUSION S6
REFERENCES Sh
Appendix A- BSIM USER GUIDE •• '. 95
Appendix B - LINKED LIST SPECIFICATIONS106
Appendix C- THE TRANSISTOR SMALL-SIGNAL MODEL AND EXTRINSIC
COMPONENT MODELS j13
Appendix D- LISTING OF SUBROUTINE BSIMEQ IN SPICE2 IMPLEMENTATION ,25Appendix E - BENCHMARK CIRCUITS
13*J
-V-
Appendix F - SOURCE-DRAIN SERIES RESISTA.NCL OF LIGHTLY-DOPED-
DRAIN MOS TRANSISTORS ••-146
Appendix G - CHANNEL LENGTHS AND WIDTHS OF CONVENTIONAL
AND L1GHTLY-DOPED-DRAIN MOS TRANSISTORS 160
Appendix H- MEASUREMENT AND MODELING OF SMALL-GEOMETRY MOS
TRANSISTOR GATE CAPACITANCES182
-1-
CHAPTER 1
INTRODUCTION
Increases in the level of integration of very large-scale integrated (VLSI) circuits
are realized mainly through the shrinkage of device dimensions. With the current rapid
development of high performance metal-oxide-semiconductor integrated-circuit (MOS
IC) technologies, the minimum-feature sizes for production processes have shrunk from
10 fim in production in 1971 to 2.5 ^m in 1981 [l.l]. VLSI circuits with transistor
effective channel lengths of 1.2 fim are in volume production in 1985. Further scale
down to 0.5 fim is expected to be realized in 1990. With the present speed of technol
ogy improvement continues, the level of integration will increase from 106 transistors
per chip in the year 1985 to 107 transistors per chip in 1990. Such marvelous techno
logical advances have made possible the implementation of a whole system in a single
chip.
For efficient integrated-circuit design, computer-aided tools have become indispens
able. Currently such tools in simulation, layout, and automatic synthesis are being
heavily used. In Fig. 1.1. a selection of some of these tools available in the public
domain are shown.
The SPICE1 and SPICE2 (Simulation Program with Integrated Circuit Emphasis)
programs [1.2.1.3] has been widely accepted for circuit analysis since its introduction a
decade ago. Circuit simulation has been speeded up substantially through algorithm
mprovement and hardware enhancements in the past few years. Novel circuit-
simulation algorithms, such as the iterated-timing-analysis method [1.4] and the
\xaveform-relaxation method [1.5], promise to offer more than an order of magnitude
speed-up as compared with the conventional circuit simulator SPICE2. The dedicated-
Chap. 1
Existing Process/Device/Circuit Design
Tools in the Public Domain
process schedule
\/
SAMPLE/SIMPLE
\/
SUPREM/SUPRA/
FABRICS
NkGEMINI/MINIMOS/
PISCES
±k.TECAP/SUXES/
BSIM.extract
.^LSPICE
mask topology
impurity profile
2—D device simulation
model parameters
circuit performance
-2-
Fig. 1.1 A selection of some of the computer-aided tools available in the public
domain.
Chap. 1-3-
hardware approach, such as multi-processor based simulation schemes [1.6.1.7]. also
drastically reduces the circuit-simulation time.
Device modeling plays a important role in VLSI circuit design because computer-
aided circuit analysis results are only as accurate as the models used. It is therefore
essential to develop device models which meet the preset accuracy and computational
efficiency requirements. The SPICE2 program provides three MOS transistor models
[1.8J. The LEVEL-1 model, which contains fairly simple expressions, is most suitable
for preliminary analysis. The LEVEL-2 model, which contains expressions from
detailed device physics, does not work well for small-geometry transistors. The
LEVEL-3 model represents an attempt at pursuing the semi-empirical modeling
approach, which only approximates device physics and relieson the proper choice of the
empirical parameters to accurately reproduce device characteristics.
In this dissertation, the development of a simple and accurate short-channel MOS
transistor model, the Berkeley Short-Channel IGFET Model (BSIM) [1.9], and its associ
ated characterization facility for IC process-oriented circuit designs are described. The
BSIM builds upon AT&T Bell Labs' CSIM with substantial enhancements [1.10]-[1.12].
The characterization facility includes a fully automated parameter-extraction program
and implementation of the complete model, which includes expressions for dc and capa
citance characteristics and extrinsic components, in SP1CE2. Since the fully device-
physics-oriented approach usually makes parameter extraction particularly difficult, the
semi-empirical approach was adopted in developing BSIM to cope with the rapid
advance of technology and to make automated parameter extraction possible. An
analytical representation with 17 electrical parameters per device size was found to be
adequate for modeling the dc characteristics. The parameter-extraction program gen
erates a process file which contains a set of parameter values for circuit analysis. Cir
cuit designers need only describe the layout geometries of transistors and parasitic ele-
Chap. 1 _4-
ments to execute circuit simulation. Use of BSIM to analyze device characteristics from
several NMOS and CMOS processes has resulted in good agreement between measured
and modeled results with eflfective channel lengths down to 1 fim. Only minor
enhancements are necessary to extend BSIM for submicron devices.
The BSIM is simulator-independent. Implementation of BSIM in SPICE2 and
SPICE3 has been finished.
CHAPTER 2
BERKELEY SHORT-CHANNEL IGFET MODEL
LIST OF SYMBOLS
a conductance degradation coefficient.
C0 gate capacitance per unit area.
AL channel-length reduction.
AW channel-width change.
Ec critical field for carrier velocity saturation.
g coefficient of average body effect on drain current.
Ids drain current.
Idsat drain current in the saturation region.
Kj body-effect coefficient including short- and narrow- channel effects.
K2 source and drain depletion charge sharing effect coefficient.
Leff effective channel length.
LMK masked-level channel length.
NA substrate doping concentration.
Nss surface state density.
n} intrinsic carrier concentration.
Tox gate-oxide thickness.
U0 vertical field mobility degradation coefficient.
Uqb sensitivity of U„ to the substrate bias.
Uoz U0 at zero substrate bias.
Ui carrier velocity saturation coefficient.
-5-
Chap. 2 _5_
U1B sensitivity of Vi to the substrate bias.
U1D sensitivity of Ui to the drain bias at Vds«=Vdd.
UiZ Ui at zero substrate bias.
Vbs substrate-to-source voltage.
Vqs drain-to-source voltage.
Vdsat saturation drain voltage.
Vra flat-band voltage.
VGB gate-to-substrate voltage.
Vgs gate-to-source voltage.
Vth threshold voltage.
Vt0 threshold voltage for zero drain and substrate biases.
Weff effective channel width.
WMK masked-level channel width.
Mo intrinsic surface mobility.
Mz fio at zero substrate and drain biases.
Mzb sensitivityof /x0 to thesubstrate bias at VDS =0.
Ms Mo at zero substrate biasand VDS = VDD.
Msb sensitivity of m<> to thesubstrate bias at VDS =VDD.
Msd sensitivity of Mo to the drain bias at VDS =VDD.
<f>s surface potential at strong inversion.
0ms gate-to-semiconductor work function difference.
7) drain-induced barrier lowering coefficient.
T)z 7) -at zero substrate biasand VDS = VDD.
V)z sensitivity of 7) to the substrate bias.
t)d sensitivity of 17 to the drain voltage.
Chap. 2-7-
2.1. MOS Transistor Modeling for Circuit Simulation - An Overview
Many articles on MOS transistor modeling have appeared in the literature [2.1]-
[2.10] and efforts to model ever smaller and more complex MOS transistors continue ata rapid pace.
2.1.1. Long-Channel Devices
We begin by discussing the first-order model, used in the early P-channel MOS
transistor analysis, where
Ids =&( Vgs- Vt- ^-) VDS (2.1)below saturation and
IDs=-|Uvcs-Vt)2 (2.2)above saturation, and here the threshold voltage (Vt) is a constant. Saturation occurs
when sufficient drain voltage (VPF) is applied to deplete the channel at the drain, and
vPF=vGS-vt.
The first-order model neglects a fundamental effect, which is the consequence of
finite resistivity of the substrate. This bulk-doping or body effect acts as a back gate.
That is. after the channel (in an N-channel transistor) is established, an "n-p" junction
is formed at the back side of the channel. The p value is. of course, the substrate dop
ing.
As the current flows in the channel, the "I-RH drop in effect induces a reverse bias
across this n-p junction. The depletion-region charge associated with this back gate
must be accounted for according to Gauss' law. By using the gradual-channel approxi
mation, a charge term can be derived that varies as the square root of potential. When
the expression is integrated along the channel from the source to the drain, with poten
tial as the running variable, it leads to the following improved first-order model [l]:
Chap. 2 -8-
V& 2V2q€siNAIds- 0o (VCs-0s-VFB)VDS--^.-
3C0
*[(Vk +0s-Vbs)3/2-(0s-V|s)3/2]). (2.3)The 3/2 power terms result from the integration of the square-root dependent bulk-
doping effect evaluated at the two integration limits. Furthermore, the threshold vol
tage. i.e.. the gate bias at which the above expression starts to apply, is
V, =Vt0 +V2qc6"NA IVfc=V^- V£ I (2.4)where Vt0 is the threshold voltage for zerosubstrate bias.
Similar to the first-order derivation, saturation occurs when the channel at the
drain is depleted. Hence, the saturation voltage. Vdsat. equals to the gate-to-source
voltage minus the threshold voltage at the drain terminal. For values of VDS greater
than VDSAT. IDS is constant (saturated) at the value Idsat-
For many years this improved first-order theory was quite adequate for accurate
integrated-circuit design. Problems began to appear as more and more two-dimensional
effects become prominent in small-size transistors.
2.1.2. The Semi-Empirical Modeling Approach
Fully physics-oriented models completely derived from device physics are either
mathematically too complicated or do not compare well with measured results. If all
the governing physical effects are incorporated, expensive numerical solutions are
required [2.11.2.12]. An MOS transistor model has to be evaluated thousands of times
during circuit simulation. This renders direct applications of the computationally
inefficient fully physics-oriented models impractical for circuit simulation. In addition,
fully physics-oriented models evolve behind the integrated-circuit process.
Another plausible solution is the table look-up approach [2.13] which directly
stores measured drain-current data for circuit simulation. While this approach may
Chap. 2 g_
sound attractive, it suffers from several fundamental problems. First, it is highly
desirable to be able to evolve the proper device sizes while evolving the design. The
direct table look-up approach assumes the number of device sizes to be employed in a
design is known and small and the I-V characteristics are available. Second, interpola
tion between points assumes noise-free and glitch-free data, neither of which can be
guaranteed. Third, no simple way to include effects of process variations in the simula
tion. In addition, enormous memory space has to be dedicated to the storage of the
multi-dimensional arrays needed to model the characteristic dependence of various
biasing conditions.
MOS transistor models widely used in circuit analysis are essentially semi-
empirical in nature. Terms with strong physical meaning are employed to model the
fundamental physical effects while parameters are judiciously introduced to embrace
subtle device characteristics. This approach serves best for circuit-analysis purposes
especially as two- and three-dimensional small-geometry effects become more impor
tant.
2.2. BSIM Formulation
The Berkeley Short-Channel IGFET Model (BSIM).[1.9]. a simple and accurate
short-channel MOS transistor model, has four important features. First, it is based on
solid understanding of device physics. Second, the model formulation is very simple,
which makes it suitable for the simulation of both digital and analog circuits. Third,
the model can be easily enhanced to include new effects. Fourth, the model parameters
for a family of devices can be obtained automatically by a dedicated parameter-
extraction program which generates a process file. In a circuit simulator, the electrical
parameters for each device can be calculated from size-independent parameters, which
are contained in a process file, and the dimensions of the devices.
Chap. 2 -10-
The formulation of BSIM is based on the device physics of small-geometry MOS
transistors. Special effects included are:
. vertical field dependence of carrier mobility
. carrier velocity saturation
drain-induced barrier lowering
. depletion charge sharing by the source and drain
non-uniform doping for ion-implanted devices
. channel-length modulation
. subthreshold conduction
. geometric dependencies
The eight drain-current parameters which directly appear in the threshold-voltage
and drain-current expressions are:
VFb. the flat-band voltage,
#s- the surface-inversion potential.
Klf the body-effect coefficient.
K2. the source and drain depletion charge sharing coefficient.
7). the drain-induced barrier lowering coefficient.
U0. the vertical field mobility degradation coefficient.
Ult the velocity saturation coefficient, and
Mo» the carrier mobility.
2.2.1. Strong-Inversion Component
(A) Threshold Voltage
The first five drain-current parameters. VFB. <f>s. K,. K2. and 7). model the thres
hold voltage:
Chap. 2-11-
Vth =Vra +0s+Ki V 0s- VM - K2(0S - Vbs) - -nVos (2.5)Parameter K2 is equivalent to parameter y in textbook models [2.14.2.15]. The K! and
K2 terms together model the non-uniform doping effect. In addition to the drain-
induced barrier lowering effect. 7) also partially accounts for the channel-length modulation effect.
(B) Drain Current
Another three drain-current parameters. U0. U2 and fi0. appear in the drain-
current expression. In order to speed up circuit-simulation execution time, the 3/2
power dependence of the drain current on the substrate bias has been replaced by the
numerical approximation proposed by Poon [l.lOHl.12]. The drain-current expres
sions in various operation regions are summarized below.
(1) Cut-Off Region [ VGS <Vth ]:
!ds = 0. (2.6)
(2) Triode Region [VGS >Vth and 0 <VDS <VDSAT ]:
where
and
Ids—
WC _
Mo __L__Ll +Uo(VGS-Vth)J * Ux
U + -t— VDSJ
(vGS-vlh)vDS-|-vD2s . (2.7)
a=l+ g^i_2V0s-Vbs ' (2"8)
g X 1.744+0.8364 (0S-VBS) * (2-9)
(3) Saturation Region [VGS ^ Vth and VDS ^VdsAT ]:
Chap. 2 -12-
where
and
c0^-(vGS-vth)2i- "0 . ° L '™ — (2.10)W ll + U0(Vcs-Vth)J 2TK '
_ l + ve + Vl + 2ve Vcs-VthK= ^ 1. W--^-. (2.11)
_ U, (Vos-Vu)Vc = -j- • j . (2.12)
The body-effect coefficient "a" makes BSIM a close numerical approximation of thestan
dard textbook model over a reasonable range of VDB and Vps. Detailed derivation of
the expression for "a" can be found in Section 2.3.3.
2.2.2. Including the Weak-Inversion Component
When the gate voltage is below the threshold voltage, the semiconductor surface is
in weak inversion and the corresponding drain current is called the subthreshold
current. It is particularly important to include the subthreshold conduction model in
the analysis and designs of low-voltage, low-power circuits.
The diffusion-dominated drain current diminishes exponentially with decreasing
gate voltage when the transistor is biased in the weak-inversion region. Previous
SPICE2 MOS transistor models include subthreshold conduction by matching the
strong-inversion component with the weak-inversion component at a transition point
close to the threshold voltage [1.8]. Discontinuity of drain-current derivatives exists,
as has been pointed out by Antognetti [2.16], which jeopardizes the convergence of the
simulation. Proper matching of the strong-inversion component and the weak-
inversion component is not a trivial task because it has to be done on a multi
dimensional basis with respect to the gate, drain, and substrate biases. In BSIM. a sim
ple and accurate approach is employed [2.16]. The total drain current is modeled as the
linear sum of a strong-inversion component and a weak-inversion component, given by
Chap. 2 -13-
^u, = Ids,, + Ids^ • (2.13)
Ids,, is the strong-inversion component as described before. The weak-inversion com
ponent Ids^ can be expressed as
Idsw« - 1—+T— • (2.14)
where
and
lexp t *limit
=Mo C0 ™(il y e18 e"2^^ [1- e"VDs(^r) ]. (2.15)L q
MoQ w ,. kT .2 ,. _r.ilimit = —=— *-r- *(3 ) . (2.16)
z l q
The factor e18 is chosen to achieve best fits in the subthreshold characteristics with
minimum effect on the strong-inversion characteristics [2.17]. Three subthreshold
parameters. n0. nB. and nD. are used to model the subthreshold-slope coefficient.
n = n0 + nB VBS + nDVds . (2.17)
This approach does not introduce any discontinuity in the drain current and first
derivatives, and thus does not hamper convergence in circuit simulation.
2.2.3. Parameter Pre-Processing
(A) Conversion from Size-Independent Parameters to Electrical Parameters
Figure 2.1 shows the data flow in the process-oriented circuit simulation. In a
process file, for each device type, there are 54 size-independent parameters used to find
the 17 size-dependent electrical parameters. At the data structure set-up stage, the
simulation program stores 17 electrical parameters for each transistor according to the
formula:
Pl PwP=P<> +I ^TT + w ^TuT • (2.18)Lmk ~ AL WMK - AW
This data-processing step only needs to be done once. LMK and WMK are masked-level
Chap. 2
devicesizes
ciruittopology
[process-file j
\/
calculate deviceparameters foreach transistor
\L
transistor model
evaluation
(
ik
circuitsolution
simulationresults )
. Parameter" Pre-Processing
Fig. 2.1 Data flow in the process-oriented circuit simulation.
-14-
Chap. 2 _15_
channel length and width, while AL and AW are net size changes due to various fabrica
tion steps. The three components. P0. PL and Pw. of each electrical parameter P
represent respectively its offset value, channel-length sensitivity, and channel-width
sensitivity. For the subthreshold conduction, there are nine additional size-independent
parameters in the process flle.from which three subthreshold parameters per transistor
can beobtained. Subthreshold parameters are also processed using Eq. (2.18).
(B) Reduction from Bias-Independent Parameters to Drain-Current Parameters
At the model-evaluation stage, for each transistor the 17 electrical parameters are
mapped to 8 drain-current parameters. VFB . 0S . &i. K2 are kept intact. The rules to
map U0. Ui. T). and Mo are listed below:
U0 = Uoz + U0B Vbs . (2.19)
U1 = U1Z + U1BVBS + U1D(VDS-VDD). (2.20)
t) = 1)2 + 1)11 VBS + ^d ( VDS - VDD ) . (2.21)
Parameter Mo is obtained by quadratic interpolation through three data points. fi0 at
VDS = 0. fi0 at Vqs = VDD. and the sensitivity of fi0 to Vqs at VDS = VDD. with
Mol(atvDS =o) = Mz + MzBVBS . (2.22)
and
Mo I(at vDS =vDD) = Ms + Msb Vbs • (2.23)
A second-order polynomial function is used.
23. Model Derivation
The BSIM builds upon AT&T Bell Labs* CSIM [l.11.1.12]. An idealized N-channel
MOS transistor is illustrated in Fig. 2.2. The relationship between the electric field
(Eox) in the oxide, the gate voltage with respect to the substrate potential (VGB). and
the electrostatic potential at the oxide-semiconductor interface (Vsur) can be understood
by considering the energy band diagram in Fig. 2.3. Summing up the voltages on both
Vox
m
'GB
k'////7///X^-\'ox
CONDUCTION BAND
MIDGAP
Fig. 2.3 An energy band diagram.
FERMI LEVEL
VALENCE BAND
Otrs»
V
-4l
Chap. 2 -18-
the gate and the semiconductor side gives
Vox +Xm =VCB +<f>t +̂ - Vw +X, . (2.24)where Xm and Xs are. respectively, the gate and semiconductor work functions. Vox is
the voltage across the oxide, and Eg is the bandgap energy. The gate-to-semiconductor
work function difference (0ms) is defined as
0«nS =Xm - X, - 0f - *L . (2.25)Combining Equations (2.24) and (2.25). we obtain
Vox = Tox Eox = VGB - Vnr - 0ms . (2.26)
where Tox is the gate oxide thickness. To determine the relationship between E„x and
the charge in the semiconductor, let us assume:
(1) The gate-oxide thickness is much smaller than the channel length. This assump
tion implies that Eox is perpendicular to the gate plane.
(2) The horizontal component Ey of the electric field in the semiconductor at the
oxide-semiconductor interface is much smaller than the vertical component Es.
This assumption is reasonable in the region where the channel charge Qc is sub
stantial, but it is incorrect in the velocity-saturation region where Qc is small.
Our main interest is to compute the drain current which is proportional to the
integral of Qc along the channel. In the velocity-saturation region, where the
above assumption is invalid, the contribution to the integral is small. Hence, this
assumption is reasonable for drain current computation.
By Gauss' law and Assumptions 1 and 2, one obtains
€s ^ = €ox Eox + CL . (2.27)
where €ox and €s are the dielectric constants of the oxide and the semiconductor, and
Qss is the surface charge. The vertical electric field Es consists of three components.
€sEs = Qc + Qb + €sE1 . (2.28)
Chap. 2 -1Q-
where Qt> is the depletion charge in the semiconductor and. using the abrupt junction
approximation, is given by
Qb =V 2q€8NAVsur . (2.29)For short-channel devices, this expression is modified due to the influence of the source
and drain junction fields. The vertical electric field Es in Eq. (2.28) contains a third
component Ex which originates from the drain and will be discussed in detail later.
A qualitative expression for the bulk charge can be derived by considering an MOS
structure where alternatively the source and drain, and the gate are ignored (Fig. 2.4(a)
and (b)). These diagrams illustrate the influence of source and drain junction fields on
the bulk charge. According to Gauss' law (Fig. 2.4(a)). the electric field Eox at the
oxide-semiconductor interface will be balanced by the surface charge Qss. the channel
charge Qc. and the negative charge Qb in the depletion region (A) of the substrate. In
the absence of the gate (Fig. 2.4(b)). the electric field Ej at the junction will be balanced
by the charge in the depletion layer (B) near the junction. Now consider the complete
structure where the drain, source, and substrate are at the same potential'and a positive
voltage is applied to the gate as shown in Fig. 2.4(c). The depletion charge shown in
area (C) have to balance both the electric field Eox coming in from the oxide-
semiconductor interface and Ej due to the source or drain to the substrate junction. Let
a fraction, t. of the charge (C) be used to balance Ej. Since this fraction of the charge
will not be available to balance Eox. one could say that the doping of the substrate is
effectively lowered. This fraction t will depend on the position along the channel. As
an approximation, t should be proportional to the ratio of the charge in area (C) to the
total depletion charge of 2Xj /L. Since Xj is proportional to lAy/N^. t must be propor
tional to 1/(LVNa ). Therefore, the effective fraction of the charge f(L,NA) available
to balance Eox can be expressed by
Chap. 2
GATEJ, | EOX |
SOURCE
Ej
___JL_,
SOURC
J
p*
I'
*i
G>
09
GATE
i | EOX | |
®
-20-
| OXIDE
v
OXIDE
Jl DRAINEU>1B
Fig. 2.4 Diagrams illustrating the effect of drain and source junction fields.(a) The drain and source being ignored.(b) The gate being ignored.(c) The complete structure with the drain, source, and substrate at the same
potential.
Chap. 2 _21_
f(W=1-L7?ir- «"»where K^ is a constant. A more elaborate function for f(L.NA) and a more rigorous
derivation can be found in [2.18] and [2.19] which show that f(L.NA) isalso a function
of Vbs- However, we found that the additional Vbs dependence tends to complicate the
formulation and does not add much accuracy to the model. With the modified charge.
Eq. (2.28) becomes
€s E, = Qe + f(LJM) v/2q€sNAVsur. (2.31)
To derive the third component Ex of the electric field Es. let us consider the case
where Vqs is zero but VGB and V^ are non-zero. The substrate isdepleted according to
the solution of the Poisson equation. When Vds is non-zero, an additional potential
will be imposed in the region already depleted. Since no additional charge appears in
the Poisson-equation solution for zero drain bias, this additional potential will satisfy
the Laplace equation.. This Laplace equation can be solved under certain simplifying
assumptions and the solution gives the additional electric fields as shown in Fig. 2.5.
These electric fields terminate at the channel and induce additional channel charge
which enhances the drain current and results in a finite output conductance in the
saturation region.
The following approximations are made to derive a simple expression for Et.
(1) The source and drain junction depths are small compared to the channel length.
(2) Approximate boundary conditions for the Laplace equation, with solution denoted
by VlP are Vx= 0 at the oxide-semiconductor interface and V! = VDS at the drain
region. This approximation is illustrated in Fig. 2.6.
By substitution, it can be shown that
0vi = vds — (2.32)
satisfies the Laplace equation in cylindrical coordinates.
GATE
OXIDE
SOURCEj
DEPLETION EDGE
Fig. 2.5 A diagram illustrating the drain modulation effect.
ofcr
to
Chap. 2
SOURCEki i t i i ir
/Yfco
» DRAIN3 I J 1 l 3 1 I I If*
\
-23-
=v,DS
Fig. 2.6 A diagram illustrating the simplified boundary condition for the Laplace
equation.
Chap. 2
d2Vi
1dr2 )+1
r
dV!
dr+
1
7
d2V,
de2= 0.
-24-
(2.33)
and the boundary conditions. Differentiating Vi with respect to y at the source, one
obtains
E, = -DS
ttL(2.34)
With the addition of E^ Eq. (2.31) becomes
€s E,= Qc + f(L.N) 7 2 q NA Vsur + €s Ex. (2.35)
Combining Eqs. (2.26). (2.27). and (2.35). one can express Qc in terms of VCB and V^
as
Qc =C0 [vgb-V^-Vfb-K! Vvsur J-c.Elwhere
VFB - 0ms _Qss
and
' K, =f(L.N)- ^y^A.When the surface is inverted, the surface potential V^ is approximately given by
Vsur = 0n + <f>s ~ VBS •
where 0n is the electron quasi-Fermi level. Then Eq. (2.36) becomes
(2.36)
(2.37)
(2.38)
(2.39)
Qc = c0 <VGS-</>n-0s-VFB)-K1 J<f>n-VES + <f>s - €s Et . (2.40)
where
VGs = Vgb + Vbs. (2.41)
To derive an expression for the drain current, the current flow is assumed to be
parallel to the v-axis such that
and
d0ndx
= 0. (2.42)
Chap. 2-25-
J = q fi0 nd0n
(2.43)
where fi0 is the electron mobility and n is the electron density. When Eq. (2.43) is
integrated with respect to x and z. one obtains
lDs = /*oWQed0,
dy (2.44)
Integrating Eq. (2.44) with respect to y and 0n.
'DS
Ids / dy =fi0 Wf Qe d0n . (2.45)o o
Note that if channel shortening due to the finite extent of the drain depletion region is
included, the upper limit is accordingly reduced.
Bycombining Eqs. (2.40) and (2.45). the drain current is given by
'OS
Ids =0 / [(VGS - <f>a - 0s - Vra) - Kj V0n +0S - Vbs + r) VDS] d0n . (2.46)o
where 0 is the conductance coefficient and tj is the drain-induced barrier lowering
coefficient.
When Eq. (2.46) is integrated with respect to 0n in the triode region, one obtains
Ids = /3 (Vgs-0s- Vra) VK +(t, - ^)V&- | K, [(Vos +0s- VBS)3/ 2
- (0s-VBS)3/2]) (2.47)Note that Eq. (2.47) is exactly the Ihantola-Moll model [2.1] if r\ =0 and
*M = v/2q€siNA/C0. i.e.. f(L.NA) = 1.
23.1. Expansion of the Bulk-Doping Term
The function
F(VDS.^S-VBS)=| [(Vds +0s-VBs)3/2-(0s-Vbs)3/2 (2.48)
can be approximated numerically in the range 0 V < VDS < 10 V and
Chap. 2 -26-
0.7 V <0S - Vbs <20.7 V by
F(VDS.0S-VBS)= v/0S-VBSVDS+a/2fg<^DS . (2.49)V 0S ~ VBS
where
8=*" 1.744 +0.8364 (0S - Vbs ) (2'50)The details of this approximation are discussed in Section 2.3.3. The drain current in
the triode region can be expressed as
lDs =i3[(VCs-Vth)Vre-.iv&] (2.51)
where
Vth = Vra +0s + Kx V 0s-VBS ~ K2 ( 0S- Vbs ) - t) VDS . (2.52)and
a=l +— sKi__2 V 0s — VBS
The factor "a" given by Eq. (2.53) represents the bulk-doping effect. The origin of the
K2 term has already been explained.
23.2. Channel-Charge Modeling
After inserting Eqs. (2.52) and (2.53) into Eq. (2.40). the channel-charge expres
sion has the simplified form
Qc = -Co(VGS-Vth-a0n). (2.54)
If the continuos velocity-saturation characteristic (see Fig. 2.7) [2.20],
MoEyv = -, „ . with v • v^ =fiQ Ec when Ey • infinte .
(2.55)+ *L
is used in the integration of Qc. one finds the drain-current expression in the triode
region to be
Chap. 2
<ft
£io8O Electron in Si
yGS-v*hincrease
105Electric Field (v/cm)
Kf
Fig. 2.7 Carrier velocity versus electric field [2.20].
-27-
Chap. 2
Ids = 0 (VGS-Vth-Itb lDS ^sat ) Vos — •=- Vds
where
Ksat ""Wv^tQ
Eq. (2.56) can be rearranged as
where
Ids =0
( 1+ -± VDS )
Ur
1 =0 Rsat •
(Vcs-Vt^Vos-i-Vfe
-28-
(2.56)
(2.57)
(2.58)
(2.59)
The conventional definition of saturation voltage. VdsAt. is obtained as from Eq. (2.54)
with Qc = 0. This condition is not realistic for modern short-channel devices. A more
realistic assumption is that at the point in the channel where 0n goes to VDSAT the chan
nel current is limited by velocity saturation, i.e..
IdsatQc = -
Wv= - Q ( VGS - Vth - a VrDSAT ) (2.60)
sat
Substitution of the above expression into Eq. (2.54) yields an upper limit for the
integral in Eq. (2.46) as
*» ' Vdsat = - [( VGS - Vth )- IDSAT Rsat ] (2.61)
By carrying out the integration in Eq. (2.46) with the new upper limit, the following
expression for the drain current in the saturation region can be obtained.
Idsat =0[(VGS - Vth - IDSAT Rsat) VDSAT - L^L ]. (2.62)
Eq. (2.62) can be rearranged as
Idsat - yj ( VGS - Vth - IDSAT k^R^t )2 . (2.63)
which is aquadratic equation for IDSAT. To facilitate comparison with the usual expres
sion, we define
Chap. 2
i _0(vGS-vth)2Wt" 2IKlDSAT
where K is obtained by equating Eqs. (2.63) and (2.64). i.e..
a
or
_ 1+ ve + V 1+ 2 vcK =
where
= Ui . (Vbs~Vth)e X a
If vc «1. then
L a
If vc »l.then
K
and
Ui . (VGS-Vth)L 2a
L
(VGS-Vth)2
my
-29-
(2.64)
= 0. (2.65)
(2.66)
(2.67)
(2.68)
(2.69)
Idsat *C0 Vsat W ( VGS - Vth ) . (2.70)
The above expression is well-known, and states that in the limit of carrier velocity
being fully saturated at v^, the saturation current is linear instead of squared with
respect to ( VGS - Vth ). and that its value is independent of the channel length.
One can obtain the saturation drain voltage from Eqs. (2.61) and (2.64).
(VGS-Vth)V dsat-
VK (2.71)
U,In the case of — •( VGS - Vth ) « 1.
DSATVGS-Vth
(2.72)
UIn the case of -yi •( VGS - Vth ) » l.
Chap. 2 -30-
w— |2(^-v^.^1/2. (2.73)a Ux
23.3. Numerical Approximation of the Substrate-Bias Effect
The aim here is to find an accurate approximation of F(Vds . 0s —V^) over a rea
sonable voltage range of Vqs and (0s-Vbs) [1.10]-[1.12]. For convenience, let
VA = 0s —Vbs • The function
F(Vos.VA)=! [( V,* +VA )3'2 - (VA )3" ] (2.74)can be expanded as
F(V0s.VA) =VvIVDS+^^. +.... (2.75)V VA
The above expansion is invalid when VA is much greater than V^. To alleviate this
problem, the expansion is changed to
F(vDS.vA) =VvTvDS+^i8V& (2?6)v VA
where g(VA) is determined by requiring the expansion in Eq. (2.76) to give the best fit
to F(VDS . VA) in the desired voltage range.
The value of VA are considered in the range 0.7 V to 20.7 V at 2-V increments.
For each fixed VA. a parameter g is determined such that the expansion
VvIvDS+^£lBLWA
will give the best fit to F(VDS ,VA) in a least-square sense, over a range of VDS from 0
to 10 Vat 0.5-V increments. It is found that g can be accurately expressed as a func
tion of VA in the following form.
1 =Pi +P2VA (2.77)1-g
where ?t and P2 are determined by a least-square fitting over the range of VA.from 0.7
to 20.7 volts. The results are
Chap. 2 -31-
Pi = 1.744 (2.78)
and
P2 = 0.8364 (2.79)
The root-mean-square error of the approximation in Eq. (2.76) using the above value of
Vi and P2 is 2% and is illustrated by Fig. 2.8.
Chap. 2
60
50
40
<0
^? 30
u. 20
— FUNCTION
o APPROXIMATION
rDS (V)
-32-
0S-Vrs =2O.7V
Fig. 2.8 Approximating the funciion F( VK .0S - VBS )
-33-
CHAPTER 3
PARAMETER EXTRACTION
A fully integrated computer-aided-design approach is essential for efficient design
of complex VLSI circuits. Historically, the interface between process characterization
and circuit simulation has been one of the weakest links. To theend. an integrated sys
tem for automated extraction of BSIM parameters has been developed that serves
efficiently as this interface. With test devices available on wafers, the extraction pro
gram extracts parameter values and forms a process file for circuit analysis. Figure 3.1
shows the role of such an integrated system in the advanced integrated-circuit design.
3.1. Automated Parameter-Extraction System Hardware
A schematic diagram of the parameter-extraction system hardware is shown in
Fig. 3.2 [3.1]. The system consists of three major elements: an H-P 9836 desktop com
puter, an H-P 4145A semiconductor parameter analyzer, and an Electro-glass 2001X
fully-automated probe station. The H-P 9836 computer acts as the system controller
through an IEEE-488 interface bus. Data transfer between the H-P 9836 and a host
computer is via a RS-232 bus. The system also includes an option of using a manual
probe station. This alternative is particularly useful in developing new software
features. An H-P ThinkJet graphics printer supplies hard copies of measured and
extracted results.
3.2. Parameter-Extraction Program
Global optimization techniques have been widely used in conventional MOS
transistor parameter-extraction programs [3.2]-[3.5]. In general, the quantity to be
Chap. 3 -34-
Fig. 3.1 A fully integrated approach for computer-aided parameter extraction andcircuit design.
Chap. 3
HP 9836computer
RS-232
\/
VAX-11/780
automated/manualprobe station
IEEE 488 bus
HP thinkjet printer
-35-
SMU1-4
Fig. 3.2 Schematic diagram of the fully automated parameter-extraction system.
Chap. 3 -36-
minimized is the norm of the error vector which can be written in the form [3.2]
Ii(p)-Ii' *i if(P)i i2 = Z«p)2=L
i i maxOjUo)
Here p is the parameter vector to be optimized and f(p) is the error vector between the
measured drain current. 1/. and the calculated value. Ij. at the ith data point. User
input Io determines whether a relative or absolute error is used.
The solution obtained by a global optimization technique is just a combination of
parameter values that minimize the norm of the error vector, with no regard to the
physical meaning. While the global optimization approach applies to single transistor
characteristics well, it possess some difficulties in the extraction of size-independent
parameters. The BSIM extraction program employs a different approach. The local
extraction technique is used. Only related parameters are extracted together, instead of
letting all the parameter values change on the fly as is done in the global fitting
approach. Therefore, development of a process file which contains size-independent
parameter values is simple and straightforward.
3.2.1. Program Features
The extraction software is written in H-P Pascal on the H-P 9836 computer, and is
partitioned into six major-modules [3.1]:
. automatic prober control
. device measurement control
. parameter extraction -
. process file development
. interactive graphics
. menu and display handling.
Measurements are fully program-controlled. The only inputs from the user are the
probe file, which contains device-layout information, and the extraction voltage range.
(3.1)
Chap. 3 -37-
Parameter extraction does not depend on any initial guesses nor parameter bounds. The
capability to develop a process file is also included in the parameter-extraction program.
After devices of different sizes are measured and characterized, a process file is formed.
The process file can then be transferred to a host computer for circuit simulation.
Salient features of the extraction program are summarized below:
(1) modular: This makes maintenance and updating simple.
(2) efficient: It only takes three minutes to extract strong-inversion parameters per
transistor.
(3) accurate: Errors less than 4% for different transistor sizes and bias conditions have
been achieved.
(4) user-friendly: It is menu-driven. Jobs can run interactively or in the batch mode.
(5) flexible: Four different operation modes are available. These include the fully
automatic mode, semi-automatic mode, manual probe-station mode, and single-
device mode.
(6) physical: Related parameters are extracted together. Extracted parameter values
reflect their original physical meanings. This makes BSIM and the associated
parameter-extraction program an excellent tool for statistical studies of transistor
characteristics [3.6]-[3.8].
3.2.2. Highlights of Extraction Procedures
Figure 3.3 shows the flowchart of the whole program. Prior to the real parameter
extraction, a series of functionality tests are performed to identify any defect devices or
connection problems. Then, measurements of drain current corresponding to various
bias conditions are carried out. Measured results are stored for the next step which
extracts parameter values from the data. When the above procedures have been done
for all devices on the same die. a process file is formed. Once the process file is created.
Chap. 3
BSIM EXTRACTION PROGRAM FLOWCHART
IINITIAL STATUS INPUTS
MEASURE DEVICE
PARAMETER EXTRACTION
CREATE PROCESS FILE
I-V PLAYBACK
PARAMETER PLOTS
EXIT?
YES
ERASE TEMPORARY FILE
J
Fig. 3.3 Flowchart of the whole program.
-38-
Chap. 3 -39-
the user can select on-line comparisons of measured and modeled results. Plots of
extracted parameter values versus transistor channel lengths and widths can also be
generated [3.9].
The flowchart for the parameter-extraction subroutine is shown in Fig. 3.4.
Threshold voltage related parameters, together with low field parameters, are first
extracted when small drain biases are applied to the transistor. The rest of the parame
ters are extracted when large drain biases are applied to the transistor. Additional
information corresponding to a medium drain bias is used to refine the extracted param
eter values, which makes the set of parameter values a good representation of the
transistor characteristics over the whole bias range. Extraction of subthreshold param
eters is implemented as an option. It can be activated after the extraction of strong-
inversion parameters is finished.
A detailed description of the theory and algorithms used in the parameter-
extraction program and a complete user's guide can be found in [3.10].
3.2.3. Subthreshold Parameter Extraction
To extract subthreshold parameters, transistor subthreshold swings are character
ized under different drain and substrate biases. Then, three subthreshold parameters.
n0. nB. and nD. are fitted to the measured results with the linear-least-squares method.
The fact that the subthreshold-swing does not change too much makes the extraction
task simple. Additional results of subthreshold parameter extraction can be found in
[2.17].
Since the threshold voltage appears in the exponential term of the subthreshold
conduction expression, the success of the subthreshold conduction model highly
depends on the accurate determination of transistor threshold voltage.
Chap. 3 -40-
EXTRACTION ROUTINE FLOWCHART
1
LINEAR
REGION
ANALYSIS
VDS = 0.1. 0.2 V
SATURATION
REGION
ANALYSIS
VDS = 0.9VDD. VDD
VDS = 0.4VDD
DETERMINE BETA(VDS.VBS),VTH(VDS.VBS).UO(VDS.VBS)
DETERMINE PHIF2(VDS).VFB(VDS),K1(VDS).K2(VDS)
EXTRACT: PHIF2.VFBK1.K2.U0
DETERMINE BETA(VDS.VBS),VTH(VDS.VBS).U1(VDS.VBS)
EXTRACT: BETAOSAT
ETA.U1
PARAMETER
REFINEMENT
SUBTHRESHOLD
EXTRACTION
Fig. 3.4 Flowchart of the parameter-extraction subroutine.
Chap. 3 .41.
33. Comparison of Measured and Modeled Results
Experiments were carried out using devices fabricated at various industrial sites.
Figure 3.5 shows a comparison of measured and modeled output characteristics of a
Wmk = 20 fim and Lmk «• 3.5 fim N-channel transistor. Modeled results are plotted
with solid lines while measured data are displayed with cross marks. Figure 3.6 shows
a similar comparison for a WMK = 20 fim and LMK - 2 fim P-channel transistor. The
comparison of long-channel N-channel and P-channel transistors are shown in Fig. 3.7
and 3.8. respectively. The gate-oxide thickness of the transistors is 30.0 nm. Figure
3.9 shows the results of a N-channel transistor with the gate-oxide thickness of 70.0
nm which was fabricated from a different process.
Comparison of measured and modeled total drain current for a W^ = 3 fim and
Lmk = 4 ^m N-channel transistor is shown in Fig. 3.10. Asimilar comparison is shown
in Fig. 3.11 for a WMK = 2 jum and LMK = 4 fim P-channel transistor. With threshold
voltages properly characterized, agreement between measured and modeled results in
the subthreshold region is excellent.
Chap. 3-42-
1DS versus VdS
(a)
(b)
Fig. 3.5 Measured and modeled output characteristics of a WMK= 20 fim and
Lmk =3.5 fim N-channel transistor. Tox = 30.0 nm. (a) Ids versus Vds atVbs = 0.0 V. (b) 1^ versus V^s at V^ - -2.0 V. (c) 1^ versus Vqs at V^ =»0.1 V. (d) IDS versus VGS at V^ = 3.0-V.
Chap. 3
Fig. 3.5
Aaa dusa l.«
VOS30.10 V
vbsaa.oa V
IOS versus VGS
IDS versus VGS0.aa
-I.0B
-a. 2B
=1-1
-43-
(c)
(d)
Chap. 3
(b)
XDS versus VDS-l.ee
-a.ee
-d.ee
-5.ee
IDS vtrsus VDS Vbs<v)
wnwwwwwwnwwwwwwwwwwwwwwwia*»j«WM*i»m "1.68
-x.ee
-3.88
-f.ee
-£.ee
-44-
Fig. 3.6 Measured and modeled output characteristics of a WMk °* 20 fim and
LMk = 2 fim P-channel transistor. Tox = 30.0 nm. (a) Ids versus VDs atVBS = 0.0 V. (b) Ids versus VDS at VBS = 2.0 V. (c) IDS versus VGs at VK =-0.1 V. (d) Ids versus VGS at VDS = -3.0 V.
Chap. 3
Fig. 3.6
ZDS vmrsus VGS
IDS vmrsus VGS
WWWW I
Vaacv>
awn HiijiMJiMa
ff.aa
a.eoz.ee
eaY./ «.**• *•*•• • • I • i i.i.l,• • i • \ • l .. \.... i.... i.... i i.... i I e.
-*» -».s» -*m -».• -),» -i.m ^.gi .,.— «/#- ^.a 0
vfas«r».oav Vvs •« *u,
-45-
(c)
(d)
Chap. 3
(a)
(b)
ZDS versus VDS VtftGO5. ma
4>ee
«ttt- i-ee
•: 2.68
t.aa
^^,1 <K« ••«».im«MW»»HWM« JJ»HMM JJIJJIJK*<<«WW1>»»»*JI
♦.«• *MXMk*^JL^«HMjL*AririkI^Mtak«JL*d^rtJ^MMk«JdMMMjLAdMMjLA^*l•>» a.sa I.M 1.9 !«• t.u J.a i.m 4>« ♦.» S.*
VgSa«,0O V Vfe* ,« Vbita
IDS versus VDS Vcs«oS.aa
-46-
Fig. 3.7 Output characteristics of a WMK = 20 fim and LMk = 20 fim N-channeltransistor. Tox = 30.0 nm. (a) Ids versus Vds at VBS =0.0 V. (b) Ids versusVds at Vbs= -2.Q V. (c) Ids versus VGS at Vds = 0.1 V. (d) Ids versus Vqsat VDS = 3.0 V. "
Chap. 3
IDS vrsus VGS
/ •'/<&//&':? ///•«/
vtsrvj
0.9 ; ,t,,k \tm»4\*-iltit4tt4m^ni i i 11 i i i 11 i i 111 i i i I i i 111 i i 11S.0 lU 1.9 1.9 1,11 Ml jjM 1.9 4(9 *.9 &,m
VOS»«v IS V Vvt .« volt.
XDS versus VGS
6.9 A.9 1.9 1.9 3.9 MS JJM 1.9 4|9 *.9 £9
VDS-3,ao v ufe ,„ vt.it.
Fig. 3.7
-47-
Cc)
Cd)
Chap. 3
(a)
(b)
XDS vsrsus VOS
•4^9 -♦.» -4l« -1.9 <j,9 -HI -3,9 -1.9 -1.9 4.9 O
va&«e.oo v vbs .» Volt.
XDS versus VOS
j^l^—M— UIKI IIIKIDII limillKIIXIIIIIIK*
zJ*
i«»nimaiiii»«« « mi •<•••'« '
-48-
.98
Fig. 3.8 Output characteristics of a WMK » 20 fim and Lmk = 20 fim P-channeltransistor. Tox = 30.0 nm. (a) Ids versus Vds at Vbs = 0.0 V, (b) IDS versusVds at VBS = 2.0 V. (c) Ids versus VGS at Vds = -0.1 V. (d) Ids versus VGSat VDS = -3.0 V.
Chap. 3
Fig. 3.8
•.»
-%m »_
r
IDS Vtrsus VGS
yyyyyyyyy ' -
s. v* y
i i i I 11 >i i i 111 i 11 11 i 11 11 i i 11 1111 i i I
vucvj
! *»ee
a-ee
t.ea
0.88
•>•«!• V \/<S .„ Volt.
JOS versus VGS
l.« -a.9 ©
tf*.
1////
£" • • •!•••• ! .... I .... I ••.. I ••.• 1 • •.• I « mill t
«&9 -4.9 -4.
-i.oo V
-1.9 -},» -l» -«.«
vfcae>
-49-
(c)
«0
Chap. 3
XDS y/*.rs*a VOS
Ca)
(b)
«»jh**j«**J"} 2»aa
«.» Jr .. i. , I t i i i ..i J....1....I l.aai.9 J. 9 I.Jt 1.9 2.9 19 19 1.9 4.9 4.9 S.9
fecO.OO V VoS ,„ felt.
IDS ytttsus VOS vtocifj
i.ee
-50-
Fig. 3.9 Output characteristics of a WMK = 50 fim and LMK = 3.5 fim N-channeltransistor. Tox = 70.0 nm. (a) IDS versus YDS at YBS -0.0 V, (b) IDS versusVds at VBS= -2.0 V. (c) 1DS versus VGS at VDS =0.2 V. (d) IDS versus VGSat VDS = 3.0 V.
Chap. 3
Fig. 3.9
>3at.»
„*••.*•
m*
IOS versus VGS VfstWOa.iaa
<<m$
6\W • .1 i • ii aft • i • i i • • • • i • . • • I . . . . I • . . . I . • • • I • • • • i
•V" JS« I.* )-9 7.9 i » f^a 3.9 4v9 4.9 tf.m
VOSmo.10 V Vfe» ,„ vbit.
IDS versus VGS \focv>.aa
-51-
(c)
(d)
Chap. 3 -52-
Ids (A)
VgsCV)
Fig. 3.10 Comparison of measured and modeled total drain current for a W^ « 3fim and LMk = 4 A«n N-channel transistor with Tox= 30.0 nm.
Chap. 3
Ins (A)
-2 -1
VGS (V)
-53-
Fig. 3.11 Comparison of measured and modeled total drain current for a WMK= 2fim and Lmk *• 4 /im P-channel transistor with Tox= 30.0 nm.
CHAPTER 4
THE BSIM CHARGE AND CAPACITANCE MODEL
-54-
Less effort has been devoted to obtaining satisfactory charge models than the dc
models.
Both conductive and capacitive current components exist due to the same charge
storage in an MOS transistor. The charge and capacitance model presented here was
intimately derived with its associated dc model. The partitioning of the channel charge
into drain and source components is given significant attention. Body-bias effects are
properly incorporated and the device physics areexplained and properly modeled.
4.1. Capacitance Modeling for Circuit Simulation - The Theory
In 1971. Meyer [4.1] proposed a capacitance model for circuit analysis which has
become the basis for most existing MOS transistor models used in circuit simulators. In
the Meyer model, the expressions for intrinsic gate capacitances are obtained from the
derivatives of the gate-charge expression with respect to the gate-source and gate-drain
voltages.
C'S~W^ and Cgd=avG7' (41)It asserts that transistor capacitances are reciprocal and no ac coupling exists between
the source and the drain, i.e.. Csd and Cds are zero. The Meyer model, as was noted by
Ward [4.2]. fails to model the bulk charge. The effect of the bulk doping and body bias
are indirectly included in the threshold voltage. However, the threshold voltage is
treated as constant when taking integrals or derivatives.
Chap. 4 _55_
To derive a complete and accurate MOS transistor capacitance model for circuit
analysis, the following issues need to be properly addressed: charge conservation,
channel-charge partitioning, small-geometry effects, and distributed-channel effect.
4.1.1. Choice of State Variables
The issue of modeling MOS transistor charge storage [4.2,4.3] has attracted
integrated-^circuit designers' attention since Ward and Dutton [4.4] pointed out that
charge nonconservation is a particular problem for the Meyer model in simulating cir
cuits containing high impedance nodes as are typical in dynamic and charge-storage cir
cuits. Either inaccuracies or failures will occur in the simulation results of some
switched-capacitor, DRAM, and silicon-on-sapphire circuits that are sensitive to the
capacitive components of the MOS transistor currents.
Although there have been various solutions proposed in the literature, there is
unanimous agreement that the solution to the charge non-conservation problem is to
use the terminal charges instead of the terminal voltages as state variables. The termi
nal charges. Qc . QB . Qs , and QD are the charges associated with the gate, bulk (body),
source, and drain, and the capacitive current components of Iq. Ib. h- and Id» are respec
tively the derivatives of QG. QB. Qs, and QD with respect to time.
Yang et al. [4.5] demonstrated the importance of choosing charge as the state vari
able by using a nonlinear capacitor which is controlled by a remote voltage other than
its terminal voltages. A discontinuous relationship of the capacitor versus controlling
voltage is contrived in their network.
In general, a simple example can be constructed to illustrate the fundamental
nature of charge non-conservation problem [4.6]. First, one may write a capacitance
branch relation in terms of charge.
Q = f(vl.v2 t) (4.2)
Chap. 4 -56-
i=Af(vl.v2 0-J^+T&^ +...+/-4£Ug.(O)dt flvl dt 3v2 dt Qvn dt flt
Fortunately, we can use the simple case of the stored charge being a function of a single
voltage as follows:
Q=f(v). (4.4)
i= * f(v) =|i.i*Y_. (4.5)dt flv dt
We recognizeQf/flv as the definition of capacitance and call it C(v). Then,
i=C(v) |1. (4.6)By integrating from the present time point, t0. to the next time point, ti. Eq. (4.6)
becomes
/ i(t) dt =/ C(v) dv . (4.7)
Here comes the problem. If C(v) is treated as a constant and pulled out. Eq. (4.7)
simplifies to
/ i(t) dt =C(v) [v(tj) - v(t0) ]. (4.8)lo
The function C(v) is not known over the interval t0 to tj.. The Meyer model imple
mented in SPICE2 evaluates C(v) at t0. This rules out charge conservation. The prob
lem can not be totally eliminated even by careful choices of step sizes and error toler
ances. Evaluation of C(v) at tx has been suggested as an alternative. Since ti is the new
time, it must be picked up during the iteration. Still, it will not conserve charge.
Now. if the charge formulation is used instead, all problems are avoided. Note
that
dQ1=it (".9)By integrating from t0 to tlt Eq. (4.9) becomes
Chap. 4 _57_
/ i(t)dt =Q(tx) - Q(to) =f(v(t!)) - f(v(t0)) . (4.10)
In view of f(v(ti)) being evaluated at the new time point, one can simply perform the
Taylor-series expansion about the voltage at the last iteration to obtain the companion
model. Either the trapezoidal or Gear integration formula [1.3] can be applied to the
left-hand side of Eq. (4.10) to carry out the complete integration.
4.1.2. Channel-Charge Partition
For the bulk charge, an approximate expression is more suitable for the circuit-
simulation purpose than an "exact" expression which is very complicated. The nonuni
form bulk-doping profile of implanted-channel devices introduces additional complex
ity.
The expressions for the gate and bulk charges are relatively easy to derive com
pared to the source and drain charge expressions because both the source and drain ter
minals are in intimate contact with the channel region. The channel charge can not be
associated only with the drain or only with the source. Partitioning of the channel
charge into source and drain components must be done carefully.
A number of channel-charge partitioning methods have been attempted. The point
of partition is somewhat arbitrary, usually based on physical arguments without sub
stantial theoretical or experimental supports [4.2]. The partition may imply that the
gate-to-drain and gate-to-source capacitances are reciprocal [4.7].[4.8], that Cdg must be
zero in saturation [4.9]. or that the drain-source capacitances must be zero [4.10].
Ward [4.2] has developed a physically meaningful partitioning method. The for
mulas are shown below,
L
QS =W/(1- f )qc(y)dy (4.11)
Chap. 4 -58-
L
QD =W/ f qe(y)dy (4.12)o L
The point of partition, according to this method, is at 3/5 of the channel from the
source end. This partitioning method leads to an admittance matrix for the device
whose capacitance terms are all nonzero and non-reciprocal, and the capacitances
between the source and the drain (C^ and C^) are negative. The non-reciprocal gate
capacitances produce gate-to-source and gate-to-drain feedthrough which are not
present in the Meyer model. The universally accepted non-reciprocal capacitance is
similar to a voltage-controlled current source which produces current in proportion to
the time derivative of the controlling voltage. The gate-drain capacitances Cgd and Cdg
differ both in value and in physical interpretation. Capacitance Cgd describes the gate
current produced by a change in the drain voltage, while Cdg gives the drain current
which results from a change in the gate voltage. Capacitance Cgd is zero in the satura
tion region due to the channel being isolated from the drain terminal, but Cdg has a
finite value.
Although non-reciprocity has been proven with measurements [4.2.4.11] and dev
ice analysis, the term "non-reciprocal capacitance" is a misnomer. A more appropriate
name should be Mtrans-capacitive coefficient".
4.1.3. Small-Geometry Effects
So far. capacitance models used in circuit simulators are mainly for long-channel
devices. Small-geometry effects haven't been included yet. The important effects in
modeling the dc characteristics of small-geometry transistors are essential in modeling
the ac characteristics. These effects are:
. vertical field mobility degradation effect.
. carrier velocity saturation effect.
. channel-length modulation effect.
Chap. 4 _59_
. source-drain series resistance effect.
The channel-side bias-dependent fringing-field effect is uniquely associated with the ac
characteristics. A detailed description of modeling the small-geometry transistor capa
citances can be found in Appendix H.
4.1.4. Distributed-Channel Effect
When a transistor is turned on, it takes a certain amount of time to build up the
channel charge. When the transistor is turned off, another amount of time is needed to
dissipate the channel charge. The time constant of the channel is inversely proportional
to the amount of channel charge and is thus non-negligible at low gate bias, especially
for long-channel transistors [4.12]. An empirical expression for the channel transit
time constant, assuming no velocity saturation effect. is[4.13.4.14]
T - V
where qc is per unit-area channel charge density.
The quasi-static approximation (QSA). which is widely used in deriving circuit-
simulation device models, assumes that the terminal charges found under steady-state
conditions are valid during all transient conditions. By neglecting the distributed
nature of the channel, it allows the stored charges to be evaluated from the instantane
ous terminal voltages. This assumption becomes incorrect when circuit transient time is
comparable to the transistor channel transit time. Fortunately, fast circuits are usually
built with fast devices. There can be errors when a few slow (long-channel) transistors
are used in a very fast circuit.
Previous approaches to high-speed transient circuit analysis [4.14.4.15] have
several limitations. The non-linear transmission line approach, while valid at high
speeds, is generally limited to simplified conditions. Lack of bulk-charge effects and
Chap. 4 -60-
step inputs are typical restrictions. Paulos et al. [4.16] obtained an analytical solution
to the non-linear transmission line analysis in the small-signal domain by truncating
the Bessel functions. However, their results are not readily applicable to the large-
signal transient analysis.
In using the conventional lumped MOS transistor model, special attention has to
be paid to the channel-charge partitioning method. Although the 40/60 channel-charge
partitioning scheme [4.17] has a sound physical foundation for quasi-static applications,
large current spikes appear due to the gate-to-drain capacitive feedthrough when the
transistor is biased in the saturation region. This feedthrough capacitance introduces a
low-frequency pole in the small-signal analysis and greatly affects simulation results.
Figure 4.1 shows a schematic diagram of a resistive-load inverter with a linear ramp
waveform applied to the gate. Output characteristics for the 40/60 and 0/100
channel-charge partitioning methods are shown in Fig. 4.2(a), and (b). respectively.
The feedthrough-induced current spikes are a function of the gate-voltage ramping
speed.
A lumped MOS transistor model does not offer the exponential-type increase or
decrease of drain and source currents to the final value. Instead, it predicts sharp
changes when the gate voltage goes across the threshold voltage. This is because the
distributed nature of the channel is not included in the model. The multi-sectional
approach is suitable for modeling the distributed channel effect [4.13]. The number of
sections per transistor should be judiciously chosen to obtain accurate simulation
results with reasonable execution time. Preliminary results show that no more than
four sections per transistor are needed. A schematic diagram of the high-frequency
device models for advanced MOS VLSI circuit analysis is shown in Fig. 4.3. In addition
to the distributed-channel effect of the intrinsic transistor region, the long-distance
interconnect effect, wide-gate effect, and local interconnect effect are all essential for
Chap. 4
K)V,in
Vin6
CV)
2 -
£
(a)
f
(b)
rDD
^ 1I
\
XX
\
\time
-61-
Fig. 4.1 (a) Schematic diagram of a simple resistive-load inverter and the (b) inputwaveform.
Chap. 4
time
(a)
-62-
Fig. 4.2 Output voltages and currents for the (a) 40/60. and (b) 0/100 channel-charge partitioning methods.
Chap. 4
long-distance interconnect
I 1I
x-WW-
TI
I
I^r" TT-shape -±r |
1
local
interconnect
interconnect
-63-
Fig. 4.3 A schematic diagram of high-frequency device models. Long-distance
interconnect effect, wide-gate effect, local interconnect effect, as well as dis
tributed channel effect are important for advanced circuit simulation.
Chap. 4 -64-
advanced MOS VLSI circuit simulation.
4.2. The BSIM Charge Model
A new and simple charge model for BSIM has been derived. This new model con
serves charge and has the non-reciprocal property. The expressions for the charge den
sities are similar in form to those of [4.5]. However, due to different ways of treating
the physics behind transistor operation, the functional dependence of ax is quite
different. The charge equations in the different operation regions aregiven below.
(A) Accumulation region:
QG = WLC0(VGS -vra--Vbs). (4.14)
Qb = - Qg • (4.15)
Qs = 0. (4.16)
Qd = o. (4.17)
(B) Subthreshold region:
Qg =WLC0^ -1 +1+ 4(Vcs-Vfb-Vbs)
V 2
1/ 2
(4.18)
Qb = - Qg • (4.19)
Qs = 0. (4.20)
Qd = 0. (4.21)
When an MOS transistor is biased in the triode region, the distributed charge den
sities of the gate, channel, and bulk can be expressed as:
qg (y) = c0(vGS - vFB - 4>s - vy). (4.22)
qc (y) = - c0 (vcs - vlh - ax vy). (4.23)
qb (v) = - C0 [ Vlh - VFB - <f>s - ( 1- ax ) Vy ]. (4.24)where
Chap. 4 ^5.
ax =a[l +̂ -(Vcs-Vth)]. (4.25)Here. Vy is the electron quasi-Fermi potential with respect to the source. Observe that
qg + q« + qb = 0. (4.26)
This relationship follows the constraint of charge neutrality in a one-dimensional MOS
capacitor structure.
Expressions for the total charge stored in the gate, bulk, and channel regions can
be obtained by integrating the distributed charge densities over the area of the active
gate region (from y =0 to y - L and z =0 to z =W). That is.
Qc =w/qg(y)dy. (4.27)o
L
Qb =W/ qb(y) dy . (4.28)
Qc =W/ qc(y) dy . (4.29)o
Here, qc(y) is the mobile channel charge per unit length along the channel, and y is the
position along the channel from 0 to L.
Combining Eqs. (4.22)-(4.24) with Eqs. (4.27)-(4.29) and replacing the
differential channel length "dy" with the corresponding differential potential drop
HdV". we obtain the following expressions for total gate, channel, and bulk charges in
static equilibrium.
L
Qc =w/co(Vcs-VFB--0s-Vy)dy
= WL C„ VGS ~ VFB "" 0S ~VDs . VDS <*XVDS
12 aex(vGS-vth-^ivDS)
QB =-w/cJVlh-VFB-0s-(l-ax)Vy]dyft
'(4.30)
Chap. 4
= WLC„ -Vth + VFB + 0s +(l"«x)
V DS
(l-<*x)Vx t vds a,Vx VDS
12 a,(Vgs-V^-^-Vds)
Qc =-w/c0(VGS-Vth-axVy)dy
<*xVds= -WLC„ ^cs-Vth-^LVDs+ ^ a,Vx vds
a,(Vcs-Vth-^-Vos)
-66-
(4.31)
(4.32)
It is clear that the total stored charge components of an MOS transistor. Eqs. (4.30)-
(4.32), also exhibit charge-neutrality relationship,
Qg + Qc + Qb = 0. (4.33)
It is necessary to partition the channel charge into the drain component (Qd) and
the source component (Qs ). The issue of channel-charge partition has so far been dealt
with by gross approximation or use of an arbitrary factor. Ward et al. [4.4] already
noted this difficulty. They describe many possibilities and chose the 50/50 partition
between QD and Qs. although their device simulation had indicated a 40/60 partition in
the saturation region. Yang, et al [4.5] proposed to make the partition so as to satisfy
the condition that QD and Qs and their derivatives be continuous throughout the triode
and saturation regions. They failed to note, however, that there are infinite ways to
partition the channel charge to satisfy that requirement.
Taylor, et al. [4.18] adopted the 50/50 partition for mathematical simplicity while
noting that the correct partition of the capacitive current is 0/100 whenever dVG/dt is
positive (assuming an N-channel transistor) and 100/0 whenever dVG/dt is negative.
Their reasoning is that electrons can enter the channel only from the source and leave
the channel only through the drain. In reality, only the net current flow obeys that
restriction, if at all. The capacitive current, which is merely the difference between the
net current and the quasi-static current that would be present in the absence of
Chap. 4 -67-
capacitive coupling, can flow in either direction.
A sound theoretical model for channel-charge partition is of particular importance
because if the partition is performed through the use of a parameter, then that parame
ter (actually a function of the bias voltage) is unusually difficult to extract from device
measurements. In this work, the issue of channel-charge partition is appropriately han
dled.
In BSIM, the drain/source partitioning of the channel charge smoothly changes
from 40/60 (or 0/100) in the saturation region to 50/50 distribution in the triode
region.
4.2.1. The 40/60 Channel-Charge Partitioning Method
The channel-charge partitioning method proposed by Ward et al. [4.2] is used.
Carrying out the integrations in Eqs. (4.11) and (4.12). with qf(y) replaced by the
expression in Eq. (4.23), we obtain the total charges associated with the source and the
drain,
(C) Triode Region:
Expressions for the gate charge and the bulk charge are the same as those in Eqs.
(4.30) and (4.31). and
Qs = - W L C0Vgs - Vth <*x VDS a, Vx vDS
12 a,(VGS-V,h-^LVDS)
<*xVDsa,
r(VGS-Vth)2 axVDS(VGs-Vlh) *X2VDS2,"Ti 7 "~ 5 + 7K—J
8 40(vGS-vlh—JLVDS)
QD = - W L CflVGS - Vth ax VDS otxVx vDS
Of,
(vGS-vlh-_ivus)
(4.34)
Chap. 4 -68-
r (Vcs-Vth)2 _ OxVpsCVcs-Vth) ^ <*x2 Vps2 ,1 6 8 40 J
(D) Saturation Region:
Vcs-V*
(4.35)
QG = WLCO(VGS-VFB-0S--1^ 11). (4.36)
QB°WLC.[Vra +»s-V„,+ <*-««><V<»-V«> ], (437)J ax
Qs =- yWLC0(VGS-Vth). (4.38)
Qd =- -^ WLC0 (VGS - Vth ). (4.39)
4.2.2. The 0/100 Channel-Charge Partitioning Method
The 0/100 channel-charge partitioning method can be derived using the following
boundary conditions.
(1) Expressions for all terminal charges and capacitances are continuous from the
saturation region through the triode region.
(2) The charges Qs and QD are equal and the capacitances Csg and Cdg are equal when
VDs is zero.
(3) In the saturation region, all the channel mobile charge is only associated with the
source and QD is zero [4.5].
(4) For the simplicity of model equations, partition is done using the existing terms in
the Qc expression. No additional terms are introduced.
(C) Triode region:
Expressions for the gate charge and the bulk charge are the same as those in Eqs.
(4.30) and (4.31). and
Chap. 4
Qs=-WLC0
QD=-WLCfl
VGS-Vth ax2 +T-Vds"
Vcs-Vth 3 v .—2—"" T a* w
(D') Saturation region:
-69-
(«xVds)2
24(VGS-Vth-^iVDs)2
(4.40)
(«xVds)2a,
8(VGS-Vth-^LVDs) (4.41)
Expressions for the gate charge and the bulk charge are the same as those in Eqs.
(4.36) and (4.37). and
Qs =-y WLC0(VGS-Vth).
QD = 0.
(4.42)
(4.43)
4.2.3. The 50/50 Channel-Charge Partitioning Method
Gate capacitances are particularly important, more than other terminal capaci
tances for VLSI circuits which are mainly made up of short-channel devices. Once the
gate capacitances are measured, a charge-based capacitance model can be constructed
using simple channel-charge partitioning methods, for example with equal partition
between Qs and QD . The charge expressions for the 50/50 partitioning method are
listed below.
(C") Triode region:
Expressions for the gate charge and the bulk charge are the same as those in Eqs.
(4.30) and (4.31). and
Qs = -yWLC0
Qd = Qs •
(D") Saturation region:
VGS-Vth- ^L VDS + («« VDS)2a,
12(VGS-Vth - -JL VDS)(4.44)
(4.45)
Chap. 4 -70-
Expressions for the gate charge and the bulk charge are the same as those in Eqs.
(4.36) and (4.37). and
QD =-iwLC0(VGS-Vth). (4.46)
Qs = Qd • (4.47)
4.3. The BSIM Capacitance Model
Charge derivatives can be defined as transistor capacitances [4.2],
q,*8„J$. and 8,-f., $\l\ . (4-48)where i and j stand for g. b, d and s. The factors Sy are defined so that the Qj's will
normally be positive.
These sixteen transistor capacitances have the following properties. First, if all
the terminal voltages are changed by an equal amount, the terminal charges remain the
same. This effect of changing all the applied voltages by an equal amount is equivalent
to putting an offset on the system ground [4.2]. It can be expressed as
£ Cij = 0 for i=g.d.s.b. (4 49)j=g.b.d.s
Second, charge neutrality implies that the sum of the terminal capacitive currents is
zero. Therefore, the capacitances obey the following identities.
Cgg + cbg + Cdg + Csg = 0 . (4.50)
Cgb + Cbb + Cdb + Csb = 0 . (4.51)
Cgd + CM + Cdd + Csd = 0 . (4.52)
Cgs + 0* + Cds + C^ = 0 . (4.53)
The above two conditions put seven constraints on the capacitances. Nine of the capaci
tances are independent and must be calculated explicitly. Since twelve capacitances are
required in the assembly of nodal admittance matrix, the remaining three may be
inferred through Eqs. (4.49)-(5.53).
Chap. 4 -71-
Figure 4.4 shows plots of the four normalized terminal charges with the 40/60
channel-charge partitioning method. Selected plots of MOS transistor capacitances nor
malized to the total gate-oxide capacitance.C0WL . are shown in Fig. 4.5 and 4.6. Simi
lar plots of terminal charges and capacitances for the 0/100 and 50/50 channel-charge
partitioning methods can be easily obtained, too. Notice that the charges and capaci
tances are all continuous at the boundary of the triode and the saturation regions.
When a transistor is biased in the saturation region, the channel is decoupled from the
drain as predicted by long-channel device theories. This decoupling of the drain from
the conduction channel results in all partial derivatives with respect to the drain vol
tage (Cgd. CM. Cdd and C^) to be zero.
As the gate bias increases and reaches the threshold voltage, the transistor channel
charge starts to appear and all the 16 capacitances abruptly change in value. The
discontinuities in the capacitances are caused by the strong-inversion approximation
used in charge formulation. In transient analysis, the discontinuity in capacitances-
poses no problem because they are multiplied by terms of voltage difference which van
ish as convergence is reached [4.2]. However, for small-signal ac analysis, smooth capa
citance characteristics are highly desired. A common remedy for the problem of discon
tinuity in capacitances is to smooth out the capacitance characteristics. This proves to
be a non-trivial task because MOS transistor capacitances are functions of more than
one voltage. In general, smoothing has to be done on a multi-dimensional basis.
Recently. Tsividis [4.19] proposed to use different models for dc and transient
than for small-signal ac analysis. Such approach has several drawbacks. Circuit
designers have to deal with multiple sets of transistor parameters in circuit simulation.
In addition, the results of a transient simulation of. for example, an operational
amplifier in a switched-capacitor integrator, would not agree with the results of the ac
simulation [4.20]. Successful modeling work should be able to produce consistent dc.
Chap. 4
4U-^
Q
WLCo
6
2 -
-3L
Vbs=LOvVDS=4.0v
-72-
Fig. 4.4 Plots of normalized terminal charges versus gate bias for two drain voltages. The parameters are Vbs= 0.0 V. VDs= 10 and 4.0 V. a= 1.224.
Vth - 0.70 V. K! = 0.633. <f>s = 0.625 V.
Chap. 4
4 5 6 7
VGS (volt)
-73-
Fig. 4.5 Selected plots of normalized capacitances versus the gate bias. The parameters are V*;- -3.0 V. Vds- 4.0 V. a = 1.131. Vth(VBS= -3.0 V)= 1.4 V.K, = 0.63 V1/2. 0s = 0.62.
Chap. 4 -74-
Fig. 4.6 Selected plots of normalized capacitances versus the drain bias. The
parameters are VBS - -3.0 V. VGS = 6.0 V. a = 1.131. Vth(VBS - -3.0 V)= 1:4V. Kj = 0.63 V1/2. 0s =0.62.
Chap. 4 _75_
transient, and small-signal ac simulation results.
4.4. Comparison with Experimental Results
Measurements of MOS transistor capacitances have been reported [4.2].[4.3] using
commercially available LCR meters. The limit of this measurement method is about 1
pF. as was pointed out by Paulos et al. [4.21]. Appendix H describes in detail a newly
developed technique to accurately measure gate capacitances of small-geometry MOS
transistors.
Figure 4.7 compares calculated results with the measured data given in [4.19] for a
long-channel transistor. Good agreement is found.
Chap. 4
WLC0
model
• oxa experiment
-76-
Fig. 4.7 Comparison of several calculated and measured [8] capacitances versus thegate bias with VBS = 0.0 V. VDS =» 4.0 V.
-77-
CHAPTER 5
SPICE2 IMPLEMENTATION
5.1. Basic Considerations
It was desired that the addition of BSIM should not affect the execution of the
existing SPICE2 MOS transistor models. Therefore, a new linked list was created to
store BSIM model parameters. A SPICE2 example with BSIM is shown in Fig. 5.1. To
activate BSIM. an MOS transistor is described with "S" as the leading character in place
of "M". The transistor card refers to a process file, instead of a model card, for the
parameter values.
A model pointer has been added to the resistor and capacitor linked lists. Then,
the resistor (or capacitor) value can also be calculated using the data corresponding to
the interconnection layer from which it is made. This mimics actual integrated-circuit
construction. Whenever the fabrication process is modified, the resistor (or capacitor)
value will change according to the new data in the process file.
5.1.1. Process File Format
Figure 5.2 shows the process-file format. A process file consists of two parts: key
words on the first line, and data on the other lines. In a process file, there will be two
lines of data associated with each interconnect keyword and 23 lines of data associated
with each transistor keyword. The mapping is sequential. For example, data on the
third and fourth lines are associated with the first keyword DU1 specified on the first
line. A line beginning with "*" is treated as a comment line. At present, there are 14
keywords reserved for interconnect types (DU1 to DL'6. PY1 to PY4. .ML1 to ML4) and
10 keywords reserved for transistor types (N.M1 to NM5. PM1 to PM5).
Chap. 5
EXAMPLE1 : CMOS INVERTER
VCC 10 5
SMN1 2 3 0 0 PC1JJM1 L=10U W=50U
SMPl 2 3 11 PC1_PM1_DU2 L=10U W=50U
VIN 4 0 PWL(0 0 5N5 ION 5 20N0)RIN 4 3 PC1_PY1 L=20U W=60U
Cl 2 0 50F
.OPTIONS NOMOD RELTOL=lE-5 CHGT0L=1E-16
.TRAN 0.5N 20N
•PRINT TRAN V(3) V(2)
.PLOT TRAN V(3) V(2)
.PROCESS PCI FILENAME=PNMED
.WIDTH OUT=80
•END
Fig. 5.1 A SPICE example with BSIM.
-78-
Chap. 5
DU1 DU2 PY1 ML1 NM1 PM1
*N+ DIFFUSION LAYER
35.0 2.5E-4 3.8E-10 1.0E-4 0.8
a6 a.5 a33 2.0E-6 a
*P+ DIFFUSION LAYER
120 3.1E-4 4.7E-10 1.0E-4 0.8
0.6 0.5 0.33 2.0E-6 0.
*POLYSILICON LAYER 1
I ,• • • •
1 .... 'i i
"METAL LAYER I
1—.-.v.- ------.1 .... 'I 1
*NMOS TRANSISTOR : TYPICAL CASE
I .... |
I •_•_•_' I*PMQS TRANSISTOR : EAST CASE
I .-.-.-. 1I • • • • |
I *_•_•_• |
Fig. 5.2 Process file format.
-79-
Chap. 5 -80-
5.1.2. New and Modified Linked Lists
The implementation of BSIM and the process-oriented simulator structure
involves a large number of changes in the SPICE2G.6 source code [5.1]. New linked
lists are created for the BSIM MOSFET with internal ID = 15 [5.2], transistor process
information with internal ID= 25. and interconnection-line process information with
internal ID = 26.
Compared to the regular MOSFET linked list in SPICE, there are more entries
reserved for the BSIM MOSFET to store the electrical parameters of each individual
transistor. Two model pointers are used in the BSIM MOSFET linked list (ID =15)
while only one model pointer is reserved in the regular MOSFET linked list (ID = 14).
A new linked list with ID= 25 is created to store the 69 extracted BSIM process
parameters and one of which serves as a flag to choose the channel-charge partitioning
method. The model pointer 1 in the BSIM MOSFET linked list (ID = 15) points to the
BSIM model linked list (ID= 25) for the intrinsic gate-region information. The model
pointer 2 in the BSIM MOSFET linked list (ID = 15) points to the interconnection-line
model linked list (ID = 26) for the source and drain junction information. The model
pointer in the resistor linked list (ID = 1) or the capacitor linked list (ID = 2) points to
the interconnection-line model linked list (ID=26) for resistance or capacitance infor
mation.
In the standard SPICE2 implementation, resistor and capacitor elements have no
models, hence no pointers: now they have. For such an element two more entries are
added to the original linked list, one for the interconnect type and the other for the
model pointer. During the read-in stage. SPICE2 stores the identification code for the
keyword (PY1. ML1. DU1. etc) appearing on the element card. Later the integer code
of the element is used to search for the appropriate model to which the pointer entry of
the element can point. The same strategy is used for BSIM MOS transistors. A com-
Chap. 5 _81_
plete description of the new and modified linked lists is included in Appendix B.
Geometries of resistors, capacitors and MOS transistors are stored in their own
linked lists as before. Given their sizes, the resistor and capacitor values are calculated
from the corresponding interconnect-layer information in a pre-processing fashion.
Electrical parameters for each BSIM MOS transistor are calculated from BSIM process
parameters and stored in the linked list of each transistor. This is a one-time data
reduction. Since the source and drain junction capacitances of an MOS transistor are
bias dependent. They have to be evaluated during each iteration cycle.
5.2. Implementation in SPICE2
5.2.1. Functions of the Newly Added Subroutines
There are 5 new subroutines. Their names and functions are described in the fol
lowing:
(1) subroutine PROCHK:
This subroutine converts size-independent parameters into electrical parameters
for each transistor. It prints out a list of process-file parameters, and single-transistor
electrical parameters according to the user's request. Its role is similar to that of
MODCHK for SPICE2G.6 MOS LEVEL-1. 2 and 3 models.
(2) subroutine BSIMEQ:
BSIM dc and charge expressions and their derivatives are implemented in this sub
routine. Given all the electrical parameters and the terminal voltages of an MOS
transistor, this subroutine evaluates the drain current and conductances. It also calcu
lates terminal charges and capacitances for transient and small-signal ac analysis. Its
role is equivalent to a combination of subroutines MOSEQ2 and MOSQ2.
(3) subroutine BSIM:
Chap. 5 -82-
This subroutine processes the MOS devices using the BSIM model for dc and tran
sient analysis. Only the companion BSIM charge and capaciunce model is used for the
charge-storage effect associated with the thin-oxide region. It is similar to subroutine
MOSFET in the regular SPICE2G.6 code.
(4) subroutine BSMCAP:
Given the active-region charge and capacitances from subroutine BSIMEQ and the
overlap capacitances and junction capacitances, this subroutine computes the equivalent
conductances and complete terminal charges for an BSIM transistor. It is like subrou
tine MOSCAP.
(5) subroutine FNDTYP:
This subroutine establishes the connection between an element linked list, as that
of a resistor, capacitor, or BSIM MOS transistor, and the linked list of corresponding
process parameters. It writes the address of the process-parameter linked list to the
pointer location of the element linked list. Two keys are used to search for a match:
the process name and the model type. It is similar to subroutine FNDNAM in the regu
lar SPICE2G.6 code.
5.2.2. Modifications to the Original Subroutines
Eighteen subroutines in the original SPICE2G.6 code are partially modified. Their
names and modifications are described in the following:
ACLOAD DCTRAN LOAD SPICEADDELT ERRCHK MATLOC TOPCHKALTER FIND MATPTR TRUNCCARD GETLIN NXTCHRDCOP LNKREF READIN
(1) subroutine ACLOAD:
The task of initialization and loading of the complex coefficient matrix is extended
to include BSIM MOS transistors (ID = 15).
Chap. 5 _83-
(2) subroutines ADDELT. ALTER, and FIND:
The major changes in these subroutines are made to create linked lists with ID =
15. 25 and 26. and to expand the sizes of the linked lists with ID = 1 and 2.
(3) subroutines CARD. GETLIN:
Changes are made to handle the BSIM process file.
(4) subroutine DCTRAN:
Subroutine BSIM is called by this subroutine. The line "l + JELCNT(14)\
which is near the beginning of transient analysis source code, is changed to "l +
JELCNT(14) + JELCNT(15)".
(5) subroutine DCOP:
The printing of operating-point information is extended to include BSIM MOS
transistors.
(6) subroutine ERRCHK:
Changes include translating node initial conditions to device initial conditions for
BSIM MOS transistors when UIC is specified on the .TRAN card, and to assign default
values for transistor geometries. The added subroutine PROCHK is called by this sub
routine.
(7) subroutine LNKREF:
The task of resolving unsatisfied name references is extended to include BSIM
MOS transistors. Subroutine FNDTYP is called by this subroutine twice to find
addresses for both pointers. Tms subroutine calls FNDTYP. instead of FNDNAM. to
handle resistors and capacitors.
(8) subroutine LOAD:
Subroutine BSIM is called by this subroutine.
(9) subroutines MATPTR. MATLOC and TRUNC:
Chap. 5 -84-
Changes are made to include BSIM MOS transistors.
(10) subroutine NXTCHR:
The character "J| is also treated as a delimiter.
(11) subroutine READIN:
Many modifications have been made in this subroutine. Variable strings
BIDM(25). JPOLAR(24). NPROID(24). JPAR(3). JPBR(2). BMPAR(80). RESLIN(15).
and ITYPES(25) are created and initialized to handle the read-in of the BSIM MOS
transistor and interconnect parameters. One more entry is added to the string AIDC to
recognize the keyword "PROCESS." New input syntax for resistors, capacitors. BSIM
MOS devices, and interconnects is included. The keyword "PROCESS" is treated like
the keyword "MODEL" except it is used with ID =25 and 26. This subroutine opens
process files and calls subroutine CARD to read the parameters.
(12) main program SPICE:
The line "WRITE (IOFILE.361) NUNODS. NCNODS. NUMNOD. NUMEL.
(JELCNT(I). 1=11.14)" is changed to
"WRITE (IOFILE.361) NUNODS. NCNODS. NUMNOD. NUMEL. (JELCNT(I).I=11.13).
1JELCNT04) +JELCNT05)" to correctly count the number of MOS transistors.
(13) subroutine TOPCHK:
The line "1 1HQ.1HJ.1HM.0.0D0.0.0D0.1HT.0.0DO.0.0D0.0.0DO /" is changed to
"1 1HQ.1HJ.1HM.1HS.0.0D0.1HT.0.0D0.0.0D0.0.0D0 /" to include BSIM MOS transis
tors.
53. Program Performance
Experimental results show that the BSIM model reduces the program execution
time by a factor of 2 as compared with the popular SPICE2 LEVEL-2 MOSFET model
[1.8]. A comparison of selected SPICE2 simulation execution time is listed in Table 5.1.
Chap. 5
Table 5.1
A Comparison of Selected SPICE2 Simulation Execution Time
Circuit Description BSIM (sec.) MOS LEV-2 Model (sec.)
Ratioless Dynamic Logic Ckt. 24.50 29.75
Five Stage Inverter Chain 18.30 44.25
MOS Amplifier (dc & ac) 40.02 52.70
MOS Amplifier (transient) 75.08 137.50
One Stage Op-Amp 15.83 70.77
Binary-to-Octal Decorder 262.37 586.28
Telecommunication Ckt. 1784.83 2717.32
-85-
-86-
CHAPTER 6
CONCLUSION
The Berkeley Short-Channel IGFET Model (BSIM) is an accurate and computation
ally efficient MOS transistor model. It includes complete expressions for dc drain-
current characteristics, capacitance characteristics, and extrinsic-element characteristics,
and is therefore suitable for dc. transient, and small-signal circuit analysis. Both the
strong-inversion and the weak-inversion current components were included in the
drain-current model. For each device type there are 54 size-independent parameters
stored in a process file from which the 17 electrical parameters per transistor are
derived at the data structure set-up stage of circuit simulation. Nine additional size-
independent parameters are needed for the weak-inversion current component. In order
to speed up circuit-simulation execution time, the 3/2 power dependence of the drain
current on the substrate bias has been replaced by a numerical approximation. This
approximation also simplifies the charge expressions.
A dedicated parameter-extraction program has been developed. The local parame
ter extraction technique, instead of global optimization methods, is employed. The
parameter-extraction program is modular, efficient, accurate, flexible, and user-friendly.
The charge model has been intimately derived from its drain-current counterpart.
This new model conserves charge and has the non-reciprocal property. Charge conser
vation is guaranteed by using terminal charges, instead of terminal voltages, as state
variables. Expressions for the total stored charges in the gale. bulk, drain, and source
are obtained by integrating the distributed charge densities over the active gate region.
Proper channel-charge partitioning methods are used to separate the channel charge into
the drain and source components. The terminal charges and capacitances are all con-
Chap. 6 -87-
tinuous at the boundary of the triode and saturation regions. Calculated capacitance
characteristics compare well with the measured data.
By using BSIM. substantial improvement in accuracy and simulation time has been
achieved. Experimental results show that BSIM reduces the circuit-simulation execu
tion time by a factor of 1.5 to 2 as compared with the widely used LEVEL-2 model
provided by SPICE2. The process-file approach used in this model provides a powerful
interface between fabrication facilities and circuit simulation. Simulated results of the
drain current agree with measured data at various bias conditions for different device
sizes and gate-oxide thicknesses. Therefore, the process-oriented BSIM is well suited
for circuit analysis and for process monitoring.
Some extensions can make BSIM more suitable for submicron and even sub-half-
micron device applications. The source-drain series resistance becomes increasingly
important in short-channel devices. Inclusion of the source-drain series resistance in a
novel way is essential for submicron devices. The buried-channel structure becomes
more prominent in the advanced device design. The enhancement of the drain-current
expression to take into account the buried-channel effect is particularly important.
The velocity saturation effect has drastically changed the transistor capacitance
characteristics. The present long-channel capacitance model needs to be overhauled to
include short-channel effects. In a VLSI chip, around 60% of the silicon area is con
sumed by interconnection lines. Accurate modeling and parameter extraction of inter
connection lines are particularly important. The substrate current, which is a good
monitor of hot-electron effects, is the next candidate to be included in advanced circuit
simulation models. With a substrate current model available, the circuit designers will
have a very powerful tool to tackle the hot-carrier problems in the circuit environment.
Ref. -88-
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Append. A _95_
APPENDIX A
BSIM USER GUIDE
This is a supplement to the original "SPICE Version 2G User's Guide." and is intended
for SPICE users who have access to BSIM (Berkeley Short-channel Igfet Model). It con
tains descriptions of the various additional device features supported by BSIM and how
to activate them. To be complete, it should be used together with the original User's
Guide.
In addition to the regular resistor and capacitor formats. BSIM also supports resis
tors and capacitors generated with interconnects.
A.l. Resistors
General form:
RXXXXXXX Nl N2 PNAMEJ-T L=VAL <W=VAL> <TC=TC1 <TC2»
Examples:
RI 1 2 PC1_DU1 L=10U
RC1 12 17 PC1_DU3 L=20U W=4U TC=0.001. 0.015
Nl and N2 are the two element nodes. PNAME is the process name.
LT is the interconnect type. At present, there are fourteen interconnect types avail
able (DU1 to DU6. PY1 to PY4. and ML1 to ML4).
L and W are the resistor length and width, in meters. W should be specified if the
default value in the process file is not to be used.
TCI and TC2 are the (optional) temperature coefficients: if not specified, zero is
Append. A -96-
assumed for both. The value of the resistor as a function of temperature is given by:
value(TEMP) - value(TNOM)*(l+TCl*(TEMP-TNOM)+TC2*(TEMP-TNOM)**2))
A.2. Capacitors
General form:
CXXXXXXX Nl N2 PNAMEJT L=VAL <W=VAL>
Examples:
CBYP 13 0 PCIJ>Y1 L=20U
COSC 17 23 PC1.ML2 L=30U W»30U IC=3V
Nl and N2 are the two element nodes. PNAME is the process name.
LT is the interconnect type. At present, there are fourteen interconnect types avail
able (DU1 to DU6. PY1 to PY4. and ML1 to ML4).
L and W are the capacitor length and width, in meters. W should be specified if the
default value in the process file is not to be used.
The (optional) initial condition is the initial (time-zero) value of capacitor voltage
(in volts).
[Note that the initial conditions (if any) apply 'only' if the UIC option is specified on the
.TRAN card.]
A.3. BSIM MOSFETs
General form:
SXXXXXXX ND NG NS NB PNAMEJtfT_DT<STHD> <L=VAL> <W=VAL>
+ <AD=VAL> <AS=VAL> <PD=VAL> <PS=VAL> <NRD=VAL> <NRS=VAL>
+ OFF> <C=VDS.VGS.VBS>
Examples:
SI 24 2 0 20 PC1_NM1
S31 2 17 6 10 PC2_NM2_DU2_STHD L=5U W=2U
Append. A -97_
S31 2 16 6 10 PC2_PM1_DU3 5U 2U
SI 2 9 3 0 PC2_PM2_DU3 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
SI 2 9 3 0 PCI_NM1_STHD 10U 5U 2P 2P
ND. NG, NS. and NB are the drain, gate, source, and bulk (substrate) nodes, respec
tively.
PNAME is the process name.
MT is the device type. At present, there are five device .types for both N-channel
and P-channel transistors (NM1 to NM5. and PM1 to PM5).
DT is the diffusion type to be used for the source/drain junctions. There are six
diffusion types available (DU1 to DU6). The default is DU1 for N-channel transistors
and DU2 for P-channel transistors.
STHD is used as a flag. If it is specified, the weak-inversion current characteristic
will be included.
L and W are the channel length and width, in meters.
AD and AS are the areas of the drain and source diffusions, in sq-meters.
[Note that the suffix U specifies microns (1E-6 m) and P sq-microns (IE-12 sq-m). If
any of L. W, AD, or AS are not specified, default values are used. The user may specify
the values to be used for these default parameters on the .OPTIONS card. The use of
defaults simplifies input deck preparation, as well as the editing required if device
geometries are to be changed.]
PD and PS are the perimeters of the drain and source junctions, in meters. NRD and
NRS designate the equivalent number of squares of the drain and source diffusions: these
values multiply the sheet resistance RSH specified on the .process card for an accurate
representation of the series drain and source resistance components of each transistor.
[PD, PS. NRD. and NRS all default to 0.0. OFF indicates an (optional) initial condition
on the device for dc analysis. The (optional) initial condition specification using
IC=VDS.VGS.VBS is intended for use with the UIC option on the .TRAN card, when a
Append. A -98-
transient analysis is desired starting from other than the quiescent operating point. See
the .IC card for a better and more convenient way to specify transient initial condi
tions.]
IV. .PROCESS Card
General form:
.PROCESS PNAME FILENAME=FNAME
Examples:
.PROCESS PCI FILENAME=PNMED
.PROCESS PD2 FILENAME=FAST
The .PROCESS card specifies process parameter values that will be used by one or
more devices.
PNAME is the process name, and FNAME is the name of the file containing the pro
cess parameter values. Special rules have to be observed in choosing FNAME. The lead
ing character of FNAME should be alphabetical. Alphabetical characters will be recog
nized only in the capital form. Totally no more than 8 characters are allowed.
The process card is used together with resistors, capacitors, as well as MOS transisors.
A3. Process File
This file is generated by the automated characterization program, and it contains
the process information for the transistors as well as for the interconnects. For transis
tors, the L (channel-length) and W (channel-width) sensitivity factors of a basic electr
ical parameter are denoted by appending the italic characters T and 'w' to the name of
the parameter. For the example of the basic parameter Vra (flat-band voltage), there are
two corresponding sensitivity factors. VFB/. Vrett.. If P0 is the basic parameter and PL
and Pw are the corresponding L and W sensitivity factors. The formula
Append. A -99-
P-P + Pl j. PwLeff weff
is used to obuined the value for each transistor size with both Leff (= LMK - AL) and
Weff (= Wmk - AW) in Mm.
(a) The format of the process parameters is listed below:
TRANSISTORS
name
1 Vra (VFB)
2 0S (PHI)
3 Kj (Kl)
4 K2 (K2)
5 T)o (ETA)
6 fiz (MUZ)
7 Uoz (U0)
8 U1Z (Ul)
9 mzb (X2MZ)
10 T)B (X2E)
11 T)D(X3E)
12 Uqb (X2U0)
13 U1B(X2U1)
14 ms(MUS)
15 msb (X2MS)
16 msd (X3MS)
17 U1D (X3U1)
18 Tox (TOX)
L sens, factor
Vfb/ (LVFB)
0s/ (LPHI)
Ku(LKl)
Ks/ (LK2)
7)o/ (LETA)
8t (DL)
Uoz/ (LUO)
U1Z/(LU1)
Mzbi (LX2MZ)
7)b/ (LX2E)
7)D/ (LX3E)
U0B/ (LX2U0)
U1B/ (LX2Uft
Msi (LMS)
Msbi (LX2MS)
Msdi (LX31V1S)
U1D1 (LX3U1)
Temp (TEMP)
W sens, factor
Vraw (WVFB)
0Su. (WPffl) V
Klw (WK1) Vl/ 2
K2w (WK2)
7)0w (WETA)
8U. (DW)
U0Zu. (WUO)
u1Zw. (WU1)
Mzbw (WX2MZ) cm2/V2-s
t)b.. (WX2E) V"1
7)Du. (WX3E) V"1
Uqbh- (WX2U0) V"2
U1Bu.(WX2Ul) /xmV-2
Msw (WMS) cm2/V2-s
Msbw (WX2MS) cm2/V2-s
Msdw (WX3MS) cm2/V2-s
U1Du.(WX3Ul) fim V"2
Vdd (VDD) yum (°C . V)
units of basic parameter
V
cm2/V—s( fim , fim )
V"1
AtrnV-1
Append. A
19 CGDO CGSO
20 XPART DUM1
21 NO LNO
22 NB LNB
23 ND LND
CGBO
DUM2
WNO
WNB
WND
F/m
INTERCONNECTS
1 Rsh(RSH) Cj(CJ) Cjw(CJW) Ijs (US) Pj (PJ)
2 Pjw(PJW) Mj(MJ) Mjw(MJW) Wdf(WDF) 8/(DL)
(b) The names of the process parameters of transistors are listed below:
-100-
VFB flat-band voltage
<f>a surface inversion potential
K! body effect coefficient
K2 drain/source depletion chargesharing coefficient
7)o zero-bias drain-induced barrier lowering coefficient
Mz zero-bias mobility
Uoz zero-bias transverse-field mobility degradation coefficient
U1Z zero-bias velocity saturation coefficient
Mzb sensitivity of mobility to the substrate bias at V^ = 0
7)B sensitivity of drain-induced barrier lowering effect to the substrate bias
t)d sensitivity of drain-induced barrier lowering effect to the drain bias, at Vds= Vdd
Append. A -101-
Uqb sensitivity of transverse-field mobility degradation effect to the substrate bias
U1B sensitivity of velocity saturation effect to the substrate bias
Ms mobility at zero substrate bias and at Vds=Vdd
Msb sensitivity of mobility to the substrate bias at V^ = Vdd
Msd sensitivity of mobility to the drain bias at V^ = Vdd
U1D sensitivity of velocity saturation effect to the drain bias, at Vds= Vdd
Tox gate-oxide thickness
Temp temperature at which the process parameters are measured
Vdd measurement bias range
NO zero-bias subthreshold slope coefficient
NB sensitivity of subthrehold slope to the substrate bias
ND sensitivity of subthrehold slope to the drain bias
CGDO gate-drain overlap capacitance per meter channel width
CGSO gate-source overlap capacitance per meter channel width
CGBO gate-bulk overlap capacitance per meter channel length
XPART gate-oxide capacitance model flag
Note:.XPART= 0, 0.5. and 1 selects the 40/60. 50/50, and 0/100 channel-charge parti
tioning methods, respectively.
The names of the process parameters of diffusion layers are listed below:
sheet resistance/square
zero-bias bulk junction bottom capacitance/unit area
Rsh fVsquare
Cj F/m2
Append. A -102-
zero-bias bulk junction sidewall capacitance/unit length Cjw F/m
bulk junction saturation current/unit area Ijs A/m2
bulk junction bottom potential Pj V
bulk junction sidewall potential Pjw V
bulk junction bottom grading coefficient Mj
bulk junction sidewall grading coefficient Mjw
default width of the layer Wdf m
average reduction of size due to side etching or mask compensation 8S m
The names of the process parameters of poly and metal layers are listed as follow
ing:
sheet resistance/square Rsh (Vsquare
capacitance/unit area Cj F/m2
edge capacitance/unit length Cjw F/m
default width of the layer . Wdf m
average variation of size due to side etching or mask compensation 8/ m
Append. A -103-
A.6. Examples
(a) The following is an example of a process file. The lines starting with "*" are
used as comments.
NMl PYl MLl ML2 DUl DU2
*PROCESS=PCl
*RUN=12 medium-size devices
*OPERATOR=Bing
*DATE=07/16/85
*
* NMOS-1 PARAMETERS
-1.0087E+000. -2.1402E-001. 3.44354E-001
7.96434 E-001. 0.00000E+000. 0.00000E+000
1.31191E+000. 3.23395E-0O1. -5.7698E-001
1.46640E-001. 1.68585E-001. -1.8796E-001
-1.002 7E-003. -9.4847E-003. 1.47316E-002
5.34334E+002. 7.97991E-001. 4.77402E-001
4.38497E-002. 6.38105E-002. -6.1053E-002
-5.7332E-002. 1.01174E+000. 1.62706E-002
8.25434E+000. -2.4197E+001. 1.95696E+001
-7.6911E-004, 9.62411E-003. -3.7951E-003
7.86777E-004. 7.35448E-004. -1.7796E-003
1.06821E-003. -8.0958E-003. 4.03379E-003
-1.9209E-002. -7.4573E-002. 1.47520E-002
5.40612E+002. 6.21401E+002. -1.9190E+002
Append. A
-1.2992E+001. -6.4900E+001. 4.29043E+001
-9.4035E+000. 1.18239E+002. -2.9747E+001
7.76925E-003. -1.0940E-001. -8.3353E-003
3.00000E-002, 2.70000E+001. 5.00000E+000
2.70000E-010. 2.70000E-010. 1.40000E-010
1.0. 0.0. 0.0
1.5.5 0.0. 0.0
0.09. 0.0. 0.0
0.0.
*
0.0. 0.0
* poly layer-1
*
30.0. 7.0E-5. 0.0. 0.0. 0.0
0.0.
*
0.0. 0.0. 0.0. 0.0
* metal layer-1
*
0.040. 2.60E-5. 0.0. 0.0. 0.0
0.0. 0.0. 0.0. 0.0, 0.0
metal layer-2 (top metal)
0.030, 1.3E-5. 0.0, 0.0. 0.0
0.0. 0.0. 0.0. 0.0. 0.0
n+ diffusion layer
-104-
Append. A -105-
35.0. 2.75E-4. 1.90E-10. 1.0E-8. 0.7
0.8. 0.5. 0.33, 0.0. 0.0
* p+ diffusion layer
120.0. 3.1E-4. 3.0E-010. 1.0E-8. 0.7
0.8. 0.5. 0.33. 0.0. 0.0
(b) The following deck determines the transient characteristics of a resistive load
inverter with a capacitor connected at the output node.
SAMPLE CMOS INVERTER
VCC 1 0 5
SMNl 2 3 0 0 PCIJNTMIJXJI W=50U L=10U
SMPl 2 3 11 PC1_PM1_DU2 W=50UL=10U
VIN 4 0 PWL(0 0 5N5 ION 5 20N 0)
RIN 4 3 PC1.PY1 L=20U W=60U
CI 2 0 50FF
.OPTIONS RELTOL=lE-5 CHGT0L=1E-15
.TRAN 0.5N 20N
.PRINT TRAN V(3) V(2)
.PLOT TRAN V(3) V(2)
.PROCESS PCI FILENAME=CM0716
.WIDTH OUT=80
.END
Append. B
Appendix B
LINKED LIST SPECIFICATIONS
B.1. Resistor (ID=1)
-1: subckt info
LOC +0: next pointer LOCV
+l:LOCV
+2:nl
+3: n2
+4: (nl.n2)
+5: (n2.nl)
+6: (nl,nl)
+7: (n2.n2)
+8: model type
+9: model pointer
+10: cycle number
+0: element name
+1: g (TEMP)
+2: r (TNOM)
+3: temp.coef. 1
+4: temp.coef. 2
+5: length
+6: width
-106-
Append. B
B.2. Capacitor (ID=2)
-1: subckt info
LOC +0: next pointer
+l:LOCV
+2:nl
+3: n2
+4: function code
+5: (nl.n2)
+6: (n2.nl)
+7: tp (function coefficients)
+8: LXi offset
+9: exponent vector
+10: (nl.nl)
+Il:(n2.n2)
+12: model type
+13: model pointer
+14: cycle number
LOCV +0: element name
+1: computed element value
+2: initial condition
+3: argument vector
+4: length
+5: width
LXi +0: q(capacitor)
+1: i(capacitor)
-107-
++
OJ
u>
3-
S3
g*<*
Qto
++
u>
u»
++
tO*•
*
33
99
99
99
r9
o ao a
w.
aa
*to
OQ
aC
O
1L o
2L8.
9 a
9 cr
fa9 OQ
9 ao
9 a
9"8
«*
Q»
-*
to
9 eo#
9 cr
9 to.
9O
Q
99
99
99
9a
aa
a.
a*a*
cr
••
••
»•
V
99
ao
q9
9a
*o
q9 a
99
99
WO
Q0
0O
Q
S3
9W
}O
a
g2.
3*
-*
5' 5
r 8
++
++
++
++
++
++
++
++
4-+
4-4
-4
-4
.4
.4
.4
.X
J.
^^^^^W
^^^W
^H
^^^W
&^;!*
^'I*
^^M
MM
Mt+
+±
++
++
++
QX
JX
XE
XO
O<
<<
rr
ro
oo
Cfl
MO
ww
tom
to
++
+w
ww
vO
Ms|
zz
zO
ni
o
sa
DO
CO
3C
00
><!
J*X
Xto
wto
to
CW
tfl
00
©N
C o0
3m N
I^
*^2
m-
s
oo
2.
c-
"**
***
a3
lis?
d3
rta
o.
~-
SiF*
S
o.
Ra
aS3
5O
OO
S*
<<
<
Qto
toCO
O a
d
a 3.a 8
1 8B
o9
r*
c-»
CP
a<
to
"
<•
3a
*»
««
<t
c*
8 o
e o 3
**
*
a er
§• 0Q tr
9 P 3
P2
2 i S i
> "8 9 a 03
o 00 I
Append. B
Lxi +0: VBDO +16: QD
+1: VBSO +17: iQD
+2: VGSO +18: CGGBO
+3: VDSO +19: CGDBO
+4: id +20: CGSBO
+5: ibs +21: CBGBO
+6:ibd +22: CBDBO
+7:gm +23: CBSBO
+8:gds +24: QBD
+9: gmbs +25: iQBD
+10: gbd +26: QBS
+11: gbs +27: iQBS
+12: QB +28: CDGBO
+13: iQB +29: CDDBO
+14: QG +30: CDSBO
+15: iQG
Comments :
(1) vto=VFB+PHI+Kl* VPHI -K2*PHI
(2) device mode: +l(-l) for normaKinverse).
(3) If RSH *0.0D0. and NRD * 0.0D0
then at LOCV+13: GDPR=1.0D0/(RSH*NRD)
If RSH 5*0.0D0. and NRS ^O.ODO
then at LOCV+14: GDPR=1.0D0/(RSH*NRS)
-109-
Append. B
B.4. BSIM Model (ID= 25)
LOC -1: subckt info
+0: next pointer
LOCV +0: process name
+1: VFB
+2: LVFB
+3: WVFB
+4: PHI
+5: LPHI
+6: WPHI
+7:K1
+8: LK1
+9: WK1
+10: K2
+11:LK2
+12: WK2
+13: ETA
+14: LETA
+15: WETA
+16: MUZ
+17: DL
+18: DW
+19: U0
+20: LU0
+21: WUO
+l:LOCV
+2: device type
+22: Ul
+23: LU1
+24: WU1
+25: X2MZ
+26: LX2MZ
+27: WX2MZ
+28: X2E
+29: LX2E
+30: WX2E
+31: X3E
+32: LX3E
+33: WX3E
+34: X2U0
+35: LX2U0
+36: WX2U0
+37: X2U1
+38: LX2U1
+39: WX2U1
+40: MUS
+41: LMS
+42: WMS
+43: X2MS +64: NB
+44: LX2MS +65: LNB
+45: WX2MS +66: WNB
+46: X3MS +67: ND
+47: LX3MS +68: LND
+48: WX3MS +69: WND
+49: X3U1
+50: LX3U1
+51: WX3U1
+52: TOX
+53: TEMP
+54: VDD
+55: CGDO
+56: CGSO
+57: CGBO
+58: XPART
+59: DUM1
+60: DUM2
+61: NO
+62: LNO
+63: WNO
-110-
Append. B -Ill-
Comments :
(1) device type:
1 for NMOS
-1 for PMOS
(2) XPART:
1 for the 0/100 channel-charge partitioning method.
0 for the 40/60 channel-charge partitioning method.
0.5 for the 50/50 channel-charge partitioning method.
Append. B
B.5. Interconnect Model (ED=26)
-1: subckt info
LOC +0: next pointer LOCV +0: process name
+I:LOCV +1: RSH
+2: interconnect type +2:CJ
+3: CJW
+4: US
+5:PJ
+6:PJW
+7:MJ
+8: MJW
+9: WDF
+10: DL
Comments :
(l) interconnect type:
I. 2. 3. 4. 5. and 6 for DUl. DU2. DU3. DU4. DU5. and DU6.
7. 8. 9. and 10 for PYl. PY2. PY3. and PY4.
II. 12. 13. and 14 for MLl. ML2. ML3. and ML4.
-112-
Append. C -113-
APPENDEXC
The Transistor Small-Signal Model and Extrinsic Component Models
CI. The Transistor Small-Signal Model
Four transistor model parameters, Vra . 0s •Ki .and K2 are bias-independent, while
the other four bias-dependent parameters. Uo.Uj .7). and 0O (smuOC0W/L) can be
expressed as:
U0 = Uoz + UobVbs (CI)
Ui = U1Z + U1B Vbs + U1D ( Vds" VDD ) (C.2)
•n = T)2 + 7)B Vbs + tjd ( Vds - VDD ) (C.3)
j30 is treated in a different way. It is obtained by the quadratic interpolation through
three data. j30 at ,Vds = 0, /30 at Vds = vdd. and the sensitivity of /30 to VDS at
Vds = VDD.
First. j3q and the derivatives are calculated.
XT = 0z + 0zb Vbs (C.4)
Xa = 0s+0sbVbs (C.5)
Xb = j3SD (C.6)
(l)ForVDs<VDD:
/30 = C, •V§s + C2 •VDS +XT (C.7)
where
„ 2(XA-XT)C2 = £ —- XB (C.8)
vDd
Xb VDd "~ XA + XT1 771 (C9)
Vr
Append. C -114-
and
6ft>
dVos= 2C1VDS + C2 (CIO)
d^° -VA- +VM-4!£- +fc. (cil)dVBS " ^ dVBS
where
6*Q 0ZB— ^
QVbs Vdd
9C2 2 ( 0sB "~ #ZB )
2 (C.12)
6Vbs Vdd
(2) For Vds > VDD :
Linearextrapolation is used for this bias range.
j30 = XA + XB ( Vds ~ VDD ) (C.14)
and
d/30
(C.13)
evDS
60o
dVBS
Second, /3 and the derivatives are obtained.
Let
Arg=l + U0(VGS-Vth) (c.17)
Then,
*-£ (CIS)and
= XB (C.15)
= 0sb (C.16)
Append. C
where
60 _6VGS
0UO
Arg
60 _6Vds
60o
6Vds __ 0/3Arg 6VGS
6Vth
6Vds
60 _
60o
6Vbs + 0-Uo . 6Vth6Vbs Arg Arg QVbs
6Vtb
6Vds= - f) ~ 7)D ' V,DS
0(Vcs"Vth)UoBArg
6Vth
6Vbs= -0.5
K,
V0S"" Vbs+ K2-7)B-V,DS
-115-
(C.19)
(C20)
(C.21)
(C.22)
(C.23)
C.1.1. Transconductance, Output Conductance, and Back-Gate Transconductance
6a _ Kx6VB 2V0s-VBS
g
2(0s%bS)-°-8364(1^)2
Scale Uj and its components by channel length L.
UiU1L =
6U1L u ID
6VDS L
6U1L U1B
6VBS l
(1) Triode Region:
Let
Largl = 1 + U1L VDS
Larg2 = V«-V th ~~
aVDS
(C.24)
(C.25)
(C.26)
(C.27)
(C28)
(C.29)
Append. C -116-
Then.
Larg2-VDs-^- +^VDsnS£ (C30)
Larg2 •V„s ^.+0(Vos - V,„ - Vds •i^.-aVds )8,1 = Urgl
Ids •(Vds |Jii+U1L )_ avDs (C3])Largl
i.™? .v d*8 im r dv'" vds . da •> _, .v aU"-Larg2 Vds aval+gVDS ( aval" — W Ids Vps aw„.«- = njp «"«
(2) Saturation Region:
U,(VGS-Vth)v,. = (C.33)
Sarg =V 1+2 vc (C.34)
K= 1+ Vc +Sarg (C.35)
Sargl = 1+ -2- (C.36)Sarg
6vc U,
6VGS a
( V -V ^ ^LlL6vc KWGS Vtb;6VDS 6ve 6Vth
6Vds a aVGS 6Vds
(C.37)
(C.38)
6vc^(Vcs Vth)6VB7 Uil[6Vb7+ a 6Vb7J (C39)6VBS a
Append. C -117-
(C.40)
(C.41)
(C.42)
(C.43)
Let
Then.
3K _ Sargldve 2
dK _ aK .avcs ave
avc
avcs
aK _ aKavus dve
ave
avos
dK = aK . ave
aVas dve aVes
Sarg2 = ——— (C.44)a * K.
Sarg3 = Sarg2 • ( VGS - Vlh ) (C.45)
C.1.2. Transistor Capacitances
Capacitance expressions corresponding to the 40/60 channel-charge partitioning
method are listed in the following. Capacitance expressions for other partitioning
methods can be obtained in a similar way.
Vlh0 = VFB + 0S + Ki V0s-VBS (C49)
eVth0 =- , Kl (C.50)6VB 2 V0s-VBS
Append. C -118-
Let
Ent =VGS-Vth-l^. (C.51)
VGST=VGs-Vth (C.52)
Vcom =i Vgst2 - | aVDS •VGST +̂ ^- (C.53)
Cox= C0 • Weff • Leff (C.54)
Then.
AE..
(C.55)
(C.56)
(C.57)
fc>=-^- (G58)*^ox
aEnt
avG
aEnt _ aavD 2
aEnt _ avlh0 vKavB avB 2
> da
avB
Q8=£L.Qs=£.^ox ^ox
Qd = -p— . an<^ox
(1) Triode Region:
CO Qg:
3Qg _1+ aVDS2aVG T 12E„7
QQg _ 1 . aVDSaVD 2 6 Ent"
aVDS2 aEnti2Ent2 avD
aQg _ vDS2 aa a Vds2 aEntavB i2Enl avB tteJ "6%
(C.59)
(C.60)
(C.61)
avs Lavc + avD + av7J (C62)
(ii) Qb:
(WD)r °A6 da9 DAeL poe qoe *&e J
°a9
"69
:s0 (A!)
(01*3)r gAe qA& °A9 sA&1 poe poe pt>eJ pbQ
(69'D)aA6 Ofr . aA&[^-.zsaA2B_ +-_.saAsBT +
e . aA& 9_,iuHaAG !aq.iii. . 1 _ —i±2— . S: . **~ . —^— I -&-
bQ isoa . saA B 0,llA& 1SDA b B6 xsPa sa
(890)
(193)
(990)
(£93)
!aG
[AG C1UH _ aAQ Z aAQ Z«3o * woda . saA * £ B© saA on>A0 \
[2OTAz*"y+XS0AsqA*y
92AT
, *IU3 aA0iu-
iu,gO WODA SQA^Z B
wooA . ? a _ r saA B — - isoA -£- i ? a + ±.^A^Z L I A I J saAB r l
,,U3ZI aAG tu,
r aAe qAe °Ae1 qe>e qt>e qoeJ
3 El
%urq ' ( b-1) * «e ' («t -1) z^A-gA$ t _ aAQbo saA oq;A^
(WD)aA6 ,a3JX JU,
3 9IV,3G 2^(8-1)8 ^AC*-!)* B-X
(€93)^u3 Z\
z^A ( • - I ) *
-611-
?0G
3oe
DAe
poe
:pD (m)
sa9
q56
gA9
qoe
qA9
qDe
°A9
q5G
3 -puaddy
Append. C -120-
•*• — [•$.+ •£.+ «*] (C.72)avD avD avD avD
^ =-[|QL +|Qi +̂ ] (C.73)avB avB avB avB
aQs _ r aQs , aQs , aQs, ,„,.Ty- = - [ T7T- + 3T7- + ^^r- J (C.74)avs avG avD avB
(2) Saturation Region:
(i) Qg:
!^ =1-3T <C75>^Qg AdVo" - ° (C76)
aQg_ = _2_. avtho vGST eaaVB 3a aVB T7"Wi (C77)
e^ =_[_dQL +JaQL+aoL]avs• l avG avD + avT (C78)
(ii) Qb:
aQb i iaVc" " 3T " T (C79)
*Qb=oavD
avB M + 3a;^vr TI7" aW (C81)
aQi =.[aQb_ +_aoi+aQb_avs LavG + avD + av^J (C82)
(iii) Qd:
(C.80)
aQd ._ 4avc 15 (C83)
Append. C
aQd
avD\j
dQd 4 avtooavB 15 avB
dQd
avs'-[
aQd
avG
dQd
avD+
aQd,avB
(iv) Qs:
aQs
avG
aQsavD
aQs
avB
aQs
avs
r aQg aQb A aQd tavG avG avG J
r aQg aQb aQd 1avD avD avD J
r aQg_ eQb_ aQd_,avB avB avB J
r aQs aQs x aQs,avG avD avB J
(3) Subthreshold Region:
dQg _
avG
aQg _
avB
aQbavG
aQb
avB avG
i +4(VGs-VFB-VBs)
K?
aQgavG
avc
aQs
All other capacitances are zero.
-121-
(C.84)
(C.85)
(C.86)
(C.87)
(C.88)
(C.89)
(C.90)
(C.91)
(C.92)
(C.93)
(C.94)
Append. C
(4) Accumulation Region:
aQg =1avG
dQ^evB
i = -i
aQb
avG
aQb
avB
= -i
= i
All other capacitances are zero.
-122-
(C.95)
(C.96)
(C.97)
(C.98)
C.2. Extrinsic Component Models
(A) Gate-to-Bulk. Gate-to-Drain, and Gate-to-Source Overlap Capacitances:
C0vgb = Cgb0 • LMK (C.99)
C0vgd —Cgdo •Weff
^ovgs —^gso *We£f
(B) Drain and Source Series Resistances:
Rd = Rsh ' Nrd
Rs = Rsh ' Nrs
(C) drain and source junction currents:
*dt = hs ' Aq
1st = Ijs • As
If not specified. Ist and Idt will default to l.OE-14.
(C.100)
(C.101)
(C.102)
(C.103)
(C.104)
(C.105)
Append. C
(D) Drain and Source Junction Capacitances
Let
Cbda = Cj • AD
Cbsa = Cj • As
Cbdw = Cjw *Pd
Cbsw = Cjw • Ps
(1) drain junction:
ForVBD <0:
-123-
(C.106)
(C.107)
(C.108)
(C.109)
vBD . *[l-(l--p) ]
Qed = Pj *Cbda " : i —m +**JW ^Mw
v 1_MJ»JW
Cpn —'bda 'bdw
V Vr(1_ VjDjMi (1_IBD)M IW
JW
For VRn > 0BD
QbD — VBD • ( Cbda + Cbdw ) + VBD *Cbda'Mj Cbdw-MJW
2 "Pi 2PJW
CBD —Cbda + Cbdw + VBDCbda " Mj Cbdw *Mjw
2) source junction:
For VBS < 0:
JW
JW
1-MJW
(C.110)
(C.lll)
(C.112)
(C.113)
ves - J VBS .l"Miw
Qbs = Pj *Cbsa • * a* + Pjw ' Cbsw •l-Mj l-MJW
Append. C
Ces-'bsw
(i - X*L )M* (i - Ze )m,wPjw
For VBS ^ 0:
Qbs= VBS-(Cbsa + Cbsw) + V&-Cbsa'Mj Cbsw-MJW
2 *Pj 2 • Pjw
Cbs = Cbsa + Cbsw + VasCbsa'Mj Ctev • Mjw
E) Interconnect Resistor:
R - Rsh * h.w.
F) Interconnect Capacitor:
C = Cj • Le •We + 2 • CJW -( Le+ We )
Where
Le = L - 8S . and We = W - 8,
Pjw
-124-
(C.114)
(CI 15)
(CI 16)
(C.117)
(C118)
(C119)
(C120)
Append. D -125-
AFPENDEXD
LISTING OF SUBROUTINE BSIMEQ IN SPICE2 IMPLEMENTATION
SUBROUTINE BSIME0(VDS.VBS.VGS.LOC.GM.GDS.GMBS,OG.OB.QD.
1 CGGB.CGDB.CGSB.CBGB.CBDB.CBSB.CDGB.CDDB.CDSB)
IMPLICIT DOUBLE PRECISION (A-H.O-Z)
C
C THIS ROUTINE EVALUATES THE DRAIN CURRENT. ITS DERIVATIVES AND
C THE CHARGES ASSOCIATED WITH THE'GATE. BULK AND DRAIN TERMINAL
C USING THE BSIM (SHORT-CHANNEL IGFET) MODEL EQUATIONS.
C NEW SPICE SUBROUTINE FOR BSIM MODEL — AUTHOR: BING J. SHEU
C
C SPICE VERSION 2G.6 SCCSID-MOSARG 3/15/83
COMMON /MOSARG/ VTO.BETA.GAMMA,PHI.PHIB.COX.XNSUB.XNFS.XD.XJ.XLD
1 XLAMDA,UO,UEXP,VBP.UTRA.VMAX.XNEFF,XL.XW,VBI.VON.VDSAT,QSPOF.
2 BETA0.BETA1.CDRAIN.XQCO.XOC.FNARRW.FSHORT,LEV
C SPICE VERSION 2G.6 SCCSID-STATUS 3/15/83
COMMON /STATUS/ OMEGA.TIME.DELTA,DELOLD(7).AG(7),VT.XNI.EGFET.
1 XMU.SFACTR.MODE.MODEDC.ICALC.INITF.METHOD.IORD.MAXORD.NONCON.
2 ITERNC.ITEMNO.NOSOLV.MODAC.IPIV.IVMFLG.IPOSTP.ISCRCH.IOFILE
C SPICE VERSION 2G.6 SCCSID-KNSTNT 3/15/83
COMMON /KNSTNT/ TWOPI.XLOG2.XLOG10.R0OT2.RAD.BOLTZ.CHARGE.CTOK.
1 GMIN,RELTOL,ABSTOL.VNTOL.TRTOL.CHGTOL.EPS0.EPSSIL.EPSOX.
2 PIVTOL.PIVREL
COMMON /BLANK/ VALUE(200000)
INTEGER N0DPLC(64)
COMPLEX CVALUE(32)
EQUIVALENCE (VALUE(1),N0DPLC(1),CVALUE(1))
C
ICHARG=1
IF (MODE NE. 1) GO TO 5
IF (MODEDC .EQ. 2 .AND. NOSOLV .NE. 0) GO TO 5
IF (INITF .EQ. 4) GO TO 5
ICHARG=0
Append. D _126_
5 L0CV-N0DPLC(L0C+1)
LOCM-NODPLC(LOC+8)
LOCM=NODPLC(LOCM+1)
VFB=VALUE(L0CV+17)
PHI=VALUE(LOCV+18)
XK1=VALUE(LOCV+19)
XK2»VALUE(LOCV+20)
VDD=VALUE(LOCM+54)
U0=VALUE(LOCV+23)+VBS*VALUE(LOCV+28)
U1=VALUE(LOCV+24)+VBS*VALUE(LOCV+29)
1 +(VDS-VDD)*VALUE(LOCV+33)
DU0DVB»VALUE(LOCV+28)
C
XLU-VALUE(LOCV+1)•1.0D6
U1-U1/XLU
DU1DVB-VALUE(LOCV+29)/XLU
DU1DVD-VALUE(L0CV+33)/XLU
C
10 ETA=VALUE(LOCV+21)+VALUE(LOCV+26)*VBS+VALUE(LOCV+27)»(VDS-VDD)
DETDVB=VALUE(LOCV+26)
DETDVD=VALUE(LOCV+27)
C
IF (VBS .GE. 0.0D0) GO TO 14
VPB=PHI-VBS
GO TO 15
14 VPB=PHI
15 SQRVPB-OSQRT(VPB)
C
C DO NOT REMOVE THE VARIABLE "VON"
C
VON»VFB+PHI+XK1»SQRVPB-XK2«VPB-ETA»VDS
VTH=VON
DVTDVD=-ETA-VDS*DETDVD
Append. D
DVTDVB-XK2-0.5D0*XK1/SQRVPB-VDS»DETDVBVGT=VGS-VTH
IF (VGT .GE. 0.0D0) GO TO 20
C
C CUT-OFF REGION
C
CDRAIN-O.0D0
GM-O.OD0
GDS»0.0D0
GMBS-0.OD0
GO TO 100
C
20 G-1.0DO-1.0D0/(1.744D0+0.8364»VPB)
A-1.0D0+0.5D0*G»XK1/SQRVPB
DGDVBS»-0.8364D0»(1.0D0-G)*(1.0D0-G)
DADVBS-0.25D0*XK1/SQRVPB*(2.0D0*DGDVBS+G/VPB)
ARG=1.0D0+U0*VGT
C
C LIMIT ARG
C
IF (ARG .LT. 0.1D0) ARG-0.1D0
C
C QUADRATIC INTERPOLATION FOR BETA0 VALUE
C
XT=VALUE(LOCV+22)+VBS*VALUE(LOCV+25)
XA=VALUE(LOCV+30)+VBS*VALUE(LOCV+3l)
XB=VALUE(LOCV+32)
IF (VDS .LE. VDD) CO TO 25
BETA0=XA+XB«(VDS-VDD)
DBODVD=XB
DB0DVB=VALUE(LOCV+31)
GO TO 30
-127-
Append. D-128-
25 VDD2=VDD«VDD
C1»(XB*VDD-XA+XT)/VDD2
C2=2.0D0*(XA-XT)/VDD-XB
DXTDVB=VALUE(LOCV+25)
DXADVB=VALUE(L0CV+31)
DC1DVB=(-DXADVB+DXTDVB)/VDD2
DC2DVB-2.0D0«(DXADVB-DXTDVB)/VDD
BETA0o(C1«VDS-fC2 )*VDS+XT
DB0DVD-2.0D0*C1*VDS+C2
DB0DVB»DC1DVB*VDS*VDS+DC2DVB*VDS+DXTDVB
30 BETA=BETA0/ARG-
DBDVGS=-BETA»U0/ARG
DBDVDS=DB0DVD/ARG-DBDVGS*DVTDVD
DBDVBS«DB0DVB/ARG+BETA*U0*OVTDVB/ARG
1 -BETA«VGT*DU0DVB/ARG
C
C LIMIT VC
C
VC-U1*VGT/A
IF (VC .LT. -0.4D0) VC—0.4D0
TERM1»DSQRT(1.000+2.0D0«VC)
XK-0.5D0.(1.0D0+VC+TERM1)
VDSAT«VGT/(A«DSQRT(XK))
IF (VDSAT .LT. 0.0D0) VDSAT-0.0D0
IF (VDS .GE. VDSAT) GO TO 50
C
C TRIODE REGION
C
ARGL1-1.0D0+U1-VDS
C
C LIMIT ARGL1
C
Append. D -129-
IF (ARGL1 .LT. 0.1D0) ARGL1-0.1D0
ARGL2=VGT-0.5D0»A-VDS
CDRAIN«BETA»ARGL2*VDS/ARGL1
GM=(DBDVGS*ARGL2*VDS+BETA»VDS)/ARGL1
GDS=(DBDVDS»ARGL2«VDS+BETA»(VGT-VDS»DVTDVD-A»VDS)
1 -CDRAIN*(VDS»DU1DVD+U1))/ARGL1
GMBS=(DBDVBS*ARGL2*VDS+BETA*VDS*(-DVTDVB-0.5D0«VDS*DADVBS)
2 -CDRAIN»VDS«DU1DVB)/ARGL1
GO TO 100
C
C SATURATION REGION
C
50 ARGS1-1.0D0+1.0D0/TERM1
DVCDVG-U1/A
DVCDVD=VGT-DU1DVD/A-DVCDVG*DVTDVD
DVCDVB»(VGT»DU1DVB-U1*(DVTDVB+VGT»DADVBS/A))/A
DKDVC-O.5D0*ARGS1
DKDVGS»DKDVC*DVCDVG
DKDVDS-DKDVC*DVCDVD
DKDVBS«DKDVC»DVCDVB
ARGS2-VGT/(A*XK)
ARGS3-ARGS2*VGT
CDRAIN-0.5D0*BETA«ARGS3
GM-0.5D0*ARGS3*DBDVGS+BETA*ARGS2-CDRAIN*DKDVGS/XK
GDS-0.5D0»ARGS3«DBDVDS-BETA*ARGS2*DVTDVD-CDRAIN*DKDVDS/XK
GMBS-0.5D0*OBDVBS«ARGS3-BETA«ARGS2*DVTDVB
1 -CDRAIN*(DADVBS/A+DKDVBS/XK)
C
C INCLUDING THE WEAK INVERSION CONDUCTION. IF STHD IS NOT SPECIFIED.
C THEN 200.0 IS STORED AT VALUE(LOCV+37)
C
100 XN0-VALUE(LOCV+37)
Append. D -130"
XCUTH-3.5D1«XN0*VT
IF ((XN0 .GE. 2.0D2) .OR. (VGT .LT. -XCUTH)) GO TO 150
XNB-VALUE(LOCV+38)
XND-VALUE(LOCV+39)
XN=XN0+XNB«VBS+XND*VDS
C
C LIMIT XN
C
IF (XN .LT. 0.5D0) XN=0.5D0
ONXN-1 0D0/XN
ONVT=»1.0D0/VT
ONDVT»ONXN*ONVT
C AVOID UNDERFLOW
WARG1-0.0D0
TERMW1=VDS*ONVT
IF (TERMW1 .LT. 3.5D1) WARG1=DEXP(-TERMW1 )
WDS-1.0D0-WARG1
C AVOID OVERFLOW
WGS-1.6D15
IF (VGT .LT. XCUTH) WGS=DEXP(VGT*ONDVT)
VT2=VT»VT
EXP18=DEXP(1.800)
WARG2=VALUE(L0CV+22)*VT2«EXP18
CISL=VALUE(LOCV+22)*4.5D0»VT2
CIEXP-WARG2 *WGS*WDS
CDEN-CISL+CIEXP
CDRAIN»CDRAIN+CISL«CIEXP/CDEN
XC0M1-CISL«CISL/(CDEN«CDEN)
GM-GM+XC0M1*CIEXP«0NDVT
GDS-GDS+XC0M1*WARG2»WGS*(-WDS*0NDVT«(DVTDVD+VGT*XND*0NXN)1 +WARG1»0NVT)
GMBS-GMBS-XC0M1«CIEXP«(DVTDVB+VGT»XNB»ONXN)»ONDVT150 CONTINUE
Append. D-131-
c
C LIMIT CDRAIN. GM. GDS. GMBS
C
IF (CDRAIN .LT. 0.0D0) CDRAIN-0.0D0
IF (GM .LT. 0.0D0) GM-0.0D0
IF (GDS .LT. 0.0D0) GDS-0.0D0
IF (GMBS .LT. 0.0D0) GMBS-0.0D0
C
200 IF (ICHARG .EQ. 0) GO TO 900
C
C COMMON BLOCK FOR ALL PARTITIONING METHODS
C
COX=VALUE(LOCV+1)»VALUE(LOCV+2)«EPSOX/VALUE(LOCM+52)
VTHO-VFB+PHI+XK1»SQRVPB
VGST-VGS-VTHO
ARG1-A*VDS
C ARG2=VGST-0.5D0«ARG1
ENT-VGST-0.5D0-ARG1
ARG3-VDS-ARG1
ARG4-ARG2O2.0D0
ARG5°ARG1*ARG1
DVTDVB»-0.5D0«XK1/SQRVPB
DADVB=0.5D0*XK1•(0.5D0*G/VPB-0.8364D0*(1-G)*(1-G))/SQRVPB
IF (ENT .LT. 1.0D-8) ENT-1.0D-8
DETDVD=-0.5D0*A
DETDVB=-DVTDVB-0.5D0»VDS*DADVB
VGST2=VGST»VGST
VDS2=VDS*VDS
C
C EVALUATE THE GATE. BULK. AND DRAIN CHARGES AND CAPACITANCES
C
XPART=VALUE(LOCV+1 6)
IF (XPART .GE. 1.0D0) GO TO 400
Append. D _132_
IF (XPART .NE. 0.5D0) GO TO 500
C
C 50/50 PARTITIONING FOR DRAIN/SOURCE CHARGES AT THE SATURATION REGION
C
IF (VGS .LE. VTHO) GO TO 350
C
VDPOF-VGST/A
IF (VDS .GT. VDPOF) GO TO 330
C
C TRIODE REGION
C
ENT2-ENT«ENT
ARGL1-1.2D1*ENT2
ARGL2-1.0D0-A
ARGL3=ARG1*VDS
ARGL5-2.0D0
IF (ENT .GT. 1.0D-8) ARGL5-ARG1/ENT
ARGL7-ARGL5/1.2D1
ARGL8»6.0D0*ENT
QG-COX*(VGS-VFB-PHI-0.5D0»VDS+VDS*ARGL7)
QB»COX*(-VTHO+VFB+PHI+0.5D0»ARG3-ARG3*ARGL7)
QD=-0.5D0*(QG+QB)
CGGB-COX*(1 .0D0-ARGL3/ARGL1 )
CGDB=COX« (-0 .5D0+ARG1/ARGL8-ARGL3*DETDVD/ARGL1 )
CGBB=C0X«(VDS2*DADVB«ENT-ARGL3*DETDVB)/ARGL1
CGSB«-(CGGB+CGDB+CGB8)
CBGB-C0X«ARGL3*ARGL2/ARGL1
CBDB=C0X«ARGL2«(0.5D0-ARG1/ARGL8+ARGL3*DETDVD/ARGL1)
CBBB—COX* (DVTDVB+0 .5D0»VDS*DADVB+VDS2*((1.0D0-2.0D0*A)
1 •DADVB«ENT-ARGL2»A«DETDVB)/ARGL1)
CBSB«-(CBGB+CBD*B+CBBB)
CDGB—0 .5D0* (CGGB+CBGB)
CDDB=-0.5D0«(CGDB+CBDB)
Append. D -133-
CDSB—0 . 5D0»(CGSB+CBSB)
GO TO 1000
C
C SATURATION REGION
C
330 CON1V3-1.0D0/3.0D0
ARGS1-CON1V3/A
QG-COX*(VGS-VFB-PHI-VGST«ARGS1 )
QB=COX»(VFB+PHI-VTHO+(1.0DO-A)*VGST»ARGS1)
QD—C0N1V3«C0X»VGST
CGGB-COX•(1.0D0-ARGS1)
CGDB-0.OD©
CGBB-COX«ARGS1*(DVTDVB+VGST*DADVB/A)
CGSB—(CGGB+CGDB+CGBB)
CDGB—COX«CON1V3
CDDB-0.0D0
CDBB-CON1V3*COX*DVTDVB
CDSB—(CDGB+CDDB+CDBB)
CBG8—(CGGB+2. 0D0«CDGB)
CBDB-O.ODO
CBSB—(CGSB+2. 0D0«CDSB)
GO TO 1000
C
C SUBTHRESHOLD REGION
C
350 VGSMV1=VGS-(VFB+VBS)
IF (VGSMV1 .LE. 0.0D0) GO TO 370
XK1S=XK1*XK1
OG»0.5D0*COX*XK1S«(-1.0D0+DSQRT(1.0D0
1 +4.0D0»VGSMV1/XK1S))
QB—QG
QD-0.0D0
CGGB=COX/DSORT( 1 . 0D0+4 . 0D0»VGSMV1./XK1 S)
Append. D _134
CGDB-0.0D0
CGSB-0.0D0
CBGB—CGGB
CBDB-0.0D0
CBSB-0.0D0
CDGB-0.000
CDDB=0.0D0
CDSB-0.0D0
GO TO 1000
C
C ACCUMULATION REGION
C
370 QG=COX«VGSMV1
OB—QG
QD-0.0D©
CGGB-C0X
CGDB-0.0D0
CGSB-0.0D0
CBGB—COX
CBDB-0.000
CBS8-0.0D0
CDGB°0.0O0
CDDB-0.0D0
CDSB-0.0D0
GO TO 1000
C
C 0/100 PARTITIONING FOR DRAIN/SOURCE CHARGES AT THE SATURATION REGIONC
400 IF (VGS .LE. VTHO) GO TO 350
C
VDPOF-VGST/A
IF (VDS .GT. VDPOF) GO TO 430
C
Append. D-135-
C TRIODE REGION
C
ENT2«ENT*ENT
ARGL1-1.2D1*ENT2
ARGL2-1.0D0-A
ARGL3=ARG1*VDS
ARGL5=2.0D0
IF (ENT .GT. 1.0D-8) ARGL5-ARG1/ENT
ARGL7=ARGL5/1.2D1
ARGL8=6.0D0»ENT
ARGL9=0.125D0*ARGL5*ARGL5
QG=COX*(VGS-VFB-PHI-0.5D0»VDS+VDS»ARGL7)
C QB=COX«(-VTHO+VFB+PHI+0.5D0*ARG3-ARG3*ARGL7)
QB=COX* (-VTHO+VFB+PHI+ARG3*(0. 5D0.-ARGL7) )
QD—COX* (0.5D0*VGST-0.75D0*ARG1+0.125D0*ARG1*ARGL5)
CGGB=COX*(l.0D0-ARGL3/ARGL1)
CGDB»COX*(-0.5D0+ARG1/ARGL8-ARGL3*DETDVD/ARGL1)
CGBB=COX*(VDS2*DADVB*ENT-ARGL3*DETDVB)/ARGL1
CGSB— ( CGGB+CGDB+CGBB )
CBGB«COX*ARGL3*ARGL2/ARGL1
CBDB-C0X*ARGL2*(0.5D0-ARG1/ARGL8+ARGL3*DETDVD/ARGL1)
CBBB—COX*(DVTDVB+0.5D0«VDS*DADVB+VDS2*((1.0D0-2.0D0*A)
1 *DADVB*ENT-ARGL2*A*DETDVB)/ARGL1)
CBSB— (CBGB+CBDB+CBBB)
CDGB—COX• ( 0 . 5D0-ARGL9 )
CDDB-COX*(0.75D0-A-0.25D0*A*ARG1/ENT+ARGL9*DETDVD)
CDBB-COX*(0.5D0*DVTDVB+VDS*DADVB*(0.75D0-0.25D0*ARGL5)
1 +ARGL9*DETDVB)
CDSB— (CDGB+CDDB+CDBB)
GO TO 1000
C
C SATURATION REGION
C
Append. D-136-
430 C0N1V3-1.000/3.0D0
ARGS1-CON1V3/A
QG»C0X*(VGS-VFB-PHI-VGST*ARGS1)
0B=C0X*(VFB+PHI-VTH0+(1.0D0-A)*VGST*ARGS1)
QD=0.0D0
CGGB=C0X*(1.0D0-ARGS1)
CGDB-0.0D0
CGBB=COX*ARGS1*(DVTDVB+VGST*DADVB/A)
CGSB—(CGGB+CGDB+CGBB)
CBGB-C0X*(ARGS1-C0N1V3)
CBDB=©.0DO
CBBB—COX*((1,0D0-CON1V3+ARGS1)*DVTDVB+VGST*ARGS1*DADVB/A)
CBSB—(CBGB+CBDB+CBBB)
CDGB=0.0D0
CDDB=0.0D0
CDSB=0.0D0
GO TO 1000
C
C 40/60 PARTITIONING FOR DRAIN/SOURCE CHARGES AT THE SATURATION REGION
C
500 VCOM=VGST*VGST/6.0D0-1.25D-1*ARG1*VGST+2.5D-2*ARG5
IF (VGS .LE. VTHO) GO TO 350
C
VDPOF-VGST/A
IF (VDS .GT. VDPOF) GO TO 530
C
C TRIODE REGION
C
ENT2-ENT*ENT
ARGL1-1.2D1*ENT2
ARGL2-1.0D0-A
ARGL3<°ARG1*VDS
ARGL4-VC0M/ENT/ENT2
Append. D -137-
IF (ENT .LE. 1.0D-8) GO TO 520
ARGL5-ARG1/ENT
ARGL6-VCOM/ENT2
GO TO 525
520 ARGL5-2.0DO
ARGL6-4.0D0/1.5D1
525 ARGL7-ARGL5/1.201
ARGL8«6.0D0*ENT m
QG=COX*(VGS-VFB-PHI-0.5D0*VDS+VDS*ARGL7)
QB=COX*(-VTHO+VFB+PHI+0.5D0*ARG3-ARG3*ARGL7)
QD—COX*(0.5D0*(VGST-ARG1)+ARG1*ARGL6)
CGGB-COX*(1.0D0-ARGL3/ARGL1)
CGDB=COX*(-0.5D0+ARG1/ARGL8-ARGL3*DETDVD/ARGL1)
CGBB=COX*(VDS2*DADVB*ENT-ARGL3*DETDVB)/ARGL1
CGSB—(CGGB+CGDB+CGB8)
CBGB=COX*ARGL3*ARGL2/ARGL1
CBDB=COX*ARGL2*(0.5D0-ARG1/ARGL8+ARGL3*DETDVD/ARGL1)
CBBB=-COX*(DVTDVB+0.5D0*VDS-DADVB+VDS2*((1.0D0-2.0D0«A)
1 *DADVB*ENT-ARGL2*A*DETDVB)/ARGL1)
CBSB—(CBGB+CBDB+CBBB)
CDGB—COX* (0.5D0+ARG1 •(4.0D0*VGST-1 .5D0*ARG1)/ARGL1
1 -2.0D0*ARG.1*ARGL4)
• CDDB=COX*(0.5D0*A+2.0D0*ARG1*DETDVD*ARGL4-A*(2.0D0*VGST2
1 -3.0D0*ARG1*VGST+0.9D0*ARG5)/ARGL1)
CDBB=COX*(0.5D0*DVTDVB+O.5D0*VDS*DADVB+2.0D0»ARG1•DETDVB
1 •ARGL4-VDS*(2.0D0*VGST2*DADVB-4.0D0*A*VGST*DVTDVB-3.0D0
2 *ARG1*VGST»DADVB+1.5D0*A*ARG1-OVTOVB+O.9D0*ARG5*DADVB)
3 /ARGL1)
CDSB—(CDGB+CDDB+CDBB)
GO TO 1000
C
C SATURATION REGION
C
Append. D-138-
530 C0N1V3-1.0D0/3.0D0
CO4V15-4.0D0/1.501
ARGS1-1.000/(3.0D0*A)
QG-C0X*(VGS-VFB-PHI-VGST*ARGS1)
OB-COX*(VFB+PHI-VTH0+(1.0DO-A)*VGST*ARGS1)
OD—904V15*COX*VGST
CGGB-C0X*(1.0D0-ARGS1)
CGDB-O.ODO
CGBB-C0X*ARGS1*(DVTDVB+VGST*DADVB/A)
CGSB—(CGGB+CGDB+CGBB)
CBGB«C0X*(ARGS1-C0N1V3)
CBDB-0.OD©
CBBB—COX*((1.0DO-CON1V3+ARGS1)*DVTDVB-VGST*ARGS1*DADVB/A)
CBSB—(CBGB+CBDB+CBBB)
CDGB—C04V1 5*C0X
CDDB-0.0D0
CDBB=C04V15*C0X«DVTDVB
CDSB—(CDGB+CDDB+CDBB)
GO TO 1000
900 QG-O.0D0
QB-O.0D0
QC-O.0D0
1000 RETURN
END
Append. E _139
APPENDIX E
BENCHMARK CIRCUITS
Example - 1
RATLOG - RATIOLESS DYNAMIC LOGIC CIRCUIT
••••* ANALYSIS CONTROL *****
•WIDTH IN-72 OUT-80
•OPT ABST0L-1U
.OPT ACCT
*•••• DEVICES •**••
SM1 9 11 2 10 PC1.NM1 W-20U L-7U AD-1N AS-1N
SM2 9 12 4 10 PC1_NM1 W-20U L-7U AD-1N AS-1N
SM3 2 1 0 10 PC1_NM1 W-20U L-7U AD-1N AS-1N
SM4 4 3 0 10 PC1_NM1 W-20U L-7U AD-1N AS-1N
SM5 3 12 2 10 PC1_NM1 W-20U L-7U AD-1N AS-1N
SM6 1 11 5 10 PC1_NM1 W-20U L-7U AD-1N AS-1N
•PROCESS PC1 FILENAME-CB0716
C1 1 0 0.O5PF
C2 2 0 0.05PF
C3 3 0 0.O5PF
C4 4 0 0.05PF
C5 5 0 0.05PF
••••* POWER SUPPLY AND SIGNAL
VIN 5 0 PULSE(0 1.0 10N 5N 10N 55N 500N)
VP1 11 0 PULSE(0 12 10N 5N 5N 35N 120N)
VP2 12 0 PULSE(0 12 70N 5N 5N 35N 120N)
VDD 9 0 DC 12
VBB 10 0
•*••• ANALYSIS REQUEST •••••
•TRAN 2.5N 250N
•PLOT TRAN V(4) V(5)
•PLOT TRAN V(4) V(1) V(2) V(3) V(5) V(11) V(12) (-5.15)
• END
Append. E -140-
Example - 2
INVCHN - FIVE-STAGE SATURATED INVERTER CHAIN
• •••• ANALYSIS CONTROL *****
•WIDTH IN-72 OUT-80
•OPT DEFAD-1E-12 DEFAS-1E-12
•OPT ACCT
DEVICES ***••
2 8 PC1.NM1 W-10U L-8U
0 8 PC1.NM1 W-70U L-8U
3 8 PC1.NM1 W-10U L-8U
0 8 PC1.NM1 W-70U L-8U
4 8 PC1.NM1 W-10U L-8U
0 8 PC1.NM1 W-70U L-8U
5 8 PC1.NM1 W-10U L-8U
0 8 PC1.NM1 W-70U L-8U
6 8 PC1.NM1 W-10U L-8U
0 8 PC1.NM1 W-70U L-8U
•PROCESS PCI FILENAME-CC0716
***** POWER SUPPLY AND SIGNAL *****
VIN 1 0 PULSE(5 0 0.2N 1N 1N 5N 12N)
VDD 7 0 DC 6
VBB 8 0 DC 0
••*•• ANALYSIS REQUEST
• OP
•TRAN 0.12N 12N
•PLOT TRAN V(2) V(3) V(4) V(5) V(6) V(1) (-1.5)
• END
SM1
DE
7
VIi
7
SM2 2 1
SM3 7 7
SM4 3 2
SM5 7 7
SM6 4 3
SM7 7 7
SM8 5 4
SM9 7 7
SM10 6 5
Append. E -141-
Example -3
BOOTINV - BOOTSTRAPPED DOUBLE INVERTER CIRCUIT
••••• ANALYSIS CONTROL
•WIDTH IN-72 OUT-80
•OPT ABSTOL-10U
•OPT ACCT
••••• DEVICES •••••
SM1 1 1 3 6 PC1.NM1 W-10U L-7U AD-O.02P AS-0.02P
SM2 3 2 0 6 PC1.NM1 W-50U L-7U AD-2P AS-0.O2P
SM3 1 1 4 6 PC1_NM1 W-IOU L-7U ' AD-0.2P AS-0.2P
SM4 14 5 6 PC1_NM1 W-10U L-7U AD-0.02P AS-O.02P
SM5 5 3 0 6 PC1_NM1 W-50U L-7U AD-2P AS-O.02P
•PROCESS PC1 FILENAME-CD0716
CL5 5 0 0.1PF
CL2 3 0 O.IPF
CB4 4 5 O.IPF
*••*• POWER SUPPLY AND SIGNAL ••*•*
VDD 1 0 DC 12
VBB 6 0 DC -4
VIN 2 0 PULSE(10 0.4 INS 2NS 2NS 13NS 20NS)••*•• ANALYSIS REQUEST •••••
• OP
.TRAN 0.2NS 20NS
.PLOT TRAN V(5) V(2)
•PLOT TRAN V(2) V(3) V(4) V(5)
• END
Append. E -142-
Example - 4
M0SAMP1 - MOS AMPLIFIER - DC/AC
••••* ANALYSIS CONTROL •••••
•WIDTH OUT-80
•OPT ACCT
•OPT ABSTOL-10N VNTOL-10N
•OPT DEFAD-10P DEFAS-10P
***** DEVICES •••••
SM1 15 15 1 32 PC1_NM1 W-88.9U L-25.4U
2 32 PC1_NM1 W-12.7U L-266.7U
30 32 PC1.NM1 W-88.9U L-25.4U
4 32 PC1_NM1 W-12.7U L-106.7U
30 32 PC1.NM1 W-88.9U L-12.7U
5 32 PC1.NM1 W-44.5U L-25.4U
8 32 PC1.NM1 W-482.6U L-12.7U
30 32 PC1.NM1 W-88.9U L-25.4U
6 32 PC1_NM1 W-44.5U L-25.4U
8 32 PC1_NM1 W-482.6U L-12.7U
7 32 PC1_NM1 W-12.7U L-106.7U
30 32 PC1_NM1 W-88.9U L-12.7U
9 32 PC1_NM1 W-139.7U L-12.7U
30 32 PC1_NM1 W-139.7U L-12.7U
SM15 15 15 12 32 PC1_NM1 W-12.7U L-207.8U
SM16 12 12 11 32 PC1_NM1 W-54.1U L-12.7U
SM17 11 11 30 32 PC1.NM1 W-54.1U L-12.7U
SM18 15 15 10 32 PC1_NM1 W-12.7U L-45.2U
SM19 10 12 13 32 PC1_NM1 W-270.5U L-12.7U
SM20 13 7 30 32 PC1.NM1 W-270.5U L-12.7U
SM21 15 10 14 32 PC1_NM1 W=254U L-12.7U
SM22 14 11 30 32 PC1.NM1 W=241.3U L-12.7U
SM23 15 20 16 32 PC1.NM1 W-19U L-38.1U
SM2 1 1
SM3 2 2
SM4 15 5
SM5 4 4
SM6 15 15
SM7 5 0
SM8 8 2
SM9 15 15
SM10 6 21
SM11 15 6
SM12 7 4
SM13 15 10
SM14 9 11
Append. E-143-
SM24 16 14 30 32 PC1.NM1 W=406.4U L=12.7U
SM25 15 15 20 32 PC1.NM1 W=38.1U L-42.7U
SM26 20 16 30 32 PC1_NM1 W=381U L=25.4U
SM27 20 15 66 32 PC1_NM1 W=22.9U L=7.6U
•PROCESS PC1 FILENAME-CL0716
CC 7 9 40PF
CL 66 0 70PF
•**•• POWER SUPPLY AND SIGNAL •••••
VIN 21 0 DC 15MV AC 1
VCCP 15 0 DC +15
VCCN 30 0 DC -15
VB 32 0 DC -20
•OP
•DC VIN -18MV 48MV 0.66MV
•AC DEC 10 100 10MEG
•PLOT DC V(20)
•PLOT AC VDB(20) VP(20) VDB(66) VP(66)
•END
Append. E _144_
Example - 5
BINARY-TO-OCTAL DECODER CIRCUIT
•WIDTH OUT-80
•PROCESS PC1 FILENAME-CK0716
*•• NO JS, NO CBD & CBS
•DEVICE MODELS
• SUBCIRCUIT MODELS
•SUBCKT NAND 1 2 3 100
SM1 100 3 3 0 PC1.NM3 W-20U L-9.5U
SM2 3 14 0 PC1_NM1 W-20U L-2.3U
SM3 4 2 0 0 PC1.NM1 W-20U L-2.3U
•ENDS NAND
•SUBCKT NOR 1 2 3 100
SMI 100 3 3 0 PC1.NM3 W-20U L-9.5U
SM2 3 10 0 PC1.NM1 W-20U L-2.3U
SM3 3 2 0 0 PC1.NM1 W-20U L-2.3U
•ENDS NOR
•SUBCKT INV 1 2 100
SM1 100 2 2 0 PC1.NM3 W-20U L-9.5U
SM2 2 10 0 PC1.NM1 W-20U L-2.3U
•ENDS INV
• INPUT SIGNAL INVERTERS
X15 1 5 100 INV
X16 2 6 100 INV
X17 3 7 100 INV
• NOR GATES
X1 5 6 9 100 NOR
X2 2 5 10 100 NOR
X3 1 6 11 100 NOR
X4 1 2 12 100 NOR
X5 3 4 13 100 NOR
Append. E-145-
X6 4 7 14 100 NOR
• NAND GATES
X7 12 13 17 100 NAND
X8 10 13 18 100 NAND
X9 11 13 19 100 NAND
X10 9 13 20 100 NAND
X11 12 14 21 100 NAND
X12 10 14 22 100 NANO
X13 11 14 23 100 NAND
X14 9 14 24 100 NAND
* INPUT SOURCES
VCC 100 0 DC 5
VA 1 0 PULSE(5 0 5NS 10NS IONS 20NS 60NS)
VB 2 0 PULSE(5 0 45NS 10NS 10NS 50NS 120NS)
VC 3 0 PULSE(5 0 105NS 10NS 10NS 110NS 240NS)
VD 4 0 DC 0
•ANALYSIS REQUESTS
•TRAN 1.2NS 240NS
.PLOT TRAN V(17) V(18) V(19) V(20)
+ V(21) V(22) V(23) V(24) (0.5)
•OPT ACCT DEFAS-1N DEFAD-1N
+ RELT0L-1M ABST0L-1N VNT0L-1N LVLTIM-1
• .OP
• .OPT ACCT DEFAS-1N DEFAD-1N
• + RELT0L-1M ABST0L-1N VNT0L-1N LVLTIM-1
.END
Append. F -146-
APPENDDCF
SOURCE-DRAIN SERIES RESISTANCE OF UGHTLY-DOPED-DRAINMOS TRANSISTORS
F.l. Introduction
As MOS transistor device size continues to shrink, the degradation of electrical
characteristics induced by hot-carrier effects becomes increasingly severe. Device break
down or degradation and substrate current due to impact ionization have become prob
lems for aggressively-scaled devices. Recent work on lightly-doped-drain (LDD) devices
[F.l]-[F.7] is an effort to alleviate the above-mentioned problems. In the LDD device,
self-aligned n" regions are introduced between the channel and the n+ drain and source
diffusions. The n~ source is not really necessary unless the device is to be operated
bidirectionally. However, to eliminate the n~ source would require an additional mask
step. Advantages of the LDD structure are many. It increases the transistor breakdown
voltage and reduces impact ionization (and thus hot-carrier effects) by allowing the high
electric field at the drain region to extend into the n~ region.
The n~ dimensions and dopant concentration are determined by the desired
improvement in breakdown voltage, short-channel threshold-voltage falloff. and other
electrical characteristics [F.2]. However, the introduction of the n~ region increases the
source-drain resistance and degrades the transistor current-driving capability to below
that of a conventional MOS transistor with the same channel length.
In this work, the characteristic of source-drain series resistance and the effective
channel length of an LDD MOS transistor at a small drain bias are studied. An analyti
cal model for the source-drain series resistance is presented.
F.2. The Model
Append. F -147-
The measured channel resistance. RM = Vds/Ids . is [F.8.F.9]
_ UsRm-Rsd+ A.[Vcs-vTr (F1)
where
A=TTTvfc^T- G=̂ c»w- ™Rsd = Rs + RD • (F.3)
Here. Rs is the source resistance. RD is the drain resistance. U0 is the mobility degrada
tion coefficient, and G is the conductance coefficient. Voltage VgS sVgs-IdsRs is the
effective gate bias for the intrinsic active region, as explained in the insert of Fig. F.l.
For a conventional MOS transistor. RSD is a constant and plots of RM versus mask-level
(or drawn) channel length. Lmk »for different large gate biases at a fixed small drain
bias intersect at one point where the channel-length reduction. AL = LMk~~ Leff» and
source-drain series resistance. Rsd . are determined. The source-drain series resistance
consists of the contact resistance, diffusion resistance, and spreading resistance resulting
from the current-crowding effect [F.10].
The electric field emerging from the gate electrode modulates the carrier concentra
tion of the gate-overlapped n" region directly. The external n~ region is modulated by
the gate through fringing fields. Therefore, source-drain series resistance is strongly
gate-bias-dependent. Figure F.l shows the plots of RM versus LMK for an LDD MOS
transistor. Lines corresponding to different gate biases fail to intersect at a single point.
The traditional method to electrically determine effective channel length and source-
drain series resistance can not be directly applied because it assumes the effective chan
nel length and source-drain series resistance are independent of the gate bias. Figure F.2
shows schematic diagrams of the effective channel at high and low gate biases. At a high
Vgs-Vt bias condition, the amount of induced mobile carriers can be comparable to the
Append. F
10
RM(kil)
Vos « lOOmV
VBS « OVVro 3 0.59V
-148-
Fig. F.l Measured channel resistance versus mask-level channel length for severalgate biases. Definitions of different biasing voltages are shown in theinsert.
Append. F -149-
6ATE
'eflf
L°w VGS " VT bias
Ca)
GATE
High VGS - VT bias
(b)
Fig. F.2 Current flow patterns in an LDD MOS transistor.(a) Low Vcs —VT condition.(b) High Vgs —Vx condition.
Append. F -150-
n~ region implant dose. However, the mobile carriers are confined within a layer which
is much thinner than the n" region junction. The conduction channel ends near the n~-
to-n+ junction. For a low VGS-VT bias condition, the conduction channel ends at the
n"-to-" intrinsic active region" junction. The effective channel length is also gate-bias
dependent.
The measured channel resistance at a small drain bias can be expressed as
RM =Rso(VoS) +TTr^-]. (F.4)
The gate-controlled n~ region can be regarded as a depletion-mode MOS device with the
donor dopant as the threshold-voltage adjustment implant [F.ll]. Let VTn_ denote the
effective threshold voltage for this gate-controlled n" region. The source-drain series
resistance. RSD . in Eq. (F.4) can be expressed as
Rsd =Rf+b-Iv0S-vt„.J <">
where RF is the constant component of RSD. The parameter B is a function of carrier
mobility, gate-oxide capacitance, channel width, and the length of the n~ region. The
method to determine RF. B. and VTn_ from RSD - Vcs characteristic is described in the
next section with an example. With this interpretation of RSd . Leff in Eq. (F.4) should
clearly be the intrinsic channel length (the length between the n~ regions).
Obviously, if one desires to determine the intrinsic channel length of an LDD
transistor by plotting RM versus LMK for several VGS's. one should only use the low
vgs - VT bias condition. However, any inaccuracy in the determination of VT would
cause significant error in this technique if VGS - VT is chosen to be too small. An
appropriate gate bias (VGS=VGSL). which has enough safety margin above the threshold
voltage and is not too large, should be judiciously chosen. The fact that RSd is a
Append. F -151-
function of gate bias introduces a further complication. In order to minimize this
difficulty, it is proposed to plot RM versus LMK for several substrate biases at a fixed
(small) gate bias [F.ll]. The procedure is illustrated in the next section. The complete
expression for the measured channel resistance is
R -R l ^ U[1 +Uq(V^-Vt)] ^RM-R'+B-lV0S-VTn.]+ 0.(v;-V,) • (F6)
F3. Experimental Results and Discussion
Test structures were designed with a set of poly-Si gate N-channel MOS transistors
adjacent to one another, with LMK= 0.5. 0.75. 1.5. 2. 3, 5. and 10 /xm and W= 10 fim.
The test transistors were fabricated on a P-type silicon wafer with resistivity of 1-2 Or
cm. The LDD n~ region is formed by implanting 5xl012 cm-2 phosphorus at 80 Kev.
followed by n+ implant masked by 0.3 fim oxide spacer.
In performing drain current or channel resistance measurements. Vds is chosen as
small as 50 mV or 100 mV to minimize the drain bias effect on the device characteris
tics. The nominal threshold voltage for LMK= 3 fim is found to be 0.59 V by linear
extrapolation. From the criteria outlined in Section II VGSL is chosen as 2.0 V. although
the final results were insensitive to the choice of VGSL within the range of 1 to 2 V above
VT. Figure F.3 shows the plots of RM versus LMk for Vbs= 0. -1, -2. and -3 V. The
quantity AL = 0.57 fim is obtained. Electrical measurements show that the n~ regions
from the source side and the drain side touch each other for LMK= 0.5 fim. However,
for LMK= 0.75 fim, they do not touch. This agrees with the 0.57 fim value for AL. The
purpose of varying VBS is to vary VT in Eq. (F.6). Clearly, this allows for the determi
nation of Leff and RSD just as varying VGS does (see Fig. F.l). It can be shown, however,
that varying VBS has smaller effect on VTn_ than on VT. Herein lies the advantage of the
Append. F
20
I 8
I 6
I 4
RM(kil) | 0
VM= lOOmV
Vgs»2.0V20nm GATE OXIDE
t 2
LMk (^m>
-152-
8 10
Fig. F.3 Measured channel resistance versus mask-level channel length for an LDDtransistor with 20 nm gate oxide. Lines with different substrate biasesintersect at one point from which AL is derived to be 0.57 fim.
Append. F -153-
substrate-bias-varying method.
The RSD value for each VGS bias is evaluated from Fig. F.l at AL= 0.57 fim and
plotted against Vqj in Fig. F.4. The least-squares method isemployed to find the values
for the parameters RF. B. and VTn_ in Eq. (F.5). In this example. RF= 173 O. B-
8.26xl0-» V"1^1 . and VTn_ =- 0.38 V are obtained.
Figure F.5 shows the measured and calculated drain current versus Vqj for Lmk= 2.
3. 5. and 10 fim. The solid lines are the results calculated from Eq. (F.6). The good
agreement between the measured and calculated results verifies the accuracy of the
model. The parameter values for G and U0 are obtained by fitting the calculated results
with the measured data for LMK= 3 fim . which gives G« 7.52x1 QT4 fim-AW2 and U0 =
0.045 V"1.
Constant source-drain series resistance has been used to model LDD devices [F.12].
Calculated results obtained from Eq. (F.l). using aconstant RSD . are shown in Fig. F.5
with dashed lines for LmK = 1.5 fim and 2 fim devices. The parameters used are AL =0
and RSD = 153 CI, which is the mean value of the intercepts between the straight lines
and the vertical axis in Fig. F.l. A different RSD value would only enlarge the error on
the low VGS or the high VGS range. A large discrepancy between the measured and cal
culated (dashed lines) results reveals the limitation of the constant resistance model in
accurate prediction of LDD device characteristics. The fact that the source-drain series
resistance is gate-bias dependent, even for conventional phosphorus junction MOS
transistors, has been proven with 2-D device simulations [F.13].
Recently, several papers have been published related to this topic [F.14]-[F.17j.
Contrary to the understanding of Duvvury et al. [F.14]. our substrate-bias-varying
method does not depend on the assumption that depletion and enhancement devices
have the same "substrate sensitivity" (sensitivity of VT to VBS) [F.15]. Wordeman et al.
0.8
r•
••
Measu
red
Calc
ula
ted
0.6
Rsd
(kft
)
0.4
0.2 6.0
JL
GS
I,•
1I
II
6 (vo
lt)
81
01
2
Fig.
F.4
Sour
ce-d
rain
seri
esre
sist
ance
vers
usga
tebi
as.
The
para
met
erva
lues
for
the
mod
elar
eRF
=17
3ft
.B=
8.26
xl0~
4V
-1^1
.and
VT=
-0.
38V
.
> 1 a
.u
Append. F
70
• • • Measured
Calculated
60 — with constant Rso
50
40 -
I^A)
30
20
10
VGS (volt)
-155-
Fig. F.5 Comparison of measured and calculated drain current versus gate bias forVDS= 50 mV. and Vbs= 0 V. The parameter values for the intrinsic activeregion are G= 7.52X10"4 fim-A-V'2 and U0= 0.045 V"1.
Append. F _156_
[F.16] pointed out that, based on the study of asimplified MOS structure by using the
two-dimensional device simulator FIELDAY. the substrate-bias-varying method might
not yield the actual channel length. To circumvent the difficulty associated with the
"substrate sensitivity" problem, the traditional gate-bias-varying method can be
modified to electrically determine the effective channel length for LDD MOS transistors.
In the plots of RM versus LMK for various gate biases, the local AL and Ra, correspond
ing to aspecific gate bias can be determined from the intersection of two straight lines
with the gate voltages adjacent to that specific gate bias.
F.4. Conclusion
The introduction of n~ regions makes an LDD MOS transistor behave differently
from aconventional MOS transistor. The source-drain series resistance of the n+ and n"
regions shows astrong dependence on the gate bias. Also, the apparent effective channel
length can vary with gate bias. These special features make the traditional method to
determine effective channel length and series resistance inapplicable. In this work, a
simple and accurate model for the source-drain series resistance of lightly-doped-drain
MOS transistors is presented. The model treats the n~ region as adepletion-mode MOSdevice.
Append. F -157-
References
[F.l] K. Saito. T. Morase. S. Sato. U. Harada. "A New Short Channel MOSFET with
lightly Doped Drain." Denshi Tsushin Rengo Taikai (in Japanese), p.1220. Apr.1978.
[F.2] S. Ogura. P. J. Tsang. W. W. Walker. D. L. Critchlow. and J. F. Shepard.
"Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated
Gate Field-Effect Transistor." IEEE Jour, ofSolid-State Circuits, vol. SC-15. no.
4. pp. 424-432. Aug. 1980.
[F.3] S. Rathnam. H. Bahramian. D. Laurent. Y.-P. Han. "An Optimized 0.5 Micron
LDD Transistor." IEEE Internationa Electron Devices Meeting, pp. 237-241.
1983.
[F.4] Y. Matsumoto. T. Higuchi. S. Sawada. S. Shinozaki. and 0. Ozawa. "Optimized
and Reliable LDD Structure for lum NMOSFET Based on Substrate Current
Analysis." IEEE International Electron Devices Meeting, pp. 392-395. 1983.
[F.5] F.-C. Hsu. H. R. Grinolds. "Structure-Enhanced MOSFET Degradation Due to
Hot-Electron Injection." IEEE Elec. Dev. Lett., vol. EDL-5. no. 3. pp. 71-74.
Mar. 1984.
[F.6] F.-C. Hsu. K.-Y. Chiu. "Evaluation of LDD MOSFET's Based on Hot-Electron-
Induced Degradation." IEEE Elec. Dev. Lett., vol. EDL-5. no. 5. pp. 162-165.
May 1984.
[F.7] J. Frey. N. Goldsman. "Tradeoffs and Electron Temperature Calculations in
Lightly Doped Drain Structures." IEEE Elec. Dev. Lett., vol. EDL-6. no. 1. pp.
28-30.Jan. 1985.
[F.8] P. I. Suciu. R. L. Johnston. "Experimental Derivation of the Source and Drain
Resistance of MOS Transistors." IEEE Trans, on Electron Devices, vol. ED-27.
Append. F _158_
no. 9. pp. 1846-1848. Sept. 1980.
[F.9] J. G. J. Chern. P. Chang. R. F. Motta. and N. Godinho. "A New Method to
Determine MOSFET Channel Length." IEEE Elec. Dev. Lett., vol. EDL-1. no. 9.
pp. 170-173. Sept. 1980.
[F.10] G. Baccarani. G. A. Sai-Halasz. "Spreading Resistance in Submicron MOSFETs"
IEEE Elec. Dev. Lett., vol. EDL-4. no. 2. pp. 27-29. Feb. 1983.
[F.ll] B. J. Sheu. C. Hu. P. K. Ko. F.-C. Hsu. "Source-and-Drain Series Resistance of
LDD MOSFETs: IEEE Elec. Dev. Letters, vol. EDL-5. no. 9. pp. 365-367. Sept.1984.
[F.12] C. Duvvury, D. Baglee. M. Duane. A. Myslop. M. Smayling. M. Maekawa. "An
Analytical Method for Determining Intrinsic Drain/Source Resistance of Lightly
Doped Drain (LDD) Devices." Solid State Electronics, vol. 27. no. 1. pp. 89-96.
1984.
[F.l3] P. Antognetti. C. Lombardi. D. Antoniadis. "Use of Process and 2-D MOS Simu
lation in the Study of Doping Profile Influence on S/D Resistance in Short Chan
nel MOSFETs." IEEE International Electron Devices Meeting, pp. 574-577,
1981.
[F.14] C. Duvvury. D. A. G. Baglee. M. P. Duane. "Comments on 'Source-and-Drain
Series Resistance of LDD MOSFETV" IEEE Elec. Dev. Letters, vol. EDL-5. no.
12. pp. 533-534. Dec. 1984.
[F.15] B. J. Sheu. C. Hu. P. K. Ko. F.-C. Hsu. "Reply to "Comments on 'Source-and-
Drain Series Resistance of LDD MOSFETs." IEEE Elec. Dev. Letters, vol. EDL-
5. no. 12. p. 535. Dec. 1984.
[F.16] S. E. Laux. "Accuracy of an Effective Channel Length/External Resistance
Extraction Algorithm for MOSFET's." IEEE Trans, on Electron Devices, vol.
Append. F -159-
ED-31. no. 9. pp. 1245-1251, Sept. 1984.
[F.17] M. R. Wordeman, J. Y.-C. Sun, S. E. Laux. "Geometry Effects in MOSFET Chan
nel Length Extraction Algorithms," IEEE ELec. Dev. Lett., vol. EDL-6. no. 4.
186-188. Apr. 1985.
Append. G _160_
APPENDIX G
CHANNEL LENGTHS AND WIDTHS OF CONVENTIONALAND UGHTLY-DOPED-DRAIN MOS TRANSISTORS
LIST OF SYMBOLS
C0 gate capacitance per unit area.
Xox gate-oxide thickness.
AL channel-length reduction.
AW channel width reduction (or expansion).
gos channel conductance.
Ids drain current.
Le(r effective channel length.
LMK mask-level channel length.
fis carrier mobility.
Rm measured channel resistance.
Rsd source-drain series resistance.
VT transistor threshold voltage.
Weff effective channel width.
WMK mask-level channel width.
G.l. Introduction
Recent advances in VLSI technologies have successfully demonstrated submicron
MOS transistors with the desired characteristics. Since the small-geometry MOS transis
tor characteristics are highly sensitive to device dimensions, accurate determination of
the channel length, width and gate-oxide thickness is significantly important for the
purposes of device analysis and process control in MOS VLSI technologies.
Append. G _161.
The lightly-doped-drain (LDD) structure can reduce the maximum channel electric
field and thus ease the hot-carrier problem. The source-drain series resistance of an
LDD transistor increases due to the existence of the n" regions. The electric fields
emerging from the gate electrode modulate the n~-region carrier concentration and make
the source-drain series resistance strongly gate-bias dependent [G.l]. The traditional
channel-resistance method does not work well for the determination of effective channel
lengths and widths of LDD MOS transistors.
The goal of the work is to develop simple and accurate methods to electrically
determine channel lengths, widths, and in-situ gate-oxide thicknesses of small-geometry
conventional and LDD MOS transistors. In this report, the traditional channel-resistance
technique to determine the effective channel length and the source-drain series resistance
is reviewed first. An improved channel-resistance method is proposed to determine the
effective channel width. Then, the capacitance method to determine channel lengths,
widths, and in-situ gate-oxide thicknesses is described. The capacitance method applies
to both conventional and LDD MOS transistors.
G.2. The Traditional Method to Determine Channel Lengths —An Overview
Several techniques, based on.dc drain-current measurements, have been developed
to extract the effective channel length and source-drain series resistance of conventional
MOS transistors [G.2]-[G.5]. Among them, the channel-resistance technique originally
proposed by Terada et al. [2] and re-formulated by Chern et al. [G.3] has been widely
established as a defacto standard, primarily because the effective channel length and
series resistance can besimultaneously obtained in a simple way. This method is based
on the linear relationship between the measured channel resistance and effective channel
length of an MOS transistor biased in the linear region.
G.2.1. Measurement Method
Append. G _162.
For an MOS transistor biased in the linear region, the measured channel resistance,
Rm —Vds/Ids. can be expressed as [G.3],
Rm = Rsd + A (LMK - AL) (G.l)
where
A = [fis C0 Weff (VGS - VT - 0.5 Vds)]"1 . (G.2)
To avoid narrow-channel effects [G.6], wide test transistors are used. In Eq. (G.2). both
the mobility (fis) and the threshold voltage (VT) are implicit functions of the effective
channel length [G.6]. At a small drain bias, dependence of these parameters on the
effective channel length is minimized. In addition, application of a large gate bias (e.g.
VGS ^6 V) [G.3] further minimizes the effect of short-channel threshold-voltage falloff
on the parameter A. If smaller gate biases are used (VGS ^5 V in VLSI applications),
then corrections to the threshold-voltage falloff have to be included to achieve high
accuracy.
In plotting RM versus LMK for a set of adjacent transistors with the same channel
width, a straight line is fitted through the data corresponding to a specific gate bias. If
several lines with different gate biases are plotted, they intersect at one point, where AL
and RSD can be found simultaneously.
G.2.2. Experimental Results and Discussion
The test devices used in the experiments were N-channel MOS transistors fabri
cated by the Bell Labs SiGMOS process [G.7]. The substrate doping is 1015 cm"3 and the
enhancement threshold implant is 8xlOn cm-2. Measurement results on test transistors
with LMK = 1.5. 2. 2.5. 3. 4. and 5 fim and Weff =51 fim are presented here.
Figure G.l shows the plots of measured channel resistance versus mask-level chan
nel length for VGS - VT = 2. 4. 6. 8. and 10 V. The least-squares method is applied
twice. First, it is used to fit astraight line through the data for one specific gate bias.
Append. G
0 1 2 3 4 5
CHANNEL LENGTHON MASK LMk W
-163-
Fig. G.l Measured channel resistance versus mask-level channel length for severalgate biases.
Append. G -164-
Second. it is used to find the intersection of the straight lines [G.2], which gives AL =
0.62 fim and RSD =17.8 O.
The dc measurement results are sensitive to the parasitic resistance of the probes,
especially for thin-oxide or short-channel devices for which the contact resistance is not
negligible when compared to the channel resistance. The probes used in the measure
ments are carefully sharpened and cleaned so that probe to metal-pad contact resistance
is always smaller than 2 ft. An overall correlation coefficient better than 0.9999 can be
achieved with this method.
G.3. An Improved Channel-Conductance Method to Determine Channel Widths
The expression for the measured channel resistance of an MOS transistor biased in
the linearregion can be rearranged to have the Wcff term appear in the numerator.
_?_. =WrrMsC0-[VGS-VT-0,5VDS]Rm-Rsd eff L^ * (G3)
Straightforward application of the channel resistance method to determine transistor
channel widths does not work well, as was noted by Ma et al [G.S], because the source-
drain series resistance varies with the channel width. No linear relationship exists
between the measured quantity and the mask-level channel width. This is in sharp con
trast to the fact that source-drain series resistance is constant among the set of adjacent
transistors with the same width and different channel lengths, which were used in
channel-length determination. Kotecha et al. [G.9] have already pointed out that the
effective electrical channel width varies with both gate and substrate biases. However,
their measurement method was not reported. Neglecting the source-drain series resis
tance. Ma et al. [G.8] determined Weff by plotting gDS (or IDS) versus WMK for different
gate voltages at a small drain bias. That method can not be directly extended to short-
channel and thin-oxide devices where the source-drain series resistance is comparable to
Append. G -165_
the intrinsic channel resistance. For example, the typical RSD/Rch ratio is about
20fV200fl for a conventional MOS transistor with Xox = 20 nm, W^ = 50 fim. Leff - 4
fim and biased at VGS - 5 V.
The goal of this work is to develop a simple and accurate channel-conductance
method to determine the effective channel widths of MOS transistors [G.IO]. A
minimum of four test transistors are needed: two different channel widths with two
different channel lengths for each width. One measurement at a large gate bias for each
transistor is sufficient to obtain full characterization.
G.3.1. Measurement Method
The expression for the measured channel resistance of an MOS transistor biased in
the linear region can be rewritten as
Rm =RsD +M»q.w„-Lv<B-vr-o.3Vw] (G-4>
The procedures of the first part of this improved channel-width method are similar to
those of the traditional channel-length method [G.3]. In plotting RM versus LMK for a
set of transistors with the same channel width, a straight line is fitted through the data
corresponding to a specific gate bias by the linear regression technique. In this plot,
notice that the values of the intrinsic channel-conductance coefficient
(Gj =/*sC0Weff(VGS—VT—0.5VDS)). are given by the inverse of the slopes of the straight
lines, and are linearly dependent on the effective width at a given gate bias. The above
procedures are repeated for sets of transistors with different channel widths. All G{s
obtained at the same gate bias for various channel widths are plotted against WMK. and
a straight line is fitted through them by the linear regression again. The x-axis intercept
in this plot gives the channel width offset. AW . Similarly, by plotting Gj's for other
gate biases, the gate-bias dependency of AW can be obtained.
Append. G _l66_
To minimize the influence of the threshold-voltage variations caused by short-
channel effects, large gate biases are used. If short-channel transistors are used in the
experiments, corrections to the threshold-voltage falloff have to be included to achieve
high accuracy.
G3.2. Experimental Results and Discussion
Figure G.2 shows the plots of intrinsic channel conductivity versus mask-level
channel width for VGS - VT = 4. 6. 8. and 10 V from N-channel MOS transistors fabri
cated using a recessed LOCOS process. The measured AW is positive, as expected. Vds=
50 mV is used in our experiments. The correlation coefficient is better than 0.9999. The
insert in Fig. G.2 shows AW as a function of VGS-VT.
A qualitative illustration of the dependence of channel width on the gate bias is
shown in Fig. G.3. The edges of the gate structure are on top of the tapered oxide
regions. Therefore, the effective channel width is gate-bias and substrate-bias depen
dent. For transistors fabricated by a LOCOS process, lateral diffusion of the channel-
stop implant magnifies the dependence. The effective channel width is larger at a large
gate bias and a small substrate bias, because a larger portion of the edge region is
inverted. The effective channel width increases as the gate bias increases, and saturates
when all the edge regions are inverted.
G.3.3. Summary
A simple and accurate channel-conductance method to determine effective channel
widths of MOS transistors has been described. Accuracy in channel-width determina
tion better than 0.1 fim and correlation coefficient better than 0.9999 were obtained.
This method circumvents the difficulty of different source-drain series resistances associ
ated with different channel widths and can be applied to minimum feature-size MOS
transistors fabricated by various technologies.
-V
T=
-vT
=
8V
6V
-V
T=
4V
-11
35
79
11
Cha
nnel
wid
thon
mas
kW
MK
(/z
m)
Fig.
G.2
Intr
insi
cch
anne
lco
nduc
tivi
tyve
rsus
mas
k-le
vel
chan
nel
wid
th.
Line
arde
pend
ence
of
AW
onV
GS—
Vt
can
befo
und
inth
ein
sert
.
> 3 O 0\
•>4
^£—
*-^
sy
sss
Su
bst
rate
Fie
ldO
xid
e
Fie
ldIm
pla
nt
A1
Fig.
G.3
Wid
thcr
oss-
sect
ion
ofan
MO
Str
ansi
stor
from
are
cess
edLO
CO
Spr
oces
s.N
otic
eth
atth
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O On
00 I
Append. G -169-
G.4. The Capacitance Method to Determine Channel Lengths and in-situ Gate-Oxide
Thicknesses for Conventional and Lightly-Doped-Drain MOS Transistors
Adescription of the capacitance measurements for small-geometry MOS transistors
can be found in Appendix H. The plot of raw measured gate capacitance versus gate bias
for a conventional MOS transistor with Weff = 51 fim and LMK - 5 fim is shown in Fig.
G.4. The transistor threshold voltage is0.32 V. When the gate bias increases from -5 V
to 5 V. the transistor goes through three distinct regions of operation: accumulation,
depletion, and strong inversion. In the accumulation region, the measured gate capaci
tance does not contain any component from the intrinsic gate area. The measured capa
citance remains unchanged in this operation region. When the transistor enters the
depletion region, the fringing fields between the gate and sidewalls of the source and
drain junctions cause the measured gate capacitance to increase slightly [G.ll]. As the
gate bias reaches the threshold voltage, the transistor enters the strong inversion region.
Once the inversion layer is formed in the intrinsic gate area, the measured gate capaci
tance will increase asymptotically to a maximum value. In the experiments. -5 V and 5
V are chosen as the two gate biases for which the transistor is in the strong accumula
tion and the strong-inversion regions, respectively. The intrinsic gate capacitance is
obtained by subtracting the parasitic capacitance, determined by biasing the transistor in
strong accumulation, from the measured capacitance with the transistor biased in strong
inversion.
For LDD devices, the channel length is found to depend on the gate bias [G.l]. To
find the intrinsic channel length corresponding to the spacing between the n~ regions. 0
V in place of -5 V is used such that the n" regions are not depleted and thechannel sur
face is not inverted because the threshold voltage of the LDD devices used in these
experiments is 0.58 V.
G.4.1. Measurement Method
30
0 -5^4
-3A
ccu
mu
lati
on
-2
-13 gs
V„
.(V
)
Fig.
G.4
(b)
Mea
sure
dga
teca
paci
tanc
eve
rsus
gate
bias
for
ade
vice
wit
hW
eff=
51fi
man
dLm
k=
5fi
m.
The
gate
bias
isra
mpe
dfr
om-5
Vto
5V
.T
rans
isto
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resh
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volt
ag
eis
0.3
2V
.
> •a 1 -4
Append. G -171-
The capacitance method to determine the channel length and gate-oxide thickness is
conceptually simple [G.12]. The intrinsic gate capacitance can be expressed as
€
Cox = -^- Weff Leff {G.5)
In plotting Cox versus LMK for a set of transistors with the same channel width, a
straight line is fitted through the data with the least-squares technique. The x-axis
intercept in this plot gives AL. If the channel width is known, gate-oxide thickness can
be determined from the slope of the straight line.
G.4.2. Experimental Results and Discussion
The conventional transistors used in the experiments have been described in Section
G.2.2. From an ellipsometer measurement, the gate-oxide thickness is found to be 20.5
nm.
The plot of intrinsic gate capacitance versus mask-level channel length for conven
tional MOS transistors is shown in Fig. G.5. The x-axis intercept of the straight line
gives AL= 0.57 fim. The correlation coefficient for the straight line is better than
0.9999. Using Weff = 51 fim and the slope in Fig. G.5. the gate-oxide thickness is deter
mined to be 21.1 nm. To check the results on AL. the channel-resistance method is
applied to the same set of transistors. Probe to metal-pad resistance adds to the
source-drain series resistance, which could be comparable to the intrinsic channel resis
tance for thin-oxide and short-channel devices. In the capacitance method, the intrinsic
capacitive impedance (1/wC) is on the order of 100 MG in the experiments, which is
much larger than the source-drain series resistance. Hence, the capacitance method is
not sensitive to the probe to metal-pad contact resistance.
The threshold voltage of the LDD transistors used in the experiments is 0.58 V.
Measured results on test transistors with LMK = 1.5. 2. 3. 5. and 10 fim and Weff = 8.8
Mm are presented here. The plot of intrinsic gate capacitance versus mask-level channel
Append. G
400
12 3 4
CHANNEL LENGTH ON MASK LMK (Mm)
-172-
Fig. G.5 Intrinsic gate capacitance versus Lmk for conventional MOS transistors.
Append. G -173-
length for LDD MOS transistors is shown in Fig. G.6. The x-axis intercept of the
straight line gives AL =0.34 fim. The correlation coefficient for the straight line is better
than 0.9995. Using Weff « 8.8 fim and the slope obtained from Fig. G.6. the gate-oxide
thickness is determined to be 19.5 nm. Since the threshold voltage is 0.58 V. the
transistor is in the depletion region when it is biased at VGS « 0 V. Gate capacitance
measured at VGS= 0 V contains a capacitive component due to the fringing fields
between the gate and side walls of n~ regions. This causes the intrinsic gate capaciunce
and thus the effective channel length to be smaller than the actual values. For a con
ventional MOS transistor, the channel-side fringing-field capacitance could be as much
as 10 percent of the intrinsic gate capacitance [G.ll]. However, this fringing-field capa
citance will not give rise to an error larger than 0.1 fim in the AL determination of LDD
MOS transistors, which is estimated to be the accuracy limit of the electrical methods.
G.4.3. Summary
A simple method to determine the channel lengths and in-situ gate-oxide thickness
of MOS transistors is described. The method is based on the linear relationship between
the intrinsic gate capacitance and the effective channel length. Measurements from two
gate biases on devices of different channel lengths are sufficient to obtain a full charac
terization. In contrast to the channel-resistance method, the accuracy of the capacitance
method is independent of the source-drain series resistance. It can be used for conven
tional as well as lightly-doped-drain devices. Channel length and gate-oxide thickness
data determined by this method has been presented for conventional and LDD MOS
transistors. For conventional MOS transistors, the new method agrees with the tradi
tional channel-resistance method to better than 0.1 fim .
G.5. The Capacitance Method to Determine Channel Widths and in-situ Gate-Oxide
Thicknesses for Conventional and Lightly-Doped-Drain MOS Transistors
Append. G
150
df 120
8si
6 90<
5jo
60o
8
30-
2 4 6 8
CHANNEL LENGTH ON MASK LmK (fun)
10
-174-
Fig. G.6 Intrinsic gate capacitance versus LMk for LDD MOS transistors. Transistorthreshold voltage is 0.58 V.
Append. G -175-
The capacitance method to determine the channel width and in-situ gate-oxide
thickness from the measured C0X-WMK characteristics is described. Only standard test
transistors are required. The method is illustrated by application to conventional and
LDD MOS transistors. The validity of this method is supported by the close agreement
between results obtained when it is applied to both long-channel devices and short-
channel devices.
G.5.1. Measurement Method
The capacitance method to determine the channel width and gate-oxide thickness is
simple [13]. The intrinsic gate capaciunce can be expressed as
cox = ]p- Weff Leff . (Q£)
In plotting Cox versus WMK for a set of transistors with the same channel length, a
straight line is fitted through the data with the least-squares technique. The x-axis
intercept of the straight line gives AW. If the channel length is known, the gate-oxide
thickness can be determined from the slope of the straight line.
G.5.2. Experimental Results and Discussion
The conventional devices used in our experiments were N-channel MOS transistors.
The substrate doping is 5xl014 cm-3. The transistor threshold voltage is -0.11 V.
Measured results on test transistors with WMK = 5. 8. 10. and 25 fim and Leff = 2.4 and
7.4 fim are presented here. From an ellipsometer measurement, the gate-oxide thickness
is found to be 27.0 nm.
The plot of intrinsic gate capacitance versus mask-level channel width for conven
tional MOS transistors with Leff = 7.4 fim is shown in Fig. G.7. A solid line is fitted
through the data. The x-axis intercept of the straight line gives AW =1.12 ^m. The
Append. G
225
J 180
8
-
Leff " 7.4 /xm ^r
-
^r
Leff ™2.4 /im ^ -J
ii i
135-
I| 90O
O58
45 -
0 5 10 15 20 25
CHANNEL WIDTH ON MASK WMK(/tm)
-176-
Fig. G.7 Intrinsic gate capacitance versus mask-level channel width (WMK) for conventional MOS transistors. AW =1.12 and 1.16 fim are obtained for the
sets of transistors with Leff = 7.4 and 2.4 jum. respectively.
Append. G -177-
correlation coefficient for the straight line is better than 0.9999. By using L^ =7.4 fim
and the slope of the straight line, the gate-oxide thickness is determined to be 27.8 nm.
To check the result on AW. the capacitance method isapplied to aset of transistors with
Leff - 2.4 ^m. The plot of intrinsic gate capacitance versus mask-level channel width
for this set of transistors is also shown in Fig. G.7. A dashed line is fitted through the
data. AW* 1.16 fim is obtained with correlation coefficient better than 0.9999 for the
straight line. The AW values obtained from the two sets of transistors are within 0.05
fim.
The threshold voltage of the LDD transistors is 0.58 V. Measured results on test
transistors with WMK =2. 3. 5. 7. and 10 fim and Leff - 9.7 fim are presented here. The
plot of intrinsic gate capacitance versus mask-level channel width for LDD MOS transis
tors is shown in Fig. G.8. A straight line is fitted through the data. The x-axis intercept
of the straight line gives AW =1.17 fim. The correlation coefficient for the straight line
is better than 0.9999. By using Leff = 9.7 fim and the slope of the straight line, gate-
oxide thickness is determined to be 19.6 nm.
G.5.3. Summary
A simple and accurate method to determine the channel width and gate-oxide
thickness has been described. This method requires only one curve that represents the
relationship between the intrinsic gate capacitance and the effective channel width.
Correlation coefficients better than 0.9999 are obtained when this method is applied to
conventional and LDD MOS transistors.
G.6. Conclusion
The transistor channel lengths and widths are the major parameters under acircuit
designer's control. Accurate characterization of the effective lengths and widths of MOS
Append. G
2
<oo53
150
120 -
2 4 6 8
CHANNEL WIDTH ON MASK WMK (/tm)
10
-178-
Fig. G.8 Intrinsic gate capacitance versus mask-level channel width (WMK) for LDDMOS transistors. AW = 1.17 fim is obtained.
Append. G -179-
transistors is of paramount importance in designing VLSI circuits because the charac
teristics of the submicron minimum-size transistors used in VLSI circuits are highly sen
sitive to the device dimensions. The channel-resistance method has been extended to
accurately measure the channel widths of MOS transistors. The capacitance method has
also been successfully applied to measure the effective channel lengths and widths of
conventional and LDD MOS transistors. The capacitance method is insensitive to
source-drain series resistances in contrast with the widely-used channel-resistance
method.
Append. G _180_
References
[G.l] B. J. Sheu. C. Hu. P. K. Ko. F.-C. Hsu. "Source-and-Drain Series Resistance of
LDD MOSFETs." IEEE Elec. Dev. Lett., vol. EDL-5, no. 9. pp. 365-367. Sept.
1984.
[G.2] K. Terada. H. Muta. "A New Method to Determine Effective MOSFET Channel
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[G.3] J. G. J. Chern. P. Chang. R. F. Motta. and N. Godinho. "A New Method to
Determine MOSFET Channel Length." IEEE Elec. Dev. Lett., vol. EDL-1. no. 9.
pp. 170-173. Sept. 1980.
[G.4] K. L. Peng. S.-Y. Oh, M. A. Afromowitz. J. L. Moll, "Basic Parameter Measure
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[G.5] P. I. Suciu. R. L. Johnston. "Experimental Derivation of the Source and Drain
Resistance of MOS Transistors." IEEE Trans, on Electron Devices, vol. ED-27.
no. 9. pp. 1846-1848. Sept. 1980.
[G.6] P. P. Wang. "Device Characteristics of Short-Channel and Narrow-Width
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[G.7] P. K. Ko et al.. "SiGMOS - ASilicon Gigabit/S NMOS Technology." IEEE International Electron Devices Meeting, pp. 751-753. 1983.
[G.8] Y.-R. Ma. K. L. Wang. "A New Method to Electrically Determine Effective
MOSFET Channel Width." IEEE Trans, on Electron Devices, vol. ED-29. no. 12.
pp. 1825-18217. Dec. 1982.
Append. G -181-
[G.9] H. Kotecha. W. Noble. "Interaction of IGFET Field Design with Narrow Channel
Device Operation." IEEE International Electron Devices Meeting, pp. 724-727.
1980.
[G.IO] M.-C. Jeng. B. J. Sheu, P. K. Ko. "A New Channel-Conductance Method to
Determine Effective Channel Widths of MOS Transistors," to be published.
[G.ll] R. Shrivastava. K. Fitzpatrick. "A Simple Model for the Overlap Capacitance of
a VLSI MOS Device." IEEE Trans, on Electron Devices, vol. ED-29. no. 12. pp.
1870-1875. Dec. 1982.
[G.l2] B. J. Sheu. P. K. Ko. "A Capacitance Method to Determine Channel Lengths for
Conventional and LDD MOSFETs." IEEE Elec. Dev. Letters, vol. EDL-5. no. 11.
pp. 491-493. Nov. 1984.
[G.l3] B. J. Sheu. P. K. Ko. "A Simple Method to Determine Channel Widths for Con
ventional and LDD MOSFETs." IEEE Elec. Dev. Letters, vol. EDL-5. no. 11. pp.
485-486. Nov. 1984.
Append. H _182_
APPENDIX H
MEASUREMENT AND MODELING OFSMALL-GEOMETRY MOS TRANSISTORGATE CAPACITANCES
H.1. Introduction
Precise characterization of intrinsic gate capacitances of small-geometry MOS
transistors is very important in the design of MOS VLSI circuits. Recent progress in
integrated-circuit technologies has advanced device geometries into the submicron range.
The micron and submicron transistors show prominent short-channel effects and
knowledge of the small-geometry effects on device characteristics becomes extremely
important.
The intrinsic capacitances of short-channel MOS transistors have not been widely
investigated, mainly due to the lack of accurate measurement techniques for characteriz
ing extremely small capacitances (on the order of fento Farads). The goal of this
research is to develop a direct-on-wafer technique capable of measuring micron and sub
micron transistor capacitances and to derive a physics-based short-channel transistor
capacitance model useful for process optimization as well as advanced circuit simulation.
The direct-on-wafer measurement method is simple, fast, and gives accurate results.
H.2. Capacitance Measurement Methods —An Overview
Various methods are available to measure capacitance. The traditional bridge
method [H.l] is suitable for two-terminal elements. For the measurement of four-
terminal MOS transistor capacitances, the four-port-nulling method [H.2.H.3] has been
used because a typical LCR meter or impedance analyzer is sufficient. The four-port-
nulling method is typically applied to large (100 fim by 100 fim or larger) transistors
[H.2]. The measurement limit of commercially-available capacitance meters is probablyaround 1 pF [H.4]. To accurately characterize small-geometry MOS transistor
Append. H -183-
capacitances down to the fF range, new measurement techniques are needed. On-chip
circuitry measurement methods, proposed by Iwai et al. [H.5] and Paulos et al. [H.4],
were the results of recent efforts in this area. Such methods can achieve good measure
ment resolution. This section gives a brief review of different capacitance measurement
methods. A new direct-on-wafer capaciunce method that has been developed will be
described in the next section.
H.2.1. The Bridge Method
The Wheatstone bridge method is commonly used in resistance measurement. Bal
ance isachieved by adjusting the resistance in one arm so that no current flows through
the detector. For the measurement of capaciunce and inductance, an ac bridge is
required. Figure H.l shows the schematic diagram of the general ac bridge which is
equivalent to the Wheatstone bridge except that the arms consist of impedance elements
rather than resisunce elements. The dc voltage source is replaced by an ac signal source,
and the detector must be able to detect ac signals. The condition of balance is [H.l]
Zi _ Z37T2-TZ (H1)
H.2.2. The Four-Port-Nulling Method
The operation of the four-port-nulling method for MOS transistor capaciunce
measurements has been described.in detail by Ward [H.2] and Conilogue [H.3]. The test
instrument interfaces to the outside world through four measurement ports: low
current, low potential, high current and high potential. The Hewlett-Packard series of
LCR meters and impedance analyzers are based on the four-port-nulling measurement
scheme [H.2]. Figure 11.2 shows the equivalent circuit for the MOS transistor inter-
electrode capacitance measurement. Both the connections of the high potential port to
the high current port and the low potential port to the low current port should be made
as close to the physical device as possible in order to minimize the effect ofstray
Append. H
,u1
' n
BIAS He HpHP4271B
LCR METERLc Lp
HIOUT
1
j L. -5
i ,1L
00
ISmV/O1MHz W
0)
-185-
Fig. H.2 Equivalent circuit for inter-electrode capaciunce measurement using animpedance analyzer [2].
Append. H _186.
capaciunce on the measurement results. The ac test signal is applied to the transistor
under test via the high current port. The second signal source in the low current port is
adjusted to produce a null condition at the low terminal. The magnitude of the ac test
signal is monitored at the high potential port, while the response information is sensed
at the low potential port.
So far. the capaciunce measurements at the source and drain are restricted to
long-channel devices. Phase information is required to separate the capacitive com
ponent of current from the conductive component. For reasonable accuracy, the capaci
tive component must be an appreciable fraction of theconductive component. This frac
tion is proportional to the test frequency and the square of the channel length. The
maximum test frequency is limited by the op-amp bandwidth, therefore, the minimum
channel length is constrained [H.6].
H.23. The Open-Loop On-Chip Circuitry Method
The open-loop technique using on-chip circuits to measure small parasitic capaci
tances was first reported by Iwai and Kohyama [H.7]. This technique has been extended
to measure gate capacitances of small-geometry MOS transistors [H.5]. [H.8]-[H.ll].
Figure H.3 shows one of the three circuit configurations necessary to determine the
gate-to-drain (Cgd ). gate-to-source (Cgs). and gate-to-bulk (Cgb ) capacitances. The ac
equivalent circuit is shown in Fig. H.4. By subsequently applying the ac test signal to
the drain, source, and substrate terminals, the following three relationships can be
obtained [H.8]:
Cgd = vo1 ( Cgd + Cgs + Cgb + Cref) . (H.2)
Cgs = vo2 ( Cgd + Cgs + Cgb + Cref). (H.3)
Cgb = vo3 ( Cgd + Cgs + Cgb + Cref ). (H.4)
The above equations are solved simultaneously to determine the three gate capacitances.
'JL
\
ein
Cref
I ION CHIP
Fig. H.3 Open-loop capaciunce measurement techniqueof Iwai et al. [6].
>
Pa
00
Append. H _189_
Kn - Cv0l + vo2 + vo3 ) J Kn""
Cv - C"<' 1,-lv. 1" ,A„,u • (H.6)
C*b - C"< * K,. - rf „ . r„ -...SI • (H.7)
Vq2I vJn - Cv0l + vo2 + vo3 ) J
Vq3lVin-C Vol + V02 + Vo3)J
As was noted by Paulos et al. [H.4], the open-loop capaciunce measurement tech
nique has some drawbacks which makes it inferior to the closed-loop technique. The
input capaciunce of the amplifier, which is strongly bias-dependent, affects the reference
capaciunce value. The switch in Fig. H.3 is used to esublish dc bias on the floating gate
and to calibrate the actual ac gain of the output-buffer circuit. Charge injection from
the switch when it turns off perturbs the dc bias of the floating gate. Complicated com
pensation is required to achieve the desired gate bias.
H.2.4. The Closed-Loop Coulombmeter Method
A closed-loop technique using on-chip circuits to measure MOS transistor capaci-
Unces has been reported by Paulos et al. [H.4]. This technique is an extension of the
previously-proposed coulombmeter method [H.6]. The method is shown in Fig. H.5.
Drain, source, bulk biases are applied directly to the transistor terminals, while the gate
bias is applied through the noninverting node of the amplifier. A switch is required to
periodically establish the dc bias condition for the gate terminal. Similar to the open-
loop technique, it suffers from the problem of charge-injection from the switch [H.4].
The closed-loop approach has the following advantages over the open-loop approach.
First, any of the three gate capacitances . Cgd. Cgs. and Cgb. can be independently meas
ured by applying the ac test signal to the corresponding terminal. Second, the measured
result is insensitive to parasitic capacitance on the virtual-ground node. Feedback have
been added to ensure that all of the response current is forced through the feedback
Append. H -191-
capacitor. Third, the same coulombmeter circuit can be physically shared by several test
devices as long as one device is measured at a time.
IL3. The New Direct-on-Wafer Capacitance Measurement Method
Although the capaciunce measurement methods feported by Paulos et al. [4] and
Iwai et al. [5] have good resolution, the requirement that special on-chip circuits to be
fabricated near the devices of interest has prevented them from being widely adopted.
The op-amp circuit consumes large area as compared to the test transistor itself. Dedi
cated masks are needed for the fabrication of these test structures. The performance of
the op-amp circuit highly depends on the specific process being used. In addition, the
inherently complicated data reduction scheme for the open-loop technique jeopardizes
the accuracy of that method [H.8].
In this research, the instruments and technique to measure fF-size gate capacitances
of small-geometry MOS transistors have been developed. No on-chip circuitry is needed
and direct-on-wafer measurement using standard test transistors is possible [H.12]. By
using a commercially-available high-performance op-amp in the external I-V converter,
the measurement resolution has been improved from better than 0.2 fF [H.12] to better
than 0.02 fF. High accuracy (better than 0.2fF) has also been achieved. In addition, the
technique permits flexibility with regard to choices of dc biases and test devices. The
direct-on-wafer measuring scheme can be easily incorporated into an automatic charac
terization system. This simple and accurate capacitance measurement technique is suit
able for device analysis as well as process monitoring.
H.3.1. Measurement System
Aschematic diagram of the measurement set-up is shown in Fig. H.6. The system
contains an H-P 4145A parameter analyzer under the control of an H-P 9836 desktop
HP4145A
Lock-in
Amplifier
Bias Voltages
out
ref
n
_S£
SwitchingMatrix
7F
ac Signal
CurrentBuffer
l-V Converter
ProbeStation
Fig. H.6 Schematic diagram of measurement setup for gate capacitances.
>
na
NO
i
Append. H -193-
computer. The H-P 4145A supplies programmed dc biases to the test device. The ac test
signal is derived from the built-in oscillator of the lock-in amplifier. The coupling
transformer and the buffer amplifier convert the primary test signal into a truly-
floating, low-impedance source. In order to improve the measurement resolution, the
magnitude of the ac test signal used in the experiments has been increased from 23 mV
(rms) [H.12] to 50 mV (rms). Configurations for measuring various gate capaciUnces
can be selected with a specially designed switching matrix. The frequency of the test
signal was set at 1 KHz for optimal operation of the l-V converter and for minimizing
the phase shift due to cable capaciUnces. The l-V converter connected to the gate con
verts the gate capacitive current into volUge. which is detected by the lock-in amplifier.
The employment of the high-performance op-amp in the l-V converter allows the test
frequency to be increased to 6 KHz which is a major factor in improving the measure
ment resolution. The H-P 4145A monitors the output of the lock-in amplifier, which
gives the capacitance information.
Figure H.7 shows the three measurement configurations to determine the gate-to-
source Cgs. gate-to-drain Cgd. and gate-to-substrate Cgb capacitances, respectively.
Capacitance Cgs is a measure of the change in the gate charge in response to the change in
the gate-to-source voltage only. Therefore, the ac test signal is applied to the source ter
minal, with the gate-to-drain and gate-to-substrate voltages kept constant. Similarly,
the ac test signal is applied to the drain and substrate terminals for the Cgd and Cgb
capacitance measurements, respectively. This new technique contains all the advantages
that the closed-loop technique has. Any of the three gate capacitances Cgs. Cgd . and Cgb
can be measured independently. Full bias-range characterization can be easily achieved
by varying the dc bias voltages Vgs. Vds. and Vbs. This method does not have the
switch-induced charge injection problem which is characteristic of the on-chip-circuitry
methods, since the input of the l-V converter is connected to the gate terminal of the
Append. H
(•)
®
CO
l-Vconverter .
l-V |j converter .
'98
[""test"1device
Hfc&ilf^9
r ,:3L* converter
! ran
Cgd
*" ^aU* Itestdevice
I
tt<KIOT-l'gs
'*fas "Hi.
rbs'da
-194-
Fig. H.7 Measurement configurations to determine (a) gate-to-source capacitanceCgs. and (b) gate-to-drain capaciunce Cgd . and (c) gate-to-substrate capacitance Cgb.
Append. H -195-
test device and it remains at virtual-grounded throughout the measurements. Measured
results are insensitive to parasitic capaciUnces on the virtual-ground node.
R3.2. Measurement Method
The measurement system is calibrated using standard capacitors with 5-digit accu
racy. External and parasitic capaciUnces have to be subtracted from the raw measured
results in order to obuin the intrinsic capaciUnces. Figure H.8 shows the external capa
ciUnces and the parasitic capacitances encountered in the Cgs and Cgd measurements.
CapaciUnces Cgse and Cgde are the inter-probe external capacitances between the gate
probe and source and drain probes. Cps and C^ include the overlap capaciUnces. outer
fringing-field capaciUnces. and metallization capaciUnces associated with the pads at the
source and the drain. The capacitances Cgse+Cps and Cgde+Cpd are equal to the measured
gate-to-source and gate-to-drain capacitances respectively when the device is in the
strong accumulation region. Such measured capacitances do not contain any contribu
tion from the intrinsic gate area. It is essential to keep the external capacitances Cgse and
Cgde small in order to retain high accuracy.
Schematic diagrams of three different types of probes are shown in Fig. H.9. The
darkened area denotes the conductor in direct contact with the probing pin. For the
ordinary probe to ordinary probe" arrangement, the inter-probe capacitance is as large
as a few picofarads so that accurate measurement of the small-geometry MOS transistor
capacitances becomes impossible. If the probe is teflon-shielded, the inter-probe capaci
tance is reduced to the sub-pF range. However, it is still too large to achieve high accu
racy. By using the coaxial probes, the inter-probe parasitic capaciunce is further
reduced down to 4-5 fF for both "coaxial probe to teflon-shielded probe" and "coaxial
probe to coaxial probe" arrangements. The coaxial probe arrangements are used in the
experiments.
H.3.3. Experimental Results
Append. H -196-
Fig. H.8 Probe arrangement indicating the external-and-parasitic capaciunce components.
External Inter-probe Capacitance
52
Ordinary Probe Teflon-shielded Probe Coaxial Probe
Arrangement Inter-probe Capacitance
Ordinary Probeto
Ordinary Probea few pF
Teflon-shielded Probeto
Teflon-shielded Probe0.4 pF
Coaxial Probeto
Teflon-shielded Probe4~5 fF
Coaxial Probeto
Coaxial Probe4^5 fF
Fig. H.9 Schematic diagrams of an ordinary probe, teflon-shielded probe, and coaxial probe.
>
"8oa
VO
i
Append. H -198-
The resolution of this method is illustrated in the following example. The raw
measured results for a test transistor with W^/L^ = 4.2 fim/1.0 fim are shown in Fig.
H.10. High resolution better than 0.1 fF is achieved in this measurement. The devices
used in the experiments were N-channel MOS transistors. The gate-oxide thickness is
20.0 nm. substrate doping is 1015 cm-3 . and enhancement threshold implant is 81011
cm"2. Figure H.ll shows the normalized plot of the gate-to-source (Cgs) and gate-to-
drain (Cgd) capaciUnces of a short-channel transistor with ^^Us = 99.2 fim/1.0 fim.
Included in this figure for comparison purposes are the measured capaciUnces of a long-
channel transistor with Vta/Us = 99.2 fim/99.5 fim. In this plot, the external capaci
unce and the parasitic capaciunce have been subtracted. The curves corresponding to
Vgs-Vx= 1 V start at a value slightly smaller than 0.5 Cox because gate capaciunce
hasn't reached the maximum value at the low gate bias. The fact that the Cgd curves
bend up and the Cgs curves bend down at large drain biases is believed to be due to the
hot-carrier effect.
H.4. Short-Channel Effects
At zero drain-source bias. Cgd and C^ are the same for both long-channel and
short-channel devices, as expected. This means that the drain and source have equal
amount of control over the channel charge.
For a long-channel device. Cgd approaches to zero and Cgs approaches to 2/3 Cox as
the device goes into the saturation region. A sharp transitions between the triode and
saturation regions can be found. This behavior is well known and modeled [H.13]. The
reason for Cgd approaching to zero is that in the saturation region the mobile carriers
adjacent to the drain are depleted and the drain has very little control over the channel
charge.
Append. H
12->
fF
5~>
t0 vds(v)
-199-
Fig. H.10 Raw measured gate-to-source and gate-to-drain capacitances for a transis
tor with Weff = 4.2 fim and Leff = 1.0 fim. The two sets of curves
correspond to Vgs - Vlh = 2 V and 4 V, respectively. The parasitic capacitance has not been subtracted yet.
Append. H
1.0
-
Vga-^r» ^^ ^
-
- \i\^C|;
• i • i
c
Cox.8-
.6-
.4-
2 ~ 3vd»cv)
0>)
-200-
'98
Cgd
Fig. H.ll Normalized plots of measured Cgs and Cgd results for (a) a long-channeltransistor with W= 100 fim and Leff = 100 fim. (b) a short-channeltransistor with W =50 fim and Leff = 1.0 fim. Vgs increases in 1 V steps.
Append. H -201-
For a short-channel device, several unusual features are observed. First, the Cgd
and C^ curves are much smoother than the long-channel device curves. No sharp tran
sition from the triode region to the saturation region can be identified. This can be
understood in terms of the phenomenon of carrier velocity saturation in short-channel
devices. Second, the C^ curves split in the saturation region for different gate biases.
Both velocity saturation and source-drain series resistance contribute to this splitting.
Because of the velocity saturation effect, a larger amount of the channel charge exists
under gate control than predicted by the long-channel transistor theory. The increase in
the gate-controlled channel charge is more prominent at a larger gate bias as the
velocity-saturation effect is more dominant [H.14]. The source-drain series resisUnce.
on the other hand, tends to reduce the splitting since the IR drop, which reduces the
effective gate voltage, is larger at a higher gate bias. Third. Cgd saturates to a finite value
in the saturation region. This behavior, as first described in [H.12], is due to the
channel-side fringing fields between the gate and drain (source) junctions. The magni
tude of this fringing capacitance is a strong function of the drain bias. At zero drain-
source voltage when no channel electric field exists, the drain and source junctions are
shielded from the gate on the channel side by the inversion layer. However, in the
saturation region, the drain fringing-field lines can penetrate through the conducting
channel to reach the gate in the region near the drain where the channel electric field is
high. It is important to point out that the limiting saturated value for Cgd at large drain
biases is a function of the drain-junction depth, gate-oxide thickness [H.14.H.15], and
does not scale with device size. It. therefore, is more prominent in short-channel dev
ices. In the experiments, the limiting saturated values for Cgd are approximately 4%. 8%.
and 14% of Cox for devices with Leff= 4.5. 1.5. and 0.75 fim. respectively. Because of
the Miller effect, the influence of channel-side fringing capacitance on the performance of
high-speed MOS circuits is readily noticeable experimentally.
Append. H _202-
H.5. A Physics-Based Capacitance Model for Short-Channel MOS Transistors
An analytical model to explain the measured results, especially the short-channel
effects and above-threshold characteristics, is described. This new model includes the
mobility-degradation effect, velocity-saturation effect, bias-dependent fringing-field
effect, as well as source-drain series resisUnce effect. The analytical capaciunce model is
based on the hot-electron current model previously developed by Ko [H.17]. Descrip
tions of the dc model can be found in [H.14] and [H.16].
H.5.1. The Charge and Capacitance Model
The gate charge. QG. is made up of three components. QC1 . QG2 . and QG3 . as
shown in Fig. H.12. The drawing is a schematic represenution of the charge density
along the channel. It is not the spatial distribution of the charge. The gradual-channel
approximation can be applied to the portion of the channel near the source. The charge
in this portion is designated as QG1. In the portion of the channel adjacent to the drain,
the velocity of mobile carriers saturates. The charge in this portion is designated as
Qc2 • When the device is biased in the saturation region, there isan important capacitive
component between the gate and the drain, i.e.. the channel-side bias-dependent
fringing-field capacitance. The charge associated with the fringing-field effect is desig
nated as QG3 . The gate-charge derivativesgive the intrinsic gate capacitances.
C - dQc i r - aQc i a r - 3Qg , /„ ^8S~ evgl v« -v* ' Cgd" ev '̂v* -v* •and c*b" w^ v- v<*' (H-8)
The expression for QG1 can be obtained by integrating the distributed charge den
sity over the area of the active gate region.
Qgi= / Qn(y) dy =WC0/ (V8S-VT-V(y))dy=WC0/ V*~ V^~V(y) dV ,(H.9)0 0 » t
where the integration with respect to the positional increment dy has been converted to
Gate
'G1 QG2 QG3
Source n+ Drain
Substrate
Fig. H.12 Schematic illustration of the three components of the charge stored in thegate when the device is biased in the saturation region. QGi: the charge inthe source region. Q^: the charge in the saturation region. QG3: the chargeassociated with the channel-side bias-dependent fringing fields.
>•a
1a
itoo
I
Append. H -204-
an integration with respect to the potential increment dV. Since
T _ ^ (Vgs-VT-V)E f ^
1+ g- +VEoxp
by rearranging (H.10) we obtain
l- l rv»-v'-v-ii fH11)E n+TE^T[—5— Xh (HU)
Substituting (H.11) into (H.9) and carrying out the integration.
v
WCQoi= (1+»E °>EI /1 (VP- Vt"V) E. - I„p ](Vp-VT- V) dV
=(i^SEcidp{ T[°V- Vt)3"(V*~ Vt" V-)3 ]
- ^ [(Vs»- Vt>2 - CVf.- VT- Vds)2 ]} . (H.12)
By including the source-drain series resistance effect, the expression becomes
Qgi= (l+7)E0X)EcId {T [(V* ~Vr~ IdRs)3 " (V* ~Vt " Vds+ IdRs)3 ]
- }*L (Vgs-VT-IdRs)2 -(Vgs-VT-Vds+IdRs)2 ]} .(H.13)
The Ec term comes from the velocity-saturation effect. The 7) Eoxp term comes from the
vertical-field mobility-degradation effect. The Id Rs term comes from the source-drain
series resistance effect.
When the device is biased in the saturation region. Vds in the QGi expression is
replaced by Vdsat. It is important to obtain the length of the drain region inside which
the carrier velocity saturates. A pseudo two-dimensional analysis is used to find the
channel electric field and potential distribution by solving the Poisson equation for the
Append. H -205-
Gaussian box enclosing the drain region. Once the electric field and potential drop inside
this drain region is available, the length of this drain region can be obuined easily.
Because all the carriers travel at the same saturated velocity in the drain region, the
mobile carrier density is constant in this region. The multiplication of the charge den
sity with the length gives QG2 .
_ Idsat ALQg2= -^ (H.14)
vsat
where vat is the saturation velocity. Accurate determination of the saturation volUge is
crucial in the calculations of QG1 and QG2 .
The bias-dependent fringing-field capaciunce associated with QG3 can be deter
mined by considering the device operation in the drain area. When the device is biased
in the strong inversion region and Vds= 0. the fringing field is shielded by channel
inversion charge. In this case, the drain terminal has a strong control over the channel,
and
r _ d(QGi+QG2) . C0 ffX8dc" —e\g— v" -v*=T' (IU5)
The limiting condition corresponding to non-shielding of the channel-side fringing field
is when Cgdc = 0. In this case, the drain has no control over the channel. An approxi
mate expression for the unshielded fringing-field capacitance is given by [H.15],
cr =i!|^i„[, +̂ Lsin(^i)]. (H.16)w Kx 2eSi
Here. Xj is the drain-junction depth. However, for Vds > 0. the control by the drain
over the channel degrades. Linear interpolation is used to give a first-order model of the
bias-dependent fringing-field effect.
2 CCgdfrmgmg =Q ( 1- *?! ) . (H.17)
Append. H _206-
The two limiting conditions, when Cgdc= C0/2 and when Cgde= 0, are satisfied by
(H.17).
H.5.2. Results and Discussion
Figure H.l3 shows the calculated C-V characteristics for a long-channel transistor
and a short-channel transistor with the same device parameters as those for the transis
tors used in Fig. H.ll. Good agreement between the calculated results and the meas
ured dau in Fig. H.ll is found.
When compared to the already published charge and capacitance models for long-
channel devices, the salient features of this short-channel transistor model are:
(1) The vertical field and horizontal field mobility degradation effect is incorporated in
the expression for QG1 .
(2) The drain region charge. QG2 . which takes into account the velocity saturation
effect via v^ and the channel-length modulation effect via AL . is included.
(3) The bias-dependent-fringing-field effect is incorporated. QG3 is constant irrespec
tive of the channel length, and the ratio of this capacitive component to the max
imum intrinsic gate capacitance increases as channel length decreases.
(4) Source-drain series resistance is included.
The inclusion of the above features is important for a short-channel charge and
capacitance model. Features (1) and (2) make the calculated characteristics smooth.
Feature (3) accounts for the finite value of Cgd in the saturation region which has a
strong influence on the high-speed performance of MOS circuits.
For the case with source-drain series resistance. Cgd is larger and Cgs is smaller as
compared with those in the case without source-drain series resistance under the same
bias conditions. At a finite drain bias, the voltage drop across the channel is reduced due
Append. H -207-
(a)
O)
Fig. H.l3 Normalized plots of calculated Cgs and Cgd results for transistors with thesame device parameters as those for the transistors used in Fig. H.ll.
(a) a long-channel transistor, (b) a short-channel transistor.
Append. H -208-
to the volUge drop in the source-drain series resistance. The hot-electron effects which
modify the C-V characteristics of short-channel transistors at large drain biases (see Fig.
H.ll(b)) have not been included in the model yet.
H.6. Conclusion
A new and simple technique for measuring the gate capacitances ofsmall-geometry
transistors has been described. This direct-on-wafer measurement scheme is very suit
able for the purposes of device physics study and process control applications and can be
easily incorporated into an automated characterization system. It applies to sUndard
test transistors without requiring any on-chip circuitry. Very high accuracy and resolu
tion have been achieved by using this measurement technique. An analytical model
which satisfactorily explains the various unusual features observed in the intrinsic gate
capacitance characteristics of short-channel MOS transistors has also been presented.
The inclusion of the mobility degradation effect, velocity saturation effect, bias-
dependent fringing-field effect, and source-drain series resistance effect proves to be ade
quate for accurate prediction of the intrinsic capaciUnces.
Append. H -209"
References
[1] H. H. Chiang. Electrical and Electronic Instrumentation, John Wiley & Sons.
1984.
[2] D. E. Ward, "Charge-Based Modeling of Capaciunce in MOS Transistors."
Technical Report G20I-II, Stanford Electronics Laboratories. Stanford Univer
sity. June 1981.
[3] R. L. Conilogue, "A Large and Small Signal Charge Storage Model for an
Enhancement Mode M.O.S. Field Effect Transistor," Ph.D. Dissertation, Univer
sity of California, Los Angeles. 1983.
[4] J. J. Paulos. D. A. Antoniadis. "Measurement of Minimum-Geometry MOS
Transistor Capacitances." IEEE Trans, on Electron Devices, vol. ED-32, no. 2, pp.
357-363. Feb. 1985.
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