built in self test - computer systems & reliable soc lab

Built In Self Test

Sungho Kang

Yonsei University

2Computer Systems Lab. YONSEI UNIVERSITY

Outline

? Introduction? Pattern Generation? Response Analysis? BIST Architectures? Conclusion

IntroductionBuilt In Self Test

? Capability of a product to carry out an explicit test of itself? Test patterns are generated on-chip?Responses to the test patterns

are also evaluated on chip? External operations are required

only to initialized the built-in tests and to check the test results(go/no-go)

Pattern Generation(random pattern)

CircuitunderTest

OutputResponse

Monitor

Output

Test/Normal

IntroductionBuilt In Self Test

? Advantage?No need for expensive tester?At-speed testing? Thorough test

? Disadvantages? Initial Design Investment?Area overhead? Pin overhead?Not effective for random testing resistive circuits?Aliasing problem

Pattern GenerationTest Pattern Generation

? Stored Pattern? Exhaustive Pattern? Pseudo Exhaustive Pattern? Pseudo Random Pattern? Weighted Random Pattern

Pattern GenerationStored Pattern

? Store deterministic test patterns in a ROM? Can achieve high fault coverage? Requires large memory space? Requires external ATPG and fault simulation? Not practical or cost effective for large circuits

Pattern GenerationExhaustive Pattern

? For n input combinational circuit, 2n exhaustive patterns are required

? For large n, it is not practical? Detects all irredundant, combinational faults? Uses binary counters or LFSRs

Pattern GenerationExhaustive and Pseudo Exhaustive

? Possible required ? Fault free simulation?Way to make segmentation

? Not required ? Fault simulation?Circuit modification

? Very high fault coverage? Pattern generation?Use counters or LFSRs

Pattern GenerationPseudo Exhaustive Pattern

? Used when exhaustive test is too long? Divide circuits into subcircuits? Individual output verification (Cone verification)? Exhaustive test of each output?No output depends on all inputs

? Segment verification?Network partitioned? Exhaustive test of each segment

Pattern GenerationCombinational Circuit Classification

? Partial Dependence Circuit (PDC)?No output depends on all inputs? Exhaustive test if possible? Else output verification test? Else segment verification

? Full Dependence Circuit (FDC)? Some output depends on all inputs? Exhaustive test if possible? Else segment verification

Pattern GenerationCone Verification

? The p output circuit is logically divided into p cones? Each cone is tested exhaustively? All cones are tested concurrently? (n,w) CUT? n inputs and output Yi = fi(Xi), w = maxi { |Xi| }

? Example : (4,2) CUT? If w=n, pseudo exhaustive testing is exhaustive testing

y1 y4y3y2

x4x3x2x1

Pattern GenerationCone Verification

? LS630 (16bit error detection and correction)? 24 inputs, 6 outputs? Each output depends on 10 inputs? 210 patterns for each output? 6 X 210 patterns for all

Pattern GenerationPDC Classification

? MTC ?Maximal Test Concurrency Circuit ? The number of test signals required?The maximum number of inputs connected to any output

?MTC Example ?4 test vectors required ?A = C?Minimal number of required test signals is equal to the

maximum number of inputs upon which any output depends

? NMTC ?Non-Maximal Test Concurrency Circuit ? The number of test signals required?More than the maximum number of inputs connected to any

output?NMTC Example?Every output is a function of only 2 inputs?Each output can still be

tested exhaustively by4 patterns

? NMTC Example? Every output is a function of only 2 inputs? Each output can be tested exhaustively by 5 patterns

Pattern GenerationNMTC? Identification of minimal set of test signals? Partition the circuit into disjoint subcircuits? For each disjoint subcircuit?Generate a dependency matrix?Partition the matrix into groups of inputs so that 2 or more

inputs in a group do not affect the same output?Collapse each group to form an equivalent input, called a test

signal input?Characterize the collapsed matrix in terms of p and w where p is

the number of partitions (width) and w is the maximum number of 1s in any row (weight)

?Construct the test pattern for the circuit ?p=w : MTC and test set consists of all 2p patterns?p=w+1 : test set consists of all possible patterns of p with

either odd or even parity?p>w+1 : test set consists of 2 or more pattern subsets, each of

which contains all possible patterns of p bits having a specificconstant weight

NMTC Example

? Example circuit

? Dependency matrix?Dij = 1 if output I depends on input j ; otherwise Dij=0

gfedcb

f1(a,b,e)

f2(b,c,g)f3(a,d,e)

f4(c,d,e)

f5(e,f)

c ga b fed

NMTC Example

? Reordering and grouping the inputs produce the following modified matrix

c ga b fed

NMTC Example

? In each group there must be less than two 1s in each row and the number of groups should be minimal

? This insures that no output is driven by more than one input from each group? Finding such a partition is NP-complete

? ORing each row within a group to form a single column

NMTC Example

? p=4 and w=3 ? odd parity

?A B C D? 0 0 0 1? 0 0 1 0? 0 1 0 0? 1 0 0 0? 0 1 1 1? 1 0 1 1? 1 1 0 1? 1 1 1 0

? Pseudo exhaustive test set consists of 8 patterns instead of 128?Among 4 groups, 8 patterns using any 3 inputs are necessary

? Total number of test patterns is a function of p and w? Constant weights do not exist for all pairs of p and w? For such cases, w can be increased so as to achieve a constant-

weight pseudo exhaustive test, but it may not be minimal in length? It is always easy to construct a circuit to generate a

pseudo exhaustive test set for p>w+1 and hardware overhead of some of these circuits is quite high

Pattern GenerationSegment Verification

? Segmentation testing via path sensitization

? Sensitized path is established from C to F?Use 2n1+2n2 patterns instead of 2n1+n2 patterns

Pattern GenerationFDC

? LS181 (ALU)? 14 inputs, 8 outputs? Some outputs depends on all inputs? 214 patterns

? Use segmentation?Only 356 patterns are required

Pattern GenerationSegment

? Example? Exhaustive test vectors : 64?Output cone test vectors : 32

Pattern GenerationSegment Example

? Example

? Exhaustive test of G sensitized to F2 by Z = 1?U V W X Y Z G H F1 F2 ? 0 0 0 1 1 1? 0 0 1 1 1 1? 0 1 0 1 1 1? 0 1 1 1 0 0? 1 0 0 1 1 1 ? 1 0 1 1 1 1? 1 1 0 1 1 1? 1 1 1 1 1 1

? Added to exhaustive test of G ?U V W X Y Z G H F1 F2 ? 0 0 0 1 1 1? 0 0 1 1 1 1? 0 1 0 1 1 1? 0 1 1 1 0 0? 1 0 0 1 1 1 ? 1 0 1 1 1 1? 1 1 0 1 1 1? 1 1 1 1 1 1? 1 1 1 0 1 0? 0 0 1 0 1 0

? Added to exhaustive test of H ?U V W X Y Z G H F1 F2 ? 0 0 0 1 1 1? 0 0 1 1 1 1? 0 1 0 1 1 1? 0 1 1 1 0 0? 0 0 1 0 0 1 1 0 0 1 ? 0 1 1 0 1 1 1 1 1 1? 1 0 1 1 0 1 1 1 1 1? 1 1 1 1 1 1 1 1 1 1? 1 1 1 0 1 0? 0 0 1 0 1 0

? Added to exhaustive test of F1 ?U V W X Y Z G H F1 F2 ? 0 0 0 1 1 1? 0 0 1 1 1 1? 0 1 0 1 1 1? 0 0 0 1 1 1 0 0 0 0? 0 0 1 0 0 1 1 0 0 1 ? 0 1 1 0 1 1 1 1 1 1? 1 0 1 1 0 1 1 1 1 1? 1 1 1 1 1 1 1 1 1 1? 1 1 1 0 1 0? 1 1 0 0 1 0 1 1 0 0

? Segmentation by multiplexors? Path sensitization : 10? Multiplexors : 13

? 74181 ALU? 214 exhaustive patterns ?Output cone test : 214 patterns

? 74181 ALU? Li function : 16 patterns

? 74181 ALU?Hi function : 16 patterns

? 74181 ALU? 74181 ALU : N2 ?Hi = (Ai X Bi)’? Li = Ai’?Design constraints : HiLi = 01 is impossible? 34 AB tests X 22 M Cn tests : 324? Segment Test : 324 + 16 + 16 = 356

Pattern GenerationPseudo Exhaustive Pattern

? 8 input parity tree

? Instead of 256 pattern, only 4 patterns are required?Minimum pseudo exhaustive pattern? a b c d e f g h i j k l m n ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 1 1 1 0 1 1 1 1 0 1 0 1 1 ? 1 0 1 0 1 1 0 1 1 1 0 1 0 1 ? 1 1 0 1 1 0 1 0 0 1 1 1 1 0

Pattern GenerationConstant Weight Pseudo Exhaustive

? Any (n, w) circuit can be tested by a constant weight counter implementing a w-out-of-k code for an appropriate value of k? n : number of inputs?w : weights?maximum of inputs for any cone

? 2-out-of-4 code? 1100? 1010? 1001? 0110? 0101? 0011

Pattern GenerationPseudo Random Pattern

? Test Pattern Source?ALFSR (Autonomous Linear Feedback Shift Register) LFSR?All patterns equally likely? Sometimes misnamed random

Pattern GenerationRandom vs Pseudorandom

? Random? Patterns can occur more than once?Non-reproducible

? Pseudorandom?All (possibly except all-0 pattern) patterns occur before any

pattern repeats?Reproducible

Pattern GenerationLinear Feedback Shift Register

? The state of shift register depends only on the prior state

D Q D QD QD Q

c2c1c1 cn

Q1 Q2 Q3 Qn

a-1 a-2 a-n+1 a-n

amam-1 am-2 am-n+1 am-n

Next State

Current State

D Q D QD QD Q

c2c1c1

cncn-1

Q1 Q2 Q3 Qn

am-1 am-2 am-nCurrent State

? Polynomial? shorthand notation for a bit stream

? x6+x2+x+1? 1000111? 1X6+0X5+0X4+0X3+1X2+1X+1

? Arithmetic of polynomial is modulo 2?Addition and subtraction is the same? (x-1) is the same as (x+1)

? Degree of a polynomial is the highest power of the non-zero term

? Generating function G(x)?G(x) = a0+a1x+a2x2+… +amxm+... = ? amxm where ai is 0 or 1

? For type 1 LFSR?

??????

???? ??

1iimim

)xa...xa(xc)x(G

)xa...xa(xc)x(Gxc

)]x(Gxa...xa[xc

]xaxa...xa[xc

xaxcxac)x(G

xa)x(G

? Characteristic polynomial P(x)? P(x) = 1+c1x+c2x2+… +cnxn

? If a-1=a-2=… =a1-n=0 and a-n=1 then

1p1p10

p2p1p1p10

1p1p10

x1ntoidividesevenly)x(PthatseenisitThusx1

xa...xaa

)...xx1)(xa...xaa(

...)xa...xaa(x

)xa...xaa(x

)xa...xaa()x(P/1

pperiodwithcyclicis}a{sequencetheSince

xa)x(P

???????

? Maximum length sequence? Period of 2n-1 for n stage LFSR?Disregard all 0's

? Primitive polynomial?Characteristic polynomial with a maximum length sequence

? Non Primitive Polynomial? Less than maximal length

? Irreducible polynomial?Not divisible by any other polynomial other than 1 and itself?Has an odd number of terms including the 1 term? If its degree n is greater than 3, the P(x) must divide into 1+xk

where k = 2n-1? Example?x4+x3+1 divides evenly into X15+1

? Number of Primitive Polynomials? n PPs n PPs? 1 1 17 7710 ? 2 1 18 7776 ? 3 1 19 27594 ? 4 2 20 24000 ? 5 6 21 84672 ? 6 6 22 120032 ? 7 18 23 356960 ? 8 16 24 276480 ? 9 48 25 1296000 ? 10 60 26 1719900 ? 11 176 27 4202496 ? 12 144 28 4741632 ? 13 630 29 18407808 ? 14 756 30 17820000 ? 15 1800 31 69273666 ? 16 2048 32 67108864

? Primitive Polynomial ? n Primitive Polynomial ? 1, 2, 3, 4, 6, 7, 15, 22 1+x+xn

? 5, 11, 21, 29 1+x2+xn

? 10, 17, 20, 25, 28, 31 1+x3+xn

? 9 1+x4+xn

? 23 1+x5+xn

? 18 1+x7+xn

? 8 1+x2+x3+x4+xn

? 12 1+x+x4+x6+xn

? 13 1+x+x3+x4+xn

? 14, 16 1+x3+ x4+x5+xn

? 19, 27 1+x+x2+x5+xn

? 24 1+x+x2+x7+xn

? 26 1+x+x2+x6+xn

? 30 1+x+x2+x23+xn

? 32 1+x+x2+x22+xn

? Pseudo Random Pattern Generation?Characteristic Polynomial : 1+x2+x3

? Initial condition (1,0,0) : x?Q1 : x / (1+x2+x3)?Q2 : x2 / (1+x2+x3)?Q3 : x3 / (1+x2+x3)

? When initial state is 100?Q1 Q2 Q3? 1 0 0? 0 1 0? 1 0 1? 1 1 0? 1 1 1? 0 1 1? 0 0 1? 1 0 0? 0 1 0? 1 0 1

? When initial state is 000?Q1 Q2 Q3? 0 0 0? 0 0 0

Pattern Generation

LFSR SR

x1 xi xi+1 xn

Combined LFSR and SR

? Less cost than constant weight counter

D Qx1 x2 x3 x4

1 1 1 0

0 1 1 1

0 1 0 1

1 0 1 1

1 1 0 0

1 0 0 1

0 0 1 0

1 1 1 0

D D DQ Q Q

Pattern GenerationCombined LFSR and XOR

? Close to LFSR/SR ?Q1 Q2 Q3 Q4 ? 1 0 0 1 ? 0 1 0 0 ? 1 1 1 1 ? 0 1 1 0 ? 1 0 1 0 ? 0 1 0 1 ? 0 0 1 1 ? 1 0 0 1

D Q 1 0 0

x1 x2 x3 x4

1 0 0 1

1 1 0 0

0 1 1 0

1 1 1 1

0 0 1 10 1 0 11 0 1 1

1 0 0 1

D Q D Q

Pattern GenerationCondensed LFSR

? Efficient when w >= n/2 ? When w < n/2, use combined LFSR and SR

Pattern GenerationCyclic LFSR

? When w < n/2? Condensed LFSR ? Produce long test length for (n,w) circuits

? Combined LFSR and XOR ?Have a high hardware overhead

? Use cyclic code? Low hardware overhead and reduce test length

Pattern GenerationLFSR for Exhaustive Test

? Include NORs

Pattern GenerationWeighed Random Patterns

? All patterns not equally likely? Pseudo random test patterns are inefficient when random-

pattern-resistant faults exist.? Make Prob[1] ? Prob[0] at pattern sources? Random resistant faults?Consider a 32 input AND and output s-a-1 fault? The output s-a-1 is detected when all inputs are 1?When pseudo random testing is used, the detection probability is

WeightComputation

Circuit

CircuitunderTest

? Let pf be the detection probability of fault f ? (1- pf)N : probability that f is not detected by N

independent patterns ? C = 1-(1- pf)N : Confidence of detecting f by a random test

set of N patterns. ? N = ln(1-C)/ln(1- pf) : # of patterns to reach Confidence C. ? The test length required for detecting a set of faults F only

depends on the fault f with the lowest detectability.? Example> 32-input AND gate? Pseudo random testing?4.48 X 1010 patterns required to reach C = 0.999

?WPRG ?When the probability of 0 is 1/232

?pf = 0.5, N=600

Multiple Weight Sets

? Consider a circuit with a 32 input AND and a 32 input OR where the same 32 inputs feed them

? Consider AND output s-a-1 and OR output s-a-0

? If the same weights are applied, one of two faults are hard to detect.

? It is necessary to have 2 different weight sets

? (1/232, 1-1/ 232) (1-1/ 232, 1/ 232)

? The efficiency of multiple weight set is determined by both the number of weight sets (r), and the total number of random test patterns to be applied (N).

? The goal of weight generation is to reduce both r and N

? Single weight set?Advantage?Small hardware overhead

?Disadvantages?Low fault coverage?Long test pattern length

? Multiple weight sets?Advantages?High fault coverage?Short test pattern length

?Disadvantages?Large hardware overhead

Weight Generation Methods

? Structural analysis? Small number of patterns and weight sets? Easy implementation? Poor fault coverage

? Deterministic test sets?All non-redundant faults can be detected?A high number of random patterns and weights? Large hardware overhead

? Combined both methods

T1 P1 T2 P2 T3 P3A 1 0 1 0 1/2 1 0 1 1 3/4 1 0 1 X 2/3B 1 1 0 0 1/2 1 1 0 0 1/2 1 1 0 0 1/2C 1 0 0 1 1/2 0 0 0 1 1/4 X 0 0 1 1/3

A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-0Pf(P1) 1/4 1/4 3/8 3/8 1/4 1/4Pf(P2) 3/8 1/8 1/2 1/2 1/8 3/8Pf(P3) 1/3 1/6 7/18 7/18 1/ 1/3

Maximizing Don’t Cares

? If “Don’t Cares” occur in a test set they must not contribute to the weights

?by maximizing the number of “Don’t Care” bits , ATPG can remove redundancies in the test set

Maximizing Don’t Cares

? Decisions are guided by a number of heuristics which particularly aim at generating test patterns with a large number of unspecified bits, and keeping the overall test set small

? For error propagation, a node on the D-frontier is selected which is as close as possible to the POs and is located on a path with a maximum number of undetected faults,

? For line justification, observability are used if there is a choice of a gate input line to be set to a controlling value? if the gate output is observable?a gate input line is selected such that the number of

undetected faults preceding this line is maximum? if not observable?a gate input line is selected such that the number of primary

inputs to be set becomes minimal

ATPG and Weight Generation

?? A)A) ATPG is performed for all the undetected faults. ATPG tries to maximize the number of “Don’t Cares”

?? B)B) Weight generation?? C)C) WRPG and fault simulation.

Pattern generation is stopped if the last k successive patterns do not detect any new fault. ( k = a user-defined parameter)

?? BB’’)) Weight computation by using Hamming distance? Resolving conflicts?Only the patterns from

D(t,T,m) are used for weight generation

? reversing weight generation

Pseudo-random pattern generation, faultsimulation and redundancy removal

faults left = ?

ATPG forremaining faults

Weight calculation

WRPG and faultsimulation

Comments

? Pseudo Random Test Pattern could be proved to be inefficient when Random-pattern-resistant faults exist.

? Weight set generation methods can be based on the structural analysis or deterministic test sets.

? If possible, the small number of weight sets, the small number of total test patterns, and High fault coverage should be achieved at the same time.

? To combine advantages of both methods, Weight generation and ATPG could be integrated.?Maximize the number of “Don’t Cares” in deterministic sets.?Resolving conflict information problem by partitioning

deterministic test patterns? in actually testing ,WRP is generated by circuits

consisting of LFSR and combinational logic.? Rounding of weights

Response AnalysisResponse Analysis

? Duplication? Ones Count? Transition Count? Parity Check? Syndrome? Signature Analysis

Response AnalysisDuplication

? Comparison of outputs of 2 implementations? Can avoid alias problem? Can avoid loss of effective fault coverage of a signature

analyzer? Hardware overhead

Response AnalysisCompression

? Signature : output of the compactor? Decision factors? Extra hardware? Loss of fault coverage?Calculation of good signature?Aliasing?A faulty circuit produces a signature that is identical to the

signature of a fault free circuit

CircuitUnderTest

DataCompression

ComparatorErrorIndicator

Correct Signature S(R0)

InputTest

Sequence T

OutputResponse

Sequence R'Signature

Response AnalysisOnes Count

? Count the number of ones at the output? After applying n vectors, the signature is between 0 and n? Masking probability? Prob(masking) = ( nCp - 1 ) / (2n - 1)

Clock Counter

Signature(ones count)

R0=10000000

IC(R0) = 1IC(R1) = 2IC(R2) = 0

R2=00000000

R1=11000000

Response AnalysisTransition Count ? Signature ? The number of 0-to-1 and 1-to-0 transitions at the output

? After applying n vectors, signature is between 0 and n-1? Masking probability? Prob(masking) = 2 X (n-1)Cp / (2n-1) ? p : the number of transitions in a fault free response

Clock Counter

Signature(transistion count)

R0=10000000

IC(R0) = 1IC(R1) = 1(undetectable fault)IC(R2) = 0

R2=00000000R1=11000000

Response AnalysisParity Check

? Signature : parity? Compression circuit consists of a XOR and a D FF? LFSR with G(x) = x + 1

? Masking probability? Prob(masking) = ( 2(n-1) - 1 ) / (2n - 1)

Clock Signature(parity)

R0=10000000

P(R0) = 1

R2=00000000R1=11000000

P(R2) = 0P(R1) = 0

Response AnalysisSyndrome

? All 2n patterns are applied to the input? The number of 1's at an output is counted? Compare the number of 1's for good machine and for

faulty machine? Syndrome S = k/2n

? k : the number of minterms? n : the number of inputs?Normalized number of ones at the output

? Not all Boolean functions are totally Syndrome testable? Used for exhaustive testing

Response AnalysisSyndrome

? No reconvergent fanout ?C3 Syndrome of S3 ?AND S1S2 ?NAND 1 - S1S2 ?OR S1 + S2 - S1S2 ?NOR 1 - ( S1 + S2 - S1S2) ? XOR S1 + S2 - 2S1S2

? Reconvergent fanout?C3 Syndrome of S3 ?AND S1 + S2 + S((FG)’) - 1 ?OR S1 + S2 - S(FG)? XOR S( F’G) + S(FG’)

Response AnalysisSignature Analysis

? Compaction of Test Data in a LFSR? How to compare the results??Applying test sequence and compare signature

? Signature? value left in LFSR

? To obtain signature and initialization pattern, use a golden board

? Aliasing? Fault free signature is the same as fault signature? Probability : 1/2n

SR Q(x)G(x)

initial State : I(x) = 0 final State : R(x)

= Q(x) +G(x)P(x)

R(x)P(x)

or G(X) = Q(x)P(x) + R(x)

? Initial Value : 000?Good Good Faulty Faulty ? Patterns Responses Patterns Responses? Z1 Z2 Z3 Q1 Q2 Q3 Z1 Z2 Z3 Q1 Q2 Q3? 1 1 0 1 1 0 1 1 0 1 1 0? 0 1 0 1 0 1 0 1 1 0 1 1

Response AnalysisAliasing

? Initial Value : 000?Good Good Faulty Faulty ? Patterns Responses Patterns Responses? Z1 Z2 Z3 Q1 Q2 Q3 Z1 Z2 Z3 Q1 Q2 Q3? 1 1 0 1 1 0 1 0 0 0 1 1? 0 1 0 1 0 1 0 1 1 1 0 1

Response AnalysisAliasing

? For the register length n and the length of test bit stream m, assume that all possible bit streams are evenly distributed over all possible signatures

? The number of bit stream that produce a specific signature is 2m/2n = 2m-n

? For a particular fault-free response, there are 2m-n -1 erroneous bit stream with same signature

? Since there are a total of 2m-1 possible erroneous response streams, the aliasing probability is (2m-n-1)/(2m-1) = 2-n

? Reduce aliasing ? Increase the length of register chain ?Access signature several times

? Parallel ? Faster

? Serial

Response AnalysisMISR

? Normally, a single input signature analyzer is not used due to testing overhead

? Aliasing Probability : 1/2n

?All error patterns are equally likely

D Q D QD QD Q

cn-2cn-1cn

DnD3D2

Response AnalysisUsing ALU

? Low Overhead

+ or -

Register

Response AnalysisAlias Probability

? P (fault not detected) = P(no output error) + P(output error | correct signature)

? P (fault not detected) = P(no output error) + P(output error) P(correct signature | output error)

? P (no output error)? escape probability

? P (correct signature output error )? alias probability (PAL)

Response AnalysisPAL

? Depends on? P : characteristic of fault and circuit? L : test length? f(x) : polynomial describing signature register

? Exact calculation of PAL is NP-complete? Bound for Serial Signature Analysis? PAL <= (1+e)/L if L < Lc? PAL <= 1 if L = h X Lc? PAL <= 2/(L2+1) if L>Lc and L h X Lc? Lc?signature register period?maximum autonomous cycle length

? What we want?Alias probability upper bound, independent of P

? Use signature polynomial with period test length

ArchitecturesBIST Structures

? On-line BIST?Testing occurs during normal operating conditions?Self checking

? Off-line BIST? Embedded?Use system registers to generate and compact test data

? Separate?Use registers external to the system function to generate and

compact test data?Centralized?Several CUTs share TPG and ORA

?Distributed

ArchitecturesBIST Structures

? Decision factors?Degree of test parallelism? Fault coverage? Level of packaging? Test time? Physical constraints ?Complexity of replaceable units? Performance degradation

ArchitecturesSeparate BIST

? Drawbacks? Long test time? Poor delay

? Advantages? Low overhead? Simple control logic

? Danger?Decimation Dependency? Linear Dependency

ArchitecturesDecimation Dependency

? The number of LFSR patterns, M? 2m or 2m-1

? The number of possible different scan path patterns, P ?Minimum of the followings?M?N=2n

?( LCM of M and n )/n = M / (GCD of M and n) ? Example?m=4, M=15, n=5 : P=3?m=10, M=1023, n=9 : P=341

ArchitecturesLinear Dependency

? If n < m?No linear dependency

? If n >= m and kj < m ?No linear dependency

? If n >= m and kj >= m ? Possible linear dependency

ArchitecturesCSBL

? Centralized and separate board level BIST?No boundary scan?Best suited for not many feedbacks? Fault simulation is required to determine the number of test

vectors to achieve an adequate level of fault coverage

CUT(C or S)

MUXPRPG SISR

k = log2m

ArchitecturesLOCST

? LSSD On-Chip Self Test?Centralized and separate BIST? Scan path (LSSD) ?Boundary scan?On-chip test controller

ON-chipmonitor(OCM)

Error-detection circuitry

SISRSRSG

PIs POs

SRLSRL

SinSout

Error signalControl signal

ArchitecturesSTUMPS

? Self Testing Using MISR and Parallel SRSG

?Centralized and separate BIST?Multiple scan paths?Reduction in test time

?No boundary scan? Lower overhead than BILBO

but takes longer to apply

Scan path

So So'

CUT (S)

External logic

ArchitecturesCBIST

? Concurrent BIST?Centralized and separate BIST?No scan or boundary scan?Can be used for sequential logic?On-line testing?PRPG and MISR are initialized

until Enable signal is enabled?Off-line testing?PRPG drives the circuit and

responses are compressedin MISR

ArchitecturesCEBS

? Centralized and Embedded BIST with Boundary Scan? The first r bits of the input boundary scan registers are used for

PRPG and the last s bits are used for MISR or SISR

ArchitecturesRandom Test Data

? Distributed and embedded BIST? Boundary scan? Some binary patterns are repeated? Others may not be generated?R1 and R2 : PRPG?R2 and R3 : MISR

ArchitecturesSimultaneous Self-Test

? Distributed and embedded BIST? Scan path?No LFSR ?No boundary scan

? Problem in testing external logic? Problem in characterizing the quality of test process

ArchitecturesSimultaneous Self-Test

? Use self-test storage cell for each storage cell?Normal mode : Q = D? Test mode (self test) : Q = D ? Si ?Test Mode=1

? Scan mode?Test Mode=0

ArchitecturesCyclic BIST

? Use sequential circuits as nonlinear binary sequence generators? If there are more outputs than inputs, extra outputs can be

combined using XOR ? Low area overhead? Effectiveness is circuit dependent?Asynchronous feedbacks are possible?CUT should be clocked a predetermined times (determined by

fault simulation)

ArchitecturesCircular BIST

? General architecture?Register based? Partial self test?All inputs and outputs must be associated with boundary scan cell?All storage cell must be initializable before testing? LFSR with primitive polynomial 1+xn

? Storage Cell? [A] ?N/T Z Mode ? 0 Dj System ? 1 Dj ? Sj-1 Test

? [B] ?B0 B1 Z Mode ? 0 0 0 Reset ? 0 1 Sj Scan ? 1 0 Dj System ? 1 1 Dj ? Sj-1 Test

? Test process? Initialization? Testing of circuit ?Response evaluation

? Advantages?High fault coverage ? Low hardware overhead?One test per clock

? Disadvantages ? Pattern generation is heavily dependent of the circuit function?Certain pattern may be generated?May be used with partial scan path to apply deterministic patterns

ArchitecturesScan Dependence

? Possible if use output of MISR as test patterns? FF (i+1) is scan dependent iff during normal operation it is

functionally dependent on the previous FF(i) in the scan path

ArchitecturesScan Dependence

? Example?Normal mode : Zi+1 = Qi + f?MISR mode : Zi+1 = Qi’f : incorrect

? Yi+1 is scan dependent if Yi+1 is a function of Yi

? Eliminate scan dependence by reordering scan path? Use scan dependence to reduce BIST overhead?Redesign scan cell for scan dependence bits

ArchitecturesBILBO(Built-In Logic Block Observer)

? Take advantage of the register aspects of many design? Program counter, instruction register, accumulator

? Normal registers are replaced by BILBO register? Inputs to a logic C are driven by a BILBO register? Output of C drives another BILBO register

ArchitecturesBILBO(Built-In Logic Block Observer)?B1 B2 Mode? 1 1 Normal Mode? 0 1 Reset? 0 0 Shift Register? 1 0 Signature Analyzer

QnQn-1Q2Q1

D DD DQQQQ

Z1 Z2 Zn

ArchitecturesBILBO Operations

? Shift Register Mode : B1=B2=0

? Normal Mode : B1=B2=1

? Signature Analysis Mode : B1=1 B2=0? If Z1=Z2= … =Zn=0, PRPG

ArchitecturesBILBO

? To test A?R1 : RPG?R2 : Signature Analyzer

? To test B?R2 : RPG?R1 : Signature Analyzer

Register1

Combi-nationalCircuit

Register2

Combi-nationalCircuit

ArchitecturesBus Oriented BILBO

? In PRPG mode, BILBO register need to be held at constant value by disabling all bus drivers and using pull-up or pull-down circuitry

Register1A

Register1B

RegisternB

RegisternA

ArchitecturesBILBO Pipeline

? Need to deactivate inputs to BILBO registers during PRPG mode C 1

BILBO 1

BILBO 2

BILBO n

ArchitecturesBILBO

? Advantages?At-speed test?Reuse system bistables

? Drawbacks?Multiple Test sessions?Complex control

? Danger?Register self-adjacency

ArchitecturesRegister Self-Adjacency

? A register Ri is said to be a driver of a logic C if some outputs of Ri are inputs to C

? A register Rj is said to be a receiver of C if some outputs if C are inputs to Rj

? Ri is said to be adjacent to Rj if there exists a block of logic C such that Ri is a driver of C and Rj is a receiver of C

? If Ri is both a receiver and a driver of C, it is self-adjacent? Avoid by design or synthesis? Use Concurrent BILBO

ArchitecturesConcurrent BILBO

? Register can be operated as PRPG and MISR simultaneously?B1 B2 Mode ? - 0 Normal ? 1 1 Scan ? 0 1 PRPG/MISR

ArchitecturesTest Schedule

? Test session?An assignment of test modes to BILBO registers to test one or

more blocks? Test scheduling problem?Determine the minimal number of test sessions required to test all

blocks of combinational logic?Determine the minimal colors that can be assigned to the nodes of

a graph such that no edge connects two nodes of the same color? More complex when the test time for each block is

considered

ArchitecturesPartial BILBO Pipeline

? Only a subset of registers are madefor BILBO

? Reduction on hardware complexity

ArchitecturesControl of BILBO

? When multiple test sessions exist, the efficient control becomes important? The first cell of BILBO register and the control lines to all the cells

are driven by the above logic? S* drives the S0 to the first cell in BILBO register? T0 T1 T2 Mode B0 B1 S* ? 1 0 0 PRPG 0 1 FB ? 1 0 1 MISR 1 1 FB ? 0 0 Q SHIFT 0 1 Q ? 1 1 X LATCH 1 0 X ? 0 1 1 RESET 0 0 X

ArchitecturesControl of BILBO

? Control Sequence? Inhibit system clocks and enter the test mode? Initialize control registers with data specific to a test session? Send the LFSRs and scan paths? Initiate the test process? Process the final signature to determine if an error has been

detected

ArchitecturesSTARBIST

? Each cluster contains one parent test vector in the center? A number of children patterns is derived from parent test

vector by complementing certain number of coordinates in pseudo-random pattern

? This method doesn’t use the conventional LFSR directly to generate pseudo-random patterns

? The implementation makes use of scan order and polarity between the neighboring scan cells

WaveformGenerator

Diffractor

scan cells

ArchitecturesPhase Shift BIST

? Partition circuit into NAC and scan chain?NAC(Nearly Acyclic Circuit)?sequential synchronous circuit the period of which is not

larger than 1? Pseudo random patterns by LFSR and PS are applied

through primary inputs and scan chain? PS(Phase Shifter)?required to avoid the structural dependency between outputs

of pattern generator? Compress output values using MISR and SC(Space

Compressor)

ArchitecturesPhase Shift BIST

NearlyAcyclicCircuit

TestPattern

GeneratorCircuit Under Test

OutputData

Compactor

fromO.P.'s

PrimaryOutputs

toC.P.'s

PrimaryInputs

C.P.'s : Control PointsO.P.'s : Observation Points

ArchitecturesMultiple Fixed Biased PR BIST

? Pattern is applied to CUT (Circuit Under Test) through n idler register segment

? Idler register segment is operated by BIST pattern generation and control logic

? Each idler register segmenthas a different biasing valueand some bits are fixed toa specified value

? The output of CUT is passedto MISR and fault identification is performedusing signature that remainsin MISR

BIST PatternGenerationand Control

Idler Reg. 1 Idler Reg. n

ArchitecturesMultiple Frequency Scan BIST

? Several scan chains is synchronized in different frequencies

? Each frequency is generated by system clock and primary inputs

? To synchronize different scan chains, clock number required to load scan chain and perform sampling must be divided by the ratio of any frequency pair

? BIST core is composed of random pattern generator, signature analyzer, pattern counter, scan mode signal generator, and clock generator

? Better performance than STUMPS

ArchitecturesMultiple Frequency Scan BIST

BISTCORE

Chain1

Chainn

CombinationalLogic

Sistem Clock

CK1_SM1

CKn_SMn

ConclusionConclusion

? In BIST, the test pattern generation and the output response evaluation are done on chip? The use of expensive ATE machines to test chips can be avoided.

? Requirements of a BIST scheme ? Easy to implement? Small area overhead ?High fault coverage

? Advantage?No need for expensive tester?At-speed testing

built in self test - computer systems & reliable soc lab

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