ansys signal power-integrity update
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© 2011 ANSYS, Inc. October 24, 20111
Signal‐ and Power‐Integrity Update
Presented by Martin Vogel, PhDApplication Engineer
© 2011 ANSYS, Inc. October 24, 20112
• Translation from layout tools
• HFSS in layout‐based interface
• SIwave enhancements
• SI Circuit Simulation with IBIS‐AMI
• Q3D Extractor enhancements
Overview
© 2011 ANSYS, Inc. October 24, 20113
Translation from layout tools
© 2011 ANSYS, Inc. October 24, 20114
AnsoftLinks Translation Paths
Cadence Mentor ODB++ Zuken
Q3D SIwave HFSS DesignerTPA Icepak Mechanical
AnsoftLinks
HFSS PlanarEM
Solver on Demand
.anf
AnsoftLinks with Extracta
CadenceVirtuoso SiP APD Allegro
Altium
Nexxim HSPICE
© 2011 ANSYS, Inc. October 24, 20115
HFSS for Signal Integrity
HFSS “Solver on Demand” in planar interfaces
© 2011 ANSYS, Inc. October 24, 20116
“HFSS Solver on Demand”Two Design Flows for Electrical Design• Mechanical CAD– Connectors, Waveguides regular HFSS
• Electrical CAD (layout)– PCBs, Packages, On‐chip Passives HFSS ‐ Solver on Demand
© 2011 ANSYS, Inc. October 24, 20117
Designer with HFSS ‐ Solver on Demand
HFSS ‐ Solver on Demand• Intuitive design entry for HFSS• Chips, packages, PCBs, modules, …• Designer layouts simulated with HFSS– Automated boundary and port setups– Finite dielectrics and ground supported
• Wave and Lumped Gap Port– Single ended and Differential– Vertical and Horizontal– Coaxial, CPW and Grounded CPW
© 2011 ANSYS, Inc. October 24, 20118
HFSS Package & PCB Merge
Copy package
Paste into PCB layout
Independent package and board stackups
Board
HFSS ‐ Solver on Demand
© 2011 ANSYS, Inc. October 24, 20119
HFSS Solve for PKG merged to PCB
Lumped ports on package bumps
© 2011 ANSYS, Inc. October 24, 201110
Parameterized Padstacks
Enables parametric investigation and optimization of stackup.
© 2011 ANSYS, Inc. October 24, 201111
Parameterized Differential Vias
© 2011 ANSYS, Inc. October 24, 201112
HFSS Setup & Solve Within Cadence• Create and Solvemodels with HFSS from within Cadence Allegro, APD, SiP, Virtuoso
HFSS Solution Progress
© 2011 ANSYS, Inc. October 24, 201113
SIwave enhancements
© 2011 ANSYS, Inc. October 24, 201114
DDR3 Solutions: Signal Net Analyzer
• Displays Z0, length, time delay, and reference layer• All possible paths (from each pin to every other pin on net) are displayed
– Sorted in descending order of path distance• User can click on an individual path in the table
– Variation in Z0 is graphically displayed– Path is highlighted in SIwave’s main layout window
• Ideal reference layer mode (default)– Traces on top & bottom metal layers are assumed to be microstrips– Interior traces are assumed to be striplines
• Non‐ideal reference layer mode– Reference layer is explicitly calculated for each trace segment– Some traces may be floating (no suitable reference layer available)
© 2011 ANSYS, Inc. October 24, 201115
Automated DCIR Reporting
Click Here
© 2011 ANSYS, Inc. October 24, 201116
SI Circuit Simulation
© 2011 ANSYS, Inc. October 24, 201117
Network Data Explorer
Circuit Simulation• Designer• Simplorer• Other• S‐parameter visualization
• S‐matrix reduction• Passivity checker• State‐space fitting• Passivity enforcement• Macro‐model generation
HFSS
SIwave
Q3D
Network Data Explorer
Designer
• State Space• Simplorer• Spectre• HSPICE• PSPICE
Measured Data
New functionality for the SI market
© 2011 ANSYS, Inc. October 24, 201118
Network Data Explorer
© 2011 ANSYS, Inc. October 24, 201119
Network Data Explorer
Graphic comparison showing the difference between the Z‐Matrix entries for two different decoupling capacitor schemes.
© 2011 ANSYS, Inc. October 24, 201120
Network Data Explorer
• The S‐Parameter data can be reduced by terminating ports.
New s‐parameter set is generated with only these ports. All other ports are terminated.
© 2011 ANSYS, Inc. October 24, 201121
Macro‐Modeling with Network Data Explorer
Touchstone Models from Arbitrary Source can be converted to Multiple Model Types with Causality and Passivity Enforcement!
Advanced features
New!
© 2011 ANSYS, Inc. October 24, 201122
High‐Speed Serial Design with IBIS‐AMI
• Automated IBIS‐AMI Importing– IBIS‐AMI Specification Testing
• Pass/Fail• Advanced
© 2011 ANSYS, Inc. October 24, 201123
AMI Schematic
Algorithmic TxModel
LTI ChannelAlgorithmic RxModel
© 2011 ANSYS, Inc. October 24, 201124
Q3D Extractor 11.0
© 2011 ANSYS, Inc. October 24, 201125
Accuracy Improvements
• Added the ability to converge on off‐diagonal terms
• Example: Touch‐panel displays
© 2011 ANSYS, Inc. October 24, 201126
0.00 0.01 0.10 1.00 10.00 100.00Freq [MHz]
25.00
30.00
35.00
40.00
45.00
50.00
55.00
ACL(
Coi
l:Coi
l_in
,Coi
l:Coi
l_in
) [nH
]
Q3DDesign2XY Plot 1 ANSOFT
Curve InfoACL(Coil:Coil_in,Coil:Coil_in)
Setup1 : Sw eep2
Q3D – Magnetic Materials
Q3D AC 10 s Maxwell 3D 50 minQ3D DC 6min 30 sSweep 2 s
Total < 7 min 50 minPeak RAM 0.6 GB 5 GB
L(f)
Simulation Time
HFSS
Maxwell*
Q3D
* Each additional frequency point takes ~ 15 minutes to solve with Maxwell
Electroplated Nickel has 5
Bulk Nickel has 600
© 2011 ANSYS, Inc. October 24, 201127
3D Modeler Enhancements
View customization.
• Z‐stretch.• 64‐bit user interface
© 2011 ANSYS, Inc. October 24, 201128
CAD Integration in ANSYS Workbench
Provides direct link to third‐party CAD tools• Such as ProEngineer, Catia, SpaceClaim
Parameters in CAD model are available for parametric analysis and for optimization.
or Q3D, or Maxwell
© 2011 ANSYS, Inc. October 24, 201129
• HFSS Solver on Demand in Designer and Cadence
• SIwave signal‐net analyzer
• Circuit Simulation with IBIS‐AMI
Summary of highlights
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