signal integrity software -...
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Signal Integrity Software
ISD, ADK, SI3D
Dr. Ching-Chao Huang [email protected] AtaiTec Corporation
06/13/2013
About us
AtaiTec Corp. was founded in 2010 to provide SI software and consultation.
Dr. Ching-Chao Huang has 25+ years of high-speed design and SI software development experience: IBM – Package design and circuit simulation (ASXwr) TMA – Parasitic extraction (Raphael) Rambus – SI design and characterization Optimal – Power integrity (PowerGrid) SI consultant; IEEE senior member
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Outline
In-Situ De-Embedding (ISD) A cost-saving alternative to replace TRL calibration. Simple – Only one 2x through test coupon is needed. Save $$$ – Save SMAs, board material, and time. Accurate – Remove fixture crosstalk; causal DUT results.
Advanced Signal Integrity Design Kits (ADK) Everything you want to do with S parameters in one
place. Many complex SI operations in one mouse click. Great training tool for new SI engineers.
SI3D – Fast 3D solver for connector and cable Free 2D field solver and S-param viewer
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www.ataitec.com
In-Situ De-embedding (ISD)
A cost-saving alternative to TRL calibration
06/13/2013
Objective
The goal is to remove the effect of test fixture (SMA connector + lead-in trace) and extract the S parameters of DUT (device under test).
DUT
lead-in trace
SMA
test board
to VNA
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What is ISD
De-embedding is made easy as 1-2-3. Measure 2X thru coupon
and DUT board and run ISD.
More accurate than TRL calibration.
Save SMAs, board material and time.
Used by several major companies.
Presented to USB3.x CabCon WG.
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Mezzanine connector example
In the following example, we will use ISD and TRL to extract a mezzanine connector and compare their results.
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To be de-embedded
Mezzanine connector
(DUT)
SMA
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Why ISD is more accurate and saves $$$
TRL calibration board
More board space - Multiple test coupons are required.
Test coupons are used directly for de-embedding.
All difference between calibration and actual DUT boards gets piled up into DUT results.
Expensive SMAs, board materials (Roger) and tight-etching-tolerance are required. Impossible to guarantee all SMAs and traces
are identical (consider weaves, etching, …) Time-consuming manual calibration is
required. Reference plane is in front of DUT.
ISD test coupon
Only one 2x thru test coupon is needed. Test coupon is used only for reference, not
for direct de-embedding. Actual DUT board impedance is de-
embedded. Inexpensive SMAs, board materials (FR4)
and loose-etching-tolerance can be used. ECal can be used for fast SOLT calibration.
Reference plane is in front of SMA. De-embedding is made easy as 1-2-3 with
only two input files: 2x thru and DUT board (SMA-to-SMA) Touchstone files.
More information: Both de-embedding and DUT files are provided as outputs.
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DUT results after ISD and TRL – which one is more accurate?
TRL gives too many ripples in return loss (RL) for such a small DUT.
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TRL gives too many ripples.
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Time-domain response gives insights from a different perspective
Converting S param into TDR/TDT and delaying the response by 1ns reveals causality problems after TRL.
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TRL gives non-causal response.
Rise time = 40ps (20/80)
before signal arrives
Is TRL good enough here?
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Zoom-in shows non-causal TRL results in all IL, RL, NEXT and FEXT
TRL causes time-domain errors of 0.38% (IL), 25.81% (RL), 1.05% (NEXT) and 2.86% (FEXT) in this case*.
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Rise time = 40ps (20/80)
before signal arrives
Non-causal
Non-causal
Non-causal
Non-causal * The percentage is larger with single-bit response and/or faster rise time.
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How did ISD do it?
Through optimization, ISD de-embeds SMA and lead-in trace impedance exactly, independent of 2x thru’s impedance.
Rise time = 40ps (20/80)
2x thru and DUT test board have different impedance.
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TRL can give more than 100% error in SDD11 even with small impedance variation*
ISD also de-embeds SMA and lead-in trace differential impedance exactly with only a single-line 2x thru.
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Rise time = 40ps (20/80)
De-embedding
DUT (after de-embedding)
TRL gives more than 100% error due to causality violation.
* The impedance variation between TRL cal board and DUT test board is less than 5%. (See 2x thru vs. SMA-to-SMA in the previous slide.)
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Another test board was used to show ISD independent of impedance variation
Two scenarios: (a) impedance variation between 2x thru and DUT test board and (b) impedance variation between two DUT test boards using the same 2x thru.
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2x thru SMA-to-SMA DUT test board
Test boards with and without putty were tested. (Putty alters the impedance discontinuity between SMA and trace.)
Putty
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ISD gives the same DUT results even with large (~14%) impedance variation
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Large variation in trace impedance and SMA-to-trace discontinuity
De-embedding
DUT (after de-embedding)
“Raw” data
Putty was applied to reduce impedance discontinuity between SMA and trace
Rise time = 40ps (20/80)
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ISD gives the same IL, RL, NEXT and FEXT, independent of the test boards
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Rise time = 40ps (20/80)
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ISD also gives the same differential DUT results, independent of the test boards
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“Raw” SMA-to-SMA differential data
De-embedding DUT’s differential IL & RL (after de-embedding) Rise time = 40ps (20/80)
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Summary
TRL gives non-causal results in all IL, RL, NEXT and FEXT. All impedance difference between TRL calibration and
actual DUT boards gets piled up into the final DUT results. TRL gives large RL error even with slight impedance
variation between TRL calibration and actual DUT boards.
ISD is more accurate. Same DUT results (on all IL, RL, NEXT and FEXT),
independent of the 2x thru or DUT board impedance.
ISD saves $$$ and time. Less board space, inexpensive board material and loose
etching tolerance. SOLT with auto Ecal and ISD in 1-2-3 clicks.
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Demo: ISD is easy to use
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Step 1 - Input 2X thru Touchstone file
Step 2 - Input SMA-to-SMA Touchstone file
Step 3 – Click “Run”
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Demo: ISD creates three output files
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1. De-embedding file from the left
2. DUT file
3. De-embedding file from the right
We can cascade these three files to reconstruct the original SMA-to-SMA file.
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Demo: Advanced options
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1X length test coupon can also be used.
Run ISD twice and skip left/right ports each time when the left/right lead-ins are very different (e.g., IC packages)
When the DUT board is not a thru structure
Adjust lead-in flight time and attenuation to change the reference plane (useful for de-embedding vias at the end of traces, for example)
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Advanced SI Design Kits (ADK)
SI tasks made easy with one mouse click
06/13/2013
What is ADK
Everything you want to do with S parameters (28 SI Apps) in one place.
Many complex SI operations in one mouse click.
Data mining S parameters is made easy.
Great training tool for new SI engineers. 23
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SI modeling & simulation
There are more than 20 ways to process S parameters.
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ADS
ADK
S Param
S Param
HFSS VNA
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From [S] to [S]
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S parameters (Touchstone file)
S parameters (Touchstone file)
Fill in DC data Correct causality and passivity
Interpolate for more data points Re-order ports
Extract a subset of ports Combine multiple measurement files
Convert to mixed-mode Change reference impedance
Cascade De-embed
Combine [S] with PEC & PMC Change reference port
Scale impedance Remove bad data
ADK
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From [S] to ?
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S parameters (Touchstone file) ADK
TDR & TDT
Impedance & delay
SPICE model
Eye diagram
Comparison with industry standards
Over-laid [S] plot from multiple files :
Optimized TX tap coefficients
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From ? to [S]
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S parameters (Touchstone file)
SPICE model
W-element model
2D Solver
2D geometry
3D geometry
Impedance, crosstalk, etc.
ADK
Fast 3D Solver
ADK
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Convert [S] to TDR & TDT
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Filter DUT S Param
Open, Short, or Terminated Source
How to set up source and filter to give proper edge rate at the input of DUT?
Does simulation correlate with direct TDR & TDT measurements?
Tedious to connect in ADS for multi-port [S]
Filter + IFFT
Simplified to S Param TDR & TDT
Is R R
( )S
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[S] to TDR & TDT in one click
Built-in filter and IFFT. Output step, single-bit and impulse response.
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Passivity & causality correction
(Mild) causality error in time domain can mean huge difference in S param.
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S param
TDR @50 ps (20/80), shifted by 1ns
Causality violation
Before signal arrives
S-to-TDR Conversion TDR & TDT
Passivity & Causality
Correction S param
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Multiple ways to fill in DC data
Separate signal and ground resistance for point-to-point nets
Resistive circuit file for arbitrary connection
Extrapolation
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.subckt test 1 2 3 g r1 1 2 0.1 r2 2 3 0.2 r3 1 3 0.3 .ends test
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Convert [S] into SPICE model
Curvefitting SPICE models can be difficult without causality correction.
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S-to-SPICE Conversion S param SPICE model
Passivity & Causality
Correction S param
w/o causality correction with causality correction
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Scale [S] impedance
Traditional 3D solvers tend to be less accurate in computing trace impedance.
Scaling [S] impedance helps correlation (and generation of corner models).
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S Param
Impedance Scaling
(Z) A*(Z)
S Param
Impedance scaling has more effect at low frequencies!
Scale up impedance by 1%
We can scale [S] delay, too!
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IEEE and OIF specs.
Want to find out the maximum data rate a component can support? Use ADK to quickly compare with multiple IEEE and OIF specs.
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Channel optimization
Fixed cursors vs. optimized TX tap coefficients Fixed vs. random data patterns Switch between NRZ and PAM4 in one click.
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Eye diagram, TX tap coefficients, Jitter
Channel Optimization S Param
NRZ PAM4
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2D field solver
Templates for common structures User-defined files for arbitrary cross sections Ground or float conductors Output impedance & RLGC W-element model
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Trapezoidal cross section
RLGC model, impedance
2D Field Solver
Cross-sectional geometry
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Plot multiple [S] curves
Plot S-param curves from different files Plot time-domain curves from different files Save to .bmp, .jpg, … for reports Compare with industry standard spec.
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Plot S Param
or time-domain
data
.bmp, .jpg, etc.
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Summary
ADK greatly enhances productivity in processing S parameters. Many complex SI operations in one mouse click. Data mining S parameters is made easy. Avoid tedious and error-prone setups in ADS. CPU-intensive simulations are left for HFSS and ADS.
ADK helps engineers do sanity check on their VNA, HFSS and ADS results.
ADK is a great training tool for new SI engineers. 28 SI Apps in one place.
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SI3D
Fast 3D solver for connector and cable
06/13/2013
What is SI3D
SI3D is a novel 3D SI solver that creates S parameters in minutes, instead of days, for rapid design iteration.
3D objects are input in .sat, .stp, or .igs format
Summary of impedance and RLGC matrices at multiple cross sections and Touchstone file are output for detailed analysis.
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Why do we need another 3D solver
In this example, SI3D took 10 minutes on a laptop, and HFSS took 1 day on 10 workstations with 32 GB each.
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Insertion loss Return loss
SI3D
HFSS HFSS
SI3D
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HFSS limitations
Traditional 3D solvers tend to be less accurate in computing return loss (and impedance), because fewer meshes are assigned in the transverse direction.
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SI3D models each cross section with many meshes
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SI3D outputs impedance summary and Touchstone file
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Summary
SI3D complements 3D full-wave solvers by providing S param in ultra-fast turn-around time.
Such crucial design parameters as impedance and RLGC matrices at multiple cross sections are provided for detailed analysis.
SI3D can be more accurate than traditional 3D solvers in predicting return loss and TDR impedance profile.
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Free 2D field solver
and S-param viewer
Visit
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06/13/2013
Free 2D field solver
Compute impedance and create W-element RLGC models for microstrip or striplines with trapezoidal cross section and mixed width/spacing.
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* No. of lines 4 * Lo 3.118439e-07 1.368082e-08 3.118400e-07 6.395089e-11 1.394415e-09 2.771430e-07 1.247383e-12 2.719850e-11 5.283962e-09 2.771455e-07 * Co 1.325639e-10 -5.863922e-12 1.325701e-10 -1.343702e-15 -6.741986e-13 1.488909e-10 -5.916489e-19 -2.965864e-16 -2.866957e-12 1.488847e-10 Use ADK for more functionalities (for
coplanar waveguide, floating conductors, multiple dielectrics or arbitrary cross section)
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Free S-param viewer
Plot single-ended or mixed-mode S-param from multiple Touchstone files
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Use ADK for more functionalities (to resize, enter spec curves, import more than 2 files or plot Y, Z and VSWR) .
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Conclusion
Several SI tools were presented to enhance productivity and reduce design cycle time.
In-Situ De-Embedding (ISD) saves $$$ and time in extracting DUT.
Advanced Signal Integrity Design Kits (ADK) saves $$$ and time in processing S parameters.
SI3D saves $$$ and time in simulating connector and cable.
Free 2D field solver and S-param viewer are made available.
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