an introduction to vhdl

An Introduction to VHDL

Satnam Singh

Xilinx

FPGA

FPGAs

FPGAs

Design Flow

Schematics (Xlib)

VHDL History

United States Department of “Defence”

Specification and modelling language

VHDL

1983: Intermetrics, IBM and Texas Instruments awarded design contract for VHDL.

1985: Final language version produced for DOD

1987: IEEE Standard 1076-1987

1988 ANSI Standard

“VHSIC Hardware Description Language”

VHSIC = Very High Speed Integrated Circuit

How is VHDL Used?

System simulation (modelling)

Test benches

Synthesis

Why not use normal languages?

Programming languages like C and Java are sequential: one thing happens at a time.

Hardware is totally concurrent: every gate is running at the same time as every other gate.

Communication occurs over wire connections.

Concurrency Models

Cycle based simulation: every n-nanoseconds update the state of the circuit.

Event based: only update the system when certain events occur.

VHDL uses even based simulation.

std_ulogic and std_logic

type std_ulogic = (‘U’, -- unitialised ‘X’ , -- forcing unknown ‘0’, -- forcing zero ‘1’, -- forcing one ‘Z’, -- high impedance ‘W’, -- weak unknown ‘L’, -- weak zero ‘H’, -- weak one ‘-’) -- don’t know

nandgate

event based

event based

event based fixed

chain

krav

Simulations

counters

counter

resetable counter

Synchronization

process (a, b, c)

wait until clk’event and clk=‘1’ ;

wait for 50 ns ;

variables

multi_adder

Quiz 1architecture question of quiz1 is signal y : integer := 0 ;begin

process is variable p : integer ; begin y <= 2 ; p := 2 ; y <= y + 3 ; p := p + 3 ;

wait for 10 ns ; -- What are the values of y and p? end process ;

end architecture question ;

-- onecounter_package.vhdpackage onecounter_package is

constant output_size : positive := 4 ; constant input_size : positive := 2**(output_size-1) ;

subtype count_type is natural range 0 to 2**output_size ;

component onecounter is port (signal input : in bit_vector (1 to input_size) ; signal count : out count_type) ; end component onecounter ;

end package onecounter_package ;

use work.onecounter_package.all ; entity onecounter is port (signal input : in bit_vector (1 to input_size) ; signal count : out count_type) ; end entity onecounter ;

-- onecounter_behav.vhduse work.onecounter_package.all ;architecture behav of onecounter isbegin

counting : process (input) variable total : count_type ; begin -- Calculate the total using variables. total := 0 ; for i in input'range loop if input(i) = '1' then total := total + 1 ; end if ; end loop ; -- Assign the calculated total to the output signal. count <= total ; end process counting ; end behav ;

Quiz 2entity quiz2 isend entity quiz2 ;

architecture behav of quiz2 is type num_array is array (1 to 4) of integer ; signal nums : num_array := (2,4,3,1) ; signal total : integer ;begin

add : process (nums) begin total <= 0 ; for i in nums'range loop total <= total + nums(i) ; end loop ; end process add ; end behav ;

-- toggle_package.vhdpackage toggle_package is

component toggle is port (signal clk : in bit ; signal t : out bit) ; end component ;

end toggle_package ;

entity toggle is port (signal clk : in bit ; signal t : out bit) ; end entity toggle ;

-- toggle_behav.vhdarchitecture behav of toggle isbegin

toggling : process variable toggleValue : bit := '0' ; begin wait until clk'event and clk='0' ; toggleValue := not toggleValue ; t <= toggleValue ; end process toggling ;end behav ;

Synthesis

toggle