04-cdma2000 bsc hardware system

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ISSUEISSUE

CDMA2000 BSC Hardware SystemCDMA2000 BSC Hardware SystemCDMA2000 BSC Hardware System

1.01.0

Confidential Information of Huawei. No Spreading without Permission. Security Level: Internal

ContentsContents

Overview

Clock System

Windup

CDMA BSS Network StructureCDMA BSS Network Structure

BSC/IWF/PCF PDSN

A1/A2/A5

A10/A11

Internet

PSTNISDN

Optical Fiber

SoftBTS

MSBSC/IWF/PCF

CDMA WLL Network StructureCDMA WLL Network Structure

MIP HA

PDSN/FA

A10/A11

LEV5Optical

FiberSoftsite

Remote Model

AbisE1/STM-1

Module

RAC6610

INTERNET

Rack DistributionRack Distribution

� CDMA Switch Subrack (CSWS)

� CDMA Integrated Processing Subrack (CIPS)

� CDMA Resource and Packet Subrack (CRPS)

� CDMA Packet Module Subrack (CPMS)

� CLocK processing Module (CLKM)

� CDMA Integrated Management System (CIMS)

Large capacity BSC is divided into following functional blocks. In general each block corresponds to single subrack. These are:

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Large Capacity BSS Rack DistributionLarge Capacity BSS Rack Distribution

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Small Capacity BSS Rack DistributionSmall Capacity BSS Rack Distribution

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Small Capacity RAC Rack DistributionSmall Capacity RAC Rack Distribution

CIPSCIPSTo/From BTS To/From LE

CRPSTo/From PDSN

Optical fiber

GE(Gigabit Ethernet)/FE(Fast Ethernet)

To/From NMSEthernet

(V5)(Abis)

(A10/A11)

LANSMC

CCTR (CDMA Controller Rack)

CBUR (CDMA BUsiness Rack)

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Cabling Through

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Fan boxCable trough

Air guide subrack

Fan boxCable trough

Keyboard

Dummy panel

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Dummy Panel

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Lanswitch

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� � � �� BAM Server

Cabling though

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CIPS/CPMS

ContentsContents

Overview

Clock System

Windup

Boards Position in CSWS Boards Position in CSWS

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Functional Diagram of CSWSFunctional Diagram of CSWS

Other subracksOther subracks

BAMBAMCMPU

CLPCCLPC

Controlling unit of line interface card

Provide eight 155Mbps ATM-over-SDH optical interfaces

Guarantee the ATM QoS

CLPC is responsible for:

CLPC board appearanceCLPC board appearance

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Fast switching of fixed length-packets

CNETCNET

40 switching network ports

Synchronization clock function

CNET is responsible for:

CNETCNET

Clock module

RUNCLKACT

CLK IN0

CLK IN1

CLK OUT0

CLK OUT1CLK IN2CLK IN3

Managing & allocating the resources of CNET

CMPUCMPU

Management proxy for other subracks

Managing & maintaining the boards in CSWS

CMPU is responsible for:

Controls the active/standby switchover of the CNET

CMPUCMPU

IDE Hard Disk

RUNALMACT

Traffic FlowTraffic Flow

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Maintenance FlowMaintenance Flow

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CDMA WLL CIPSCDMA WLL CIPS

1514131211109876543210

CXI E/CBIE

CLCB provides V5 signaling processing (Layer2)

ContentsContents

Overview

Clock System

Windup

Functional Diagram of CIPSFunctional Diagram of CIPS

Abis Physical interface

Service frame selection, frame allocation

Multiplexing/Demultiplexing

Speech encoding and decoding

Signaling processing

A1/A2 physical interface

Packet to C

acket to CR

Circuit data processing

Boards Position in CIPS Boards Position in CIPS

1514131211109876543210

Note: CXIE/CBIE/COIE can provide the Abis interface.CAIE/CSTU can provide the A1/A2 interface.

The switching & multiplexing functions of ATM services

CMUXCMUX

Synchronization clock function

Manages & monitors the software loading of all boards in CIPS

Monitors the power of subrack, fan box and environment operating status

CMUX is responsible for:

CMUX AppearanceCMUX Appearance

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CXIECXIE

n#E1… ...

IMA Chip

E1 Interface Module

IMA Processing Module

IMA Processing

Module

E1 Interface Module

High-rate ATM flow High-rate ATM flow

IMA: Inverse Multiplexing on ATM

CXIECXIE

24 standard E1/T1 interfaces

Providing a processing capability of 24 E1/T1 IMAs and supporting pure ATM over E1 mode (UNI mode)

the channels for inter-working between CIPS and CRPS (Small capacity BSC)

CXIE is responsible for:

CXIE AppearanceCXIE Appearance

To BTS

CBIECBIE

32 standard E1/T1 interfaces

Providing a processing capability of 32 E1/T1 IMAs and supporting pure ATM over E1 mode (UNI mode)

the channels for inter-working between CIPS and CRPS (Small capacity BSC)

CBIE is responsible for:

Supporting Fractional ATM function

CBIE AppearanceCBIE Appearance

To BTS

J19 J18

To BTS

COIECOIE

Providing one 155Mbps STM-1 standard optical interface

Providing the IMA processing of 63 E1s and supporting UNI mode.

COIE is responsible for:

Supporting Fractional ATM function

COIE AppearanceCOIE Appearance

To BTS

CFMRCFMR

Selection/DistributionSelection/Distribution

BTS1 BTS2

Power controlPower control

Service Frame

Frame protocol processing

Multiplexing/DemultiplexingMultiplexing/Demultiplexing

LAC SARLAC SAR

LAC PDU

TRAU frame TRAU frame RLPRLP

CSPUCSPU CEVCCEVC CPPUCPPUSignaling Voice Packet data

TRAU - Transcoder and Rate Adaptation Unit

CFMR AppearanceCFMR Appearance

CEVCCEVC

Supports three types of coding: EVRC, QCELP8K and QCELP13K

�Perform ISLP rate adaptation for circuit data services below 64Kbps

� Provides the echo cancellation function between BSC & MSC (CEVD could not support this )

ISLP – Inter System Link Protocol

CIWFCIWF

Asynchronous data processing

Facsimile G3 processing

Analog facsimile processing

CLAPCLAP

Process the A1/A2 signaling (Layer2)

Measure, maintain and troubleshoot the A1/A2 signaling

CSPUCSPU

Process the upper-layer signaling including:� Um interface� Abis interface� A1/A2 interface� A3 interface� A7 interface� A9 interface

CAIECAIE

Provide 32 E1/T1 interfaces

Clock extraction

CAIE AppearanceCAIE Appearance

S5 S4 S9 S8

S12S15S18

S3 S2 S16 S17 S10 S13

To GCKP

CSTUCSTU

Provide 63 E1 transmission over SDH

Clock extraction

CSTU AppearanceCSTU Appearance

To GCKP

Voice Traffic Flow in CIPSVoice Traffic Flow in CIPS

CXIE CFMR CMUX CEVC CAIE

ATM Bus

Extended TDM Bus

TDM Bus

Packet Traffic Flow in CIPSPacket Traffic Flow in CIPS

CMUXCXIE CFMR

ATM BusCBTS

CEVCCIWF

Circuit Data Traffic Flow in CIPSCircuit Data Traffic Flow in CIPS

CXIE CFMR CMUX

To CBTS

ATM Bus

Expand TDM Bus

TDM BUS

Voice Signaling Flow in CIPSVoice Signaling Flow in CIPS

CXIE CFMR CSPU CMUX CAIE

ATM BUS

Expand TDM Bus

TDM BUS

Out-band signaling In-band signaling

Packet signaling Flow in CIPSPacket signaling Flow in CIPS

CXIE CFMR CSPU

ATM Bus

Outbandsignaling

To CRPS

Inband signaling

To CBTS

Circuit signaling Flow in CIPSCircuit signaling Flow in CIPS

CXIE CFMR CSPU

ATM Bus

Out-band signaling

In-band signaling

To CBTS

CLAPCAIECMUX

ATM Bus

Expand TDM Bus

TDM BUS

ContentsContents

Overview

Clock System

Windup

Provide periodical time synchronization

Packet data service processing

Functional Diagram of CRPSFunctional Diagram of CRPS

Provide A3/A7physical interface

Resource management

From CIPS

From original CIPS

To CIPSFrom CLKM

To PDSN

To target CIPS

Boards Position in CRPSBoards Position in CRPS

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CMUXCMUX

Manage & maintain the boards in CRPS

�Provide RFN for the system

� The CMUX in the CRPS is the same as the CMUX in the CIPS.

CXIECXIE

Provide inter-BSC A3/A7 interfaceand inter-subrack interface for small capacity

�Offer 24 standard E1s/T1s

� The CXIE boards in CRPS and CIPS are the same

CRMUCRMU

Note: � The CRMU’s hardware structure is the same as that of CSPU’s,

so the indicator meaning of CRMU are also the same.

Process the A3, A7 and A9 interfaces signaling

Maintenance management and distribution of the A2, A3 and A8 interface resources

CPPUCPPU

Store, process and transfer the data packets

Work in load sharing to achieve resource pool mechanism

Note: � The CPPU’s hardware structure is the same as that of CSPU’s� The indicator states are also similar to the CSPU indicators.

CPCUCPCU

Signaling Processing A11

CBPU and PPU Session ID management

Setup of signaling and traffic connection

� The CPCU’s hardware structure is the same as that of CSPU’s.� The indicator states are also similar to the CSPU indicators.

CBPUCBPU

Downlink data buffering, processing and transferring

Note: �The CBPU’s hardware structure is the same as that of CSPU’s.�The indicator states are also similar to the CSPU indicators.

Work in load sharing mode to achieve resource pool mechanism

Re-sequencing the packet sent from PDSN (transferred via CHAC)

CHACCHAC

Transfer the traffic data (A10 interface) from PDSN to CBPU

Receives the traffic data (A8 interface) from CPPU and SDB data

from CPCU, and transfer them to PDSN via the A10 interface

Transfer A11 signaling data from PDSN to CPCU directly

Provide 1000Mb Ethernet interface to PDSN

Downlink Data Flow in CRPSDownlink Data Flow in CRPS

CHAC CBPU CPPU CMUX

To PDSN To CIPS

ATM Bus

Uplink Data Flow in CRPSUplink Data Flow in CRPS

CHAC CBPU CPPU CMUX

To PDSN To CIPS

ATM Bus

Bypass the CBPU

Signaling flow in CRPSSignaling flow in CRPS

CHAC CPCU CRMU CMUX

To PDSN To CIPS

ATM Bus

CDMA WLL CRPSCDMA WLL CRPS

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CUMB - Subscriber Data Management

CSMU - Message processing and protocol conversion the Virtual Core Network module and the Message Center

CLIU - Provides ATM optical interface for the connection with the CMUX in CIPS

CDMA BSS & WLL CPMSCDMA BSS & WLL CPMS

1514131211109876543210

For data packets > 40Mbps

ContentsContents

Overview

Clock System

Windup

Types of SynchronizationTypes of Synchronization

� Transmission Synchronization

� Synchronize the transmission between BSC and MSC

� Time Synchronization

� Synchronize the radio frame number (RFN) between BSC and

CLKMCLKM

CLKM (CLocK processing Module ) is composed of two parts:

� GCKP (GPS/GLONASS & ClocK Processing Board )

� GCKB (Backplane of CLKM )

ALM ACT COM IN0 IN1 OUT ANT

CLK_B COM_B ETH_B CLK_A COM_A ETH_A

Panel of GCKB

Panel of GCKP (Active/Standby)

ALM ACT COM IN0 IN1 OUT ANT

Clock System

StructureB

lock System Structure

BITS clock source

2MHz circuit clock extracted from A-Interface

RFN cell

8k ¡¢32M

MSCA1/A2

PDSNA10/A11

GCKP GCKP

RFN pulse

8k ¡¢32M

RFN cell

PP16Sabsolute time infomation

A10/A11

A3/A7BSC

Physical ConnectionPhysical Connection

RUN ALM ACT COM IN0 IN1 TEST ANT

7#CMUX (CRPS/CRMS)

ETH_BCOM_BCLK_B ETH_ACOM_ACLK_A

8#CMUX (CRPS/CRMS)

RUN ALMACT COM IN0 IN1 TEST ANT

To GPS/Glonass antenna

ContentsContents

Overview

Clock System

Windup

Software Loading FlowSoftware Loading Flow

CMUXin CRPS

Other boardsin CRPS

CMUXin CIPS

Other boardsIn CIPS

……

GCKBIn

Voice Signaling FlowVoice Signaling Flow

TDM switching

AAL2 switching

AAL2 termination

TDM bearing

AAL2 bearing

AAL5 bearing

In-band signaling SS7

signaling

In-band signaling

Out-band signaling

Voice Service FlowVoice Service Flow

TDM switching

AAL2 switching

AAL2 terminationTDM bearing

AAL2 bearing

Packet Data Signaling FlowPacket Data Signaling Flow

AAL2 switching

AAL2 termination

AAL2 bearing

AAL5 bearing

In-band signaling

Out-band signaling

Ethernet bearing

AbisMS

SS7 signaling

A11CMUX

TDM switching

TDM bearing

AAL2 switching

AAL2 termination

Ethernet bearing

AAL2 bearing

AAL5 bearing

AbisMS

CRPS/CPMS

A10CMUX

Packet Data Service FlowPacket Data Service Flow

Configuration for 1,200,000 SubscribersConfiguration for 1,200,000 Subscribers

� BHCA: 2400k

� Voice traffic volume: 24,000Erl

� Um interface: 54,000TCE (traffic channel element)

� A-interface: 38400CIC,1280E1

� Abis interface: 960E1

� 3840 Sector Carriers

� 1,200k Voice Subscribers(0.02Erl/sub)

� 70,000 PPP connections

� 5,000 active PPP connections

� Total flow of packet data: 200Mbps

Typical BSS Hardware Configuration (1)Typical BSS Hardware Configuration (1)

CIMS 1

CPMS 0

CRPS 1

CIPS 4

CSWS 0

CLKM 1

2120,000Subs

0.02Erl/sub

CIMS 1

CPMS 0

CRPS 1

CIPS 1

CSWS 0

CLKM 1

130,000 Subs0.02Erl/sub

Number of SubracksNumber of CabinetsCapacity

CIMS 1

CPMS 2

CRPS 1

CIPS 40

CSWS 1

CLKM 1

151,200,000Subs

0.02Erl/sub

CIMS 1

CPMS 1

CRPS 1

CIPS 10

CSWS 1

CLKM 1

5300,000 Subs0.02Erl/sub

1,200k300k120k30kNumber of voice subscribers (0.02Erl/sub)

3,84096038496Number of sector carriers supported

1,2803209624Number of E1/T1 ports at Abis interface

1,28032012832Number of E1/T1 ports at A-interface

38,4009,6003,840960Number of circuits at A-interface

40,96010,2404,0961,024TC

54,000 TCE13,500 TCE5,400 TCE1,350 TCENumber of channels at Um interface

24,000Erl6,000Erl2,400Erl600ErlVoice traffic volume

2,400k600k240k60KBHCA

40 CIPS10 CIPS

1,200,000 Subscribers

300,000 Subscribers

120,000 Subscribers

4 CIPS

30,000 Subscribers

1 CIPS

NumberIndexes

31,6007,9003,160790Number of circuit data service subscribers

948 Erl237 Erl94.8 Erl23.7 ErlTraffic of circuit data services

200 Mbps100 Mbps40 Mbps10 MbpsTotal flow of packet data

5,0002,400960240Number of packet data service active PPP connections

70,00035,00035,00030,000Number of packet data service PPP connections

40 CIPS10 CIPS

1,200,000 Subscribers

300,000 Subscribers

120,000 Subscribers

4 CIPS

30,000 Subscribers

1 CIPS

NumberIndexes

Typical RAC Hardware Configuration (1)Typical RAC Hardware Configuration (1)

CIMS 1

CPMS 2

CRPS 1

CIPS 16

CSWS 1

CLKM 1

7160,000Subs

0.09Erl/sub

CIMS 1

CPMS 0

CRPS 1

CIPS 4

CSWS 0

CLKM 1

240,000 subs0.09Erl/sub

15,3603,840960Number of voice channels in V5 interface

555Number of A3/A7 interfaces

51212832Number of E1/T1 ports for V5 interface

51212832Number of E1/T1 ports for Abisinterface

21,600 TCE5,400 TCE1,350 TCEAir interface channel

14,400Erl3,600Erl900Erl

1280k320k80kBHCA

480000 subscribers (0.03Erl/sub)160000 subscribers q(0.09Erl/sub)

120000 subscribers (0.03Erl/sub)40000 subscribers (0.09Erl/sub)

30000 subscribers (0.03Erl/sub)10000 subscribers (0.09Erl/sub)

Maximum number of subscribers

Full configuration of 1X large capacity16 CIPS + 2CPMS

Full configuration of 1X small capacity4 CIPS + 1 CPMS

Single subrack of 1X1 CIPS

Number Indexes

Voice traffic volume

360K BHSM120 k BHSM60 k BHSMShort message processing rate in busy hours

576 asynchronous data/288 PC fax/288 analog fax

144 asynchronous data/72 PC fax /72 analog fax

36 asynchronous data/18 PC fax /18 analog faxIWF

10,000(2500*4)2,5002,500

Maximum number of PPP connections for data service activities

240,000(60,000*4)60,000Maximum number of data service PPP connections

400M(100M*4)40MTotal flow of packet data

Full configuration of 1X large capacity16 CIPS

Full configuration of 1X small capacity4 CIPS

Single subrack of 1X1 CIPS

Number Indexes

04-cdma2000 bsc hardware system

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