altdq dqs2 ip core user guide · for the data (dq) and data strobe (dqs) signals in arria®v,...

ALTDQ_DQS2 IP Core User Guide2014.07.07

UG-01089 Subscribe Send Feedback

The Altera ALTDQ_DQS2 megafunction IP core controls the double data rate (DDR) I/O elements (IOEs)for the data (DQ) and data strobe (DQS) signals in Arria® V, Cyclone® V, and Stratix® V devices. A DQgroup is composed of one DQS, one optional complementary DQS, and up to 36 configurable DQ I/Os.

Related InformationIntroduction to Altera IP Cores

ALTDQ_DQS2 FeaturesThe ALTDQ_DQS2 IP core has the following features:

• Access to dynamic on-chip termination (OCT) controls to switch between parallel termination duringreads and series termination during writes.

• High-performance support for DDR interface standards.• 4- to 36-bit programmable DQ group widths.• Half-rate registers to enable successful data transfers between the I/O registers and the core logic.• Access to I/O delay chains to fine-tune delays on the data or strobe signals.• Access to hard read FIFO.• Access to latency shifter FIFO and data valid FIFO for efficient control of DQS gating and read operations

(Arria V and Cyclone V devices only).

ALTDQ_DQS2 Device SupportThe ALTDQ_DQS2 IP core supports the following devices:

• Arria V devices• Cyclone V devices• Stratix V devices

Resource Utilization and PerformanceTo view the compilation reports in the Quartus II software, follow these steps:

1. On the Processing menu, click Start Compilation to run a full compilation.2. After compiling the design, on the Processing menu, click Compilation Report.3. In the Table of Contents browser, expand the Fitter folder by clicking the “+” icon.4. ExpandResource section, and selectResourceUsage Summary to view the resource usage information.

ISO9001:2008Registered

© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX wordsand logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All otherwords and logos identified as trademarks or service marks are the property of their respective holders as described atwww.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance withAltera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumesno responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

https://www.altera.com/servlets/subscriptions/alert?id=UG-01089

mailto:[email protected]?subject=Feedback%20on%20(UG-01089%202014.07.07)%20ALTDQ_DQS2%20IP%20Core%20User%20Guide&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

http://www.altera.com/literature/ug/ug_megafunction_overview.pdf

http://www.altera.com/support/devices/reliability/certifications/rel-certifications.html



5. Expand Resource section, and select Resource Utilization by Entity to view the resource utilizationinformation.

Installing and Licensing IP CoresThe Quartus II software includes the Altera IP Library. The library provides many useful IP core functionsfor production use without additional license. You can fully evaluate any licensedAltera IP core in simulationand in hardware until you are satisfied with its functionality and performance. Some Altera IP cores, suchas MegaCore® functions, require that you purchase a separate license for production use. After you purchasea license, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 1: IP Core Installation Path

acdsquartus - Contains the Quartus II softwareip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code<IP core name> - Contains the IP core source files

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux itis <home directory>/altera/ <version number>.

Note:

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

Customizing and Generating IP CoresYou can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog displays IPcores available for the current target device. The parameter editor guides you to set parameter values foroptional ports, features, and output files.

IP Catalog and Parameter EditorTheQuartus II IP Catalog (Tools > IPCatalog) and parameter editor help you easily customize and integrateIP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generatefiles representing your custom IP variation.

The IP Catalog automatically displays the IP cores available for your target device. Double-click any IP corename to launch the parameter editor and generate files representing your IP variation. The parameter editorprompts you to specify your IP variation name, optional ports, architecture features, and output file generationoptions. The parameter editor generates a top-level .qsys or .qip file representing the IP core in your project.Alternatively, you can define an IP variation without an open Quartus II project. When no project is open,select the Device Family directly in IP Catalog to filter IP cores by device.

ALTDQ_DQS2 IP Core User GuideAltera Corporation

Send Feedback

UG-01089Installing and Licensing IP Cores2 2014.07.07

http://www.altera.com/licensing

http://www.altera.com/literature/manual/quartus_install.pdf

mailto:[email protected]?subject=Feedback%20on%20ALTDQ_DQS2%20IP%20Core%20User%20Guide%20(UG-01089%202014.07.07)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusivesystem interconnect, video and image processing, and other system-level IP that are not available inthe Quartus II IP Catalog.

Note:

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.• Right-click an IP core name in IPCatalog to display details about supported devices, installation location,

and links to documentation.

Figure 2: Quartus II IP Catalog

Search and filter IP for your target device

Double-click to customize, right-click for information

The IP Catalog and parameter editor replace the MegaWizard™

Plug-In Manager in the Quartus IIsoftware. The Quartus II software may generate messages that refer to the MegaWizard Plug-In

Note:

Manager. Substitute "IP Catalog and parameter editor" for "MegaWizard Plug-In Manager" in thesemessages.

Using the Parameter EditorThe parameter editor helps you to configure your IP variation ports, parameters, architecture features, andoutput file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter valuesfor specific applications.

• View port and parameter descriptions, and links to documentation.

Altera CorporationALTDQ_DQS2 IP Core User Guide

Send Feedback

3Using the Parameter EditorUG-010892014.07.07


• Generate testbench systems or example designs (where provided).

Figure 3: IP Parameter Editors

View IP portand parameterdetails

Apply preset parameters forspecific applications

Specify your IP variation nameand target device

Legacy parametereditors

Adding IP Cores to IP CatalogThe IP Catalog automatically displays Altera IP cores found in the project directory, in the Altera installationdirectory, and in the defined IP search path. You can include IP libraries and files from other locations byadding search path locations. To add global or project-specific search path locations, clickTools >Options >IP Search Locations and specify the path to your IP cores.


Send Feedback

UG-01089Adding IP Cores to IP Catalog4 2014.07.07


Figure 4: Specifying IP Search Locations

Adds new global IP search paths

Changes search path order

Adds new project-specific IP search paths

Lists current project and global search paths

If your project includes two IP core files with the same name, the following search path precedence rulesdetermine the resolution of files:

1. Project directory.2. Project database directory.3. Project IP search path specified in IP Search Locations, or with the SEARCH_PATH assignment in the

revision .qsf.4. Global IP search path specified in IP Search Locations, or with the SEARCH_PATH assignment in the

quartus2.ini file.5. Quartus II software libraries directory, such as <Quartus II Installation>\libraries.

Specifying IP Core Parameters and OptionsFollow these steps to specify IP core parameters and options.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.

2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files inyour project. If prompted, also specify the target Altera device family and output file HDL preference.Click OK.

3. Specify parameters and options for your IP variation:

• Optionally select preset parameter values. Presets specify all initial parameter values for specificapplications (where provided).

• Specify parameters defining the IP core functionality, port configurations, and device-specific features.• Specify options for generation of a timing netlist, simulation model, testbench, or example design

(where applicable).


Send Feedback

5Specifying IP Core Parameters and OptionsUG-010892014.07.07


• Specify options for processing the IP core files in other EDA tools.

4. Click Finish or Generate to generate synthesis and other optional files matching your IP variationspecifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL filesfor synthesis and simulation. Some IP cores also simultaneously generate a testbench or example designfor hardware testing.

The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files inProject to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Files Generated for Altera IP CoresThe Quartus II software generates the following output for your IP core.

Figure 5: IP Core Generated Files

Notes:1. If supported and enabled for your IP variation2. If functional simulation models are generated

<Project Directory>

<your_ip>_sim 1

<Altera IP>_instance.vo - IPFS model 2

<simulator_vendor><simulator setup scripts>

<your_ip>.qip - Quartus II IP integration file

<your_ip>.sip - Lists files for simulation

<your_ip>_testbench or _example - Testbench or example design1

<your_ip>.v, .sv. or .vhd - Top-level IP synthesis file

<Altera IP_name>_instance

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist1<your_ip>.cmp - VHDL component declaration file<your_ip>.bsf - Block symbol schematic file

<your_ip> - IP core synthesis files<your_ip>.sv, .v, or .vhd - HDL synthesis files<your_ip>.sdc - Timing constraints file

<your_ip>.ppf - XML I/O pin information file 1

<your_ip>.spd - Combines individual simulation scripts 1

<your_ip>_sim.f - Refers to simulation models and scripts 1

Upgrading Outdated IP CoresEach IP core has a release version number that corresponds to its Quartus II software release. When youinclude IP cores from a previous version of the Quartus II software in your project, click Project > UpgradeIP Components to identify and upgrade any outdated IP cores.

TheQuartus II software prompts you to upgrade an IP core when the latest version includes port, parameter,or feature changes. The Quartus II software also notifies you when IP cores are unsupported or cannotupgrade in the current version of the Quartus II software. Most Altera IP cores support automatic simulta-neous upgrade, as indicated in the Upgrade IP Components dialog box. IP cores unsupported by auto-upgrade may require regeneration in the parameter editor, as indicated in the Upgrade IP Componentsdialog box.


Send Feedback

UG-01089Files Generated for Altera IP Cores6 2014.07.07


Before you begin

Upgrading IP cores changes your original design files. If you have not already preserved your original sourcefiles, click Project > Archive Project and save the project archive.

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IPcore variation.

File paths in a restored project archive must be relative to the project directory and you mustreference the IP variation .v or .vhd file or .qsys file, not the .qip file.

Note:

2. ClickProject >Upgrade IPComponents. TheUpgrade IPComponents dialog box displays all outdatedIP cores in your project, along with basic instructions for upgrading each core.

3. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform AutomaticUpgrade. The IP variation upgrades to the latest version.

4. To upgrade IP cores unsupported by automatic upgrade, follow these steps:a. Select the IP core in the Upgrade IP Components dialog box.b. Click Upgrade in Editor. The parameter editor appears.c. ClickFinish orGenerate to regenerate the IP variation and complete the upgrade. The version number

updates when complete.

Example designs provided with any Altera IP core regenerate automatically whenever youupgrade the IP core in the Upgrade IP Components dialog box.

Note:

Figure 6: Upgrading Outdated IP Cores

Displays upgradestatus for all IP coresin the Project

Upgrades all IP core that support “Auto Upgrade”Upgrades individual IP cores unsupported by “Auto Upgrade”

Indicates that IP upgrade is:RequiredOptionalCompleteUnsupported

Example 1: Upgrading IP Cores at the Command Line

Alternatively, you can upgrade IP cores at the command line. To upgrade a single IP core, type thefollowing command:

quartus_sh --ip_upgrade -variation_files <my_ip_path> <project>


Send Feedback

7Upgrading Outdated IP CoresUG-010892014.07.07


To upgrade a list of IP cores, type the following command:

quartus_sh --ip_upgrade -variation_files "<my_ip>.qsys;<my_ip>.<hdl>; <project>"

IP cores older than Quartus II software version 12.0 do not support upgrade. Alteraverifies that the current version of the Quartus II software compiles the previous

Note:

version of each IP core. The MegaCore IP Library Release Notes reports anyverification exceptions forMegaCore IP. TheQuartus II Software andDevice SupportRelease Notes reports any verification exceptions for other IP cores. Altera does notverify compilation for IP cores older than the previous two releases.

Related Information

• MegaCore IP Library Release Notes

• Quartus II Software and Device Support Release Notes

ALTDQ_DQS2 Parameter SettingsYou can instantiate and parameterize using the IP Catalog and parameter editor GUI, or the ip-generatecommand through the command-line interface (CLI).

The following table lists the ALTDQ_DQS2 parameter settings.

Table 1: ALTDQ_DQS2 Parameter Settings

DescriptionCLI ParameterParameter Editor GUI Setting

Legal Values(1)NameLegal ValuesName

General Settings

This setting specifies thenumber of data (DQ) pinsto make as part of this DQSgroup.

The default value is 9 (9).

1 to 36PIN_WIDTH1 to 36Pin width

This setting specifies thedirection of the data pins(input, output, or bidirec-tional).

The default value is bidir(bidir).

input

output

bidir

PIN_TYPEinput

output

bidir

Pin type

(1) All CLI parameter values are type string, therefore you must enclose the values in double quotes.


Send Feedback

UG-01089ALTDQ_DQS2 Parameter Settings8 2014.07.07

http://www.altera.com/literature/rn/rn_ip.pdf

http://www.altera.com/literature/rn/rn_qts_dev_support.pdf




This setting specifies theextra output pins that youneed as part of a DQSgroup.

A common use for thissetting is to add datamaskpins.

The default value is 0 (0).

0 to 36EXTRA_OUTPUT_WIDTH0 – 36Extra output-onlypins

This setting specifies thefull-rate clock frequency ofthe incoming DQS groupsignal from the externaldevice in MHz.

The default value is300 MHz (300).

120–1068INPUT_FREQ1–1068Memory frequency

This setting enablesdynamic control of theDLLoffset.

Altera recommends usingthis setting for test purposesonly. ForDQS data capturecalibration, use the D1, D2,D3, and D4 delay chains.

true

false

USE_OFFSET_CTRL—Use DLL OffsetControl

This setting enables thehard FIFOs (read FIFO forStratix V devices and readFIFO, latency shifter FIFOand data valid FIFO forArria V and Cyclone Vdevices) as part of theALTDQ_DQS2 IP core.

true

false

USE_HARD_FIFOS—Enable hard FIFOs

Turn on this setting whenyou use the hard data validFIFO andwhen the captureclock is not gated.

This setting is available onlyfor Arria V and Cyclone Vdevices.

true

false

USE_DQSIN_FOR_VFIFO_

READ

—Use Capture Clockto clock the readSide of the HardVFIFO



Send Feedback

9ALTDQ_DQS2 Parameter SettingsUG-010892014.07.07




This setting enables the useof separate output clocksfor data and strobe.

This setting is disabled bydefault for Arria V andCyclone V devices.

true

false

DUAL_WRITE_CLOCK—Enable dual writeclocks

This setting enables run-time configuration ofmultiple delay chains, phaseshifts, and transfer registers.

Requires a correctlyformatted bitstream.

Formore information, referto DQS ConfigurationBlock Bit Sequence forArria V GZ and Stratix VDevices on page 38 andDQSConfigurationBlockBit Sequence for Arria Vand Cyclone V Devices onpage 51.

true

false

USE_DYNAMIC_CONFIG—Use dynamicconfiguration scanchains

Output Path

This setting doubles thewidth of the data bus on theFPGA side and clocks theFPGA side interface usingthe half-rate clock input.

If this setting is enabled,drive the hr_clock_in portwith the half-rate clocksignal.

When enabling hard readFIFO in a Stratix V device,youmust set this parameterto true.

This setting is enabled bydefault.

true

false

HALF_RATE_OUTPUT—Usehalf-rate outputpath



Send Feedback





This setting enables phaseshift on the output pathbased on the delay settingsfrom the DLL.

This setting is disabled bydefault.

true

false

USE_OUTPUT_PHASE_

ALIGNMENT

—Use output phasealignment blocks

Capture Strobe

This setting specifies thetype of capture strobe (DQSsignal from the externaldevice).

The default value is Single(single).

single

differential

complemen-

tary

CAPTURE_STROBE_TYPESingle

Differential

Complemen-tary

Capture strobe type

When enabled, thisparameter captures datawith an inverted capturestrobe.

Strobe inversion occursfrom dqsbusout (an outputport from the DQS delaychain block) to the clockinput of the DDIO_INblock.

This setting is enabled bydefault.

true

false

INVERT_CAPTURE_

STROBE

—Use invertedcapture strobe

This setting specifies thephase shift value for theDQSdelay chain to shift theincoming strobe in the datavalid window during readand write operations.

The default value is 90degrees (2).

This setting is for Stratix Vdevices only.

0

1

2

3

DQS_PHASE_SETTING0 degrees

45 degrees

90 degrees

135 degrees

DQS phase shift



Send Feedback





This setting enables thecapture strobe enable block,which allows control overthe preamble state of thecapture strobe.


true

false

USE_DQS_ENABLE—Use capture strobeenable block

This setting doubles thewidth of the capture strobeenable bus on the FPGAside and clocks the FPGAside interface using thehalf-rate clock input.

true

false

USE_HALF_RATE_DQS_

ENABLE

—Treat the capturestrobe enable as ahalf-rate signal

This setting specifies thevalue of phase shift to shiftthe full-rate clock signalthat drives the capturestrobe enable block.

The default value is 0degrees (0).

0

1

2

3

DQS_ENABLE_PHASE_

SETTING

0 degrees

45 degrees

90 degrees

135 degrees

DQS enable phasesetting

Output Strobe

This setting generates anoutput strobe signal basedon the OE signal and thefull-rate clock. This settingis enabled by default.

true

false

USE_OUTPUT_STROBE—Generate outputstrobe

This setting enables thebidirectional capture strobe(capture strobe and outputstrobe is on the same port).


true

false

USE_BIDIR_STROBE—Make capturestrobe bidirectional

This setting enables eitherthe differential orcomplementary outputstrobe.


true

false

DIFFERENTIAL_OUTPUT_

STROBE

—Differential/complementaryoutput strobe



Send Feedback





This setting stops theunidirectional outputstrobe using a user-provided reset signal. Thecore_clock_in and thereset_n_core_clock_in

signals are required.

true

false

USE_OUTPUT_STROBE_

RESET

—Use reset signal tostop output strobe

This setting specifies thetype of input signal totoggle the OCT control:

• Output StrobeEnable—Uses theoutput_strobe_ena

input as the OCTcontrol signal.

• Data WriteEnable—Uses thewrite_oe_in input asthe OCT control signal.

• Dedicated OCTEnable—Adds a oct_ena_in input to theinterface, which is usedas the OCT controlsignal.

The availability of theOutput Strobe Enable,Data Write Enable,andDedicatedOCTEnable aredependent on PIN_TYPE

and USE_BIDIR_STROBE

parameters.

Default value isDataWriteEnable.

0

1

2

OCT_SOURCEOutput StrobeEnable

Data WriteEnable

DedicatedOCTEnable

OCT Source



Send Feedback





This setting sets the DQSpreamble to high (DDR3),low (DDR2), or none:

• When you select lowand the strobe isbidirectional, the outputstrobe is held low for thefirst full rate cycle.

• When you selecthigh ornone, the strobe isdriven high for the firstfull rate cycle.

• Default value is low.

The ALTDQ_DQS2 IP coredoes notsupport DQStracking.

Note:

high

low

none

PREAMBLE_TYPEhigh

low

none

Preamble type

Related Information

• DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices on page 51

• DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices on page 38

• IP-Generate Command on page 88

ALTDQ_DQS2 Data PathsDescribes the read and write data paths and using other IP cores with the ALTDQ_DQS2 IP core.

DQ and DQS Input PathThe DQ and DQS input paths receive the DQ and DQS signals from the external device during readoperations.

DQ and DQS Input Paths for Stratix V Devices

The following figure shows the input paths where x = 0 to (n-1) and n = the number of DQ pins.



Send Feedback

UG-01089ALTDQ_DQS2 Data Paths14 2014.07.07


Figure 7: DQ and DQS Input Paths for Stratix V Devices

capture_strobe_ena

PRED Q

IN LO

strobe_ena_clock_in

DQS Enable Control

DQS Delay Chain

HI

DQSINDQSBUSOUT

IN OUT

capture_strobe_in

DQS Enable

read_data_in[x]

capture_strobe_out

read_data_out[x]

read_data_out[n+x]

(from DQS pin)

(from DQ pin)

DDIO_IN

You can use the DDIO_IN block with a soft orhard read FIFO in Stratix V devices. However,you can use this block with only a hard readFIFO in Arria V and Cyclone V devices.

When the hard read FIFO block is not present,the DQ and DQS path ends at the DDIO_INblock.

For bidirectional DQS, the input of thebuffer connects to the strobe_io port.

For bidirectional DQ, the input of the bufferconnects to the read_write_data_io[x] port.

Optional inversion occurs from dqsbusout(output port from the DQS delay chain block) tothe clock input of the DDIO_IN block.

CLK

Formore information about theDQ andDQS input pathwith a hard read FIFO block, refer to Figure8 and Figure 9.

Note:

Data Input Path for Arria V, Cyclone V, and Stratix V Devices

The DQ and DQS input paths in Arria V and Cyclone V devices are the same, except for an additional readFIFO block to implement the second-stage rate conversion DDIO. The high-speed 4 x 8 read FIFO, clockedby the DQS clock, implements the half-rate to full-rate conversion, if necessary.

The following figure shows the data input path (when you enable the hard read FIFO) for Arria V, CycloneV, and Stratix V devices.


Send Feedback

15Data Input Path for Arria V, Cyclone V, and Stratix V DevicesUG-010892014.07.07


Figure 8: Data Input Path for Arria V, Cyclone V, and Stratix V Devices

DATAINDelayChain

DDIOIn

FIFO REN LogicDATAOUT[0]DATAOUT[1]DATAOUT[2]DATAOUT[3]HR or FR Clock

DQS from DQS Logic

FIFO WRENLogic

ReadFIFO

WREN REN

This figure is applicable to Stratix V devices because Stratix V devices support optional hard read FIFO.

Blocks in DQ and DQS Data Input Path

The following table lists the blocks in the DQ and DQS input paths.

Table 2: Blocks in DQ and DQS Input Path

DescriptionBlock Name

• Represents the AND-gate control on the DQS input that groundsthe DQS input strobe when the strobe goes to Hi-Z after a DDRread postamble. TheDQS enable block enables the registers to allowenough time for the DQS delay settings to travel from the DQSphase-shift circuitry or core logic to all the DQS logic blocks beforethe next change.

• For more information about the DQS enable block, refer to the“Update EnableCircuitry” in theExternalMemory Interfaces chapterin the respective device handbook.

DQS enable

• Represents the circuitry that controls theDQS enable block. ADQSenable control block controls each DQS enable block.

• For more information about the DQS enable control block, refer tothe “DQS Postamble Circuitry” in the External Memory Interfaceschapter in the respective device handbook.

DQS enable control

• Represents the delay chains that delay signals.• For more information about the DQS delay chain block, refer to

“DQS Delay Chain” in the External Memory Interfaces chapter inthe respective device handbook.

DQS delay chain


Send Feedback

UG-01089Blocks in DQ and DQS Data Input Path16 2014.07.07


DQS Logic

The DQS input path in Arria V and Cyclone V devices has the following differences from Stratix V andearlier versions of the device families:

• A data valid FIFO delays the DQS enable path by up to 16 full-rate cycles. During a required calibrationprocess, you can increase the unknown delay, which the data valid FIFO implements, by 1, by pulsingthe INC_WR_PTR port. The delay wraps around after 16 increments.

• The DQS delay chain implements a static non-programmable phase shift of 90°.

The following figure shows the DQS input path in Arria V and Cyclone V devices.

Figure 9: DQS Input Path in Arria V and Cyclone V Devices

capture_strobe_ena[0]DDIOOut

FR Clock

capture_strobe_ena[1]

strobe_ena_hr_clock_invfifo_inc_wr_ptr

inc_wr_ptr

capture_strobe_in

Data ValidFIFO

DQS EnableControl

DQS DelayChain DQS Clock Tree

These ports are 2-bit wide because theDDIO_OUT block is driven by a half-rateclock, allowing you to enable DQS duringa half-rate cycle.

The data valid FIFO is a hard FIFOin Arria V and Cyclone V devices.

Read FIFOWrite Enable

Capture DDIO to Read FIFO Path

The capture DDIO block captures input data (DQ) on the rising and falling edges of the capture clock orstrobe (DQS).

For Stratix V devices, the capture DDIO block feeds the hard read FIFO or bypasses the hard read FIFO andgoes directly to the core. If the capture DDIO block connects directly to the core, the data is transmitted atfull rate. For protocols with bidirectional DQS, only an exact number of DQS edge is available for bothcapturing data in the capture DDIO block and then either in the read FIFO or in the core. The data transferfrom the capture DDIO block and the next stage is referred to as zero-cycle transfer. This means that thetransfer must happen on the same clock edge.

The hard read FIFO always changes the data rate from full-rate to half-rate, so if you choose to use full-rate,then you cannot use the Read FIFO.

For Arria V and Cyclone V devices, the capture DDIO block to Read FIFO path is similar, with the followingexceptions:

• The read FIFO must always be used and cannot be bypassed.• The read FIFO supports both half-rate and full-rate.

For Arria V, Cyclone V, and Stratix V devices, the hard read FIFO implements the functionality of a genericasynchronous FIFO. You can locate the hard read FIFO in a true dual-ported RAM. Data is written to thewrite side of the DQS clock domain and read from the read side of the core clock domain. For Arria V andCyclone V devices, the core clock domain can run at half the frequency and implements a full-rate to half-rate transformation. You can use the write enable and read enable signals to control when to write and readdata from the read FIFO. The same signal controls the increment of the write and read pointers. For protocols


Send Feedback

17DQS LogicUG-010892014.07.07


using a bidirectional strobe, the write enable signal is tied to VCC and DQS gating/ungating implementsthe write enable functionality.

For Arria V and Cyclone V devices, the hard data valid FIFO internally generates the write enable (orgating/ungating) signal, while the hard latency FIFO internally generates the read enable signal.

FIFO Control

For Arria V and Cyclone V devices, in addition to the read FIFO and the data valid FIFO, the location ofthe latency shifter FIFO is in each DQS group. The latency shifter FIFO takes in a read-enable commandfrom the core and implements a programmable latency of up to 32 cycles before feeding into the read-enableport of the read FIFO.

You can use the output of the data valid FIFO to perform the following tasks:

• To ungate the DQS logic when a strobe signal is capturing the data. In this case, the write-enable portmust always be '1' on the read FIFO.

• To enable the read FIFO write-enable port when a clock is in use.

The following figure shows the three FIFOs interconnection.

Figure 10: Data Valid FIFO, Latency Shifter FIFO, and Read FIFO Interconnection

The read FIFO block is a hard FIFO in Arria V,Cyclone V, and Stratix V devices. The latencyshifter FIFO and data valid FIFO are hardFIFO in Arria V and Cyclone V devices.

ReadFIFO

DOUT DIN

REN WREN

LatencyShifterFIFO

DataValidFIFO

Data to Core Data from DQ

To DQS EnableRead Data Enable from Core

When a read command is sent to the memory device, a read-data-enable token is pushed through the datavalid FIFO and the latency shifter FIFO. The data valid FIFO implements a latency equal to the read commandto data latency. When the token comes out of the data valid FIFO, the DQS signal is ungated. The latencyshifter FIFO then creates enough space between write and read pointers in the read FIFO to ensure that thedata read on the read side is correct. If the read FIFO is read at half-rate, the read FIFO also implements afull-rate to half-rate conversion.

The determination of the correct latencies to implement at each of these FIFOs is important and cannot bedone during compilation. When you attempt to implement your own custom memory solution, you mustalso implement some form of calibration algorithm.

To determine if the data coming from the read FIFO is valid, you must implement the read data valid latencyin soft logic.


Send Feedback

UG-01089FIFO Control18 2014.07.07


Related InformationUniPHY External Memory Interface Debug Toolkit

DQ and DQS Output PathThe DQ and DQS output path sends the DQ and DQS signal to the external device during write operations.

DQ and DQS Output Path for Stratix V Devices

The following figure shows the output path where n = the number of DQ pins and x = 0 to (n-1). is onlyapplicable for Stratix V devices.

This figure is only applicable for Stratix V devices. For Arria V and Cyclone V DQ and DQS outputpath, refer to Figure 13.

Note:

Figure 11: DQ and DQS Output Path for Stratix V Devices

write_oe_in[2x]

hr_clock_in

datain dataoutLO OUT

write_oe_in[2x+1]

D Q

write_data_in[3n+x]

hr_clock_in

HI OUT

write_data_in[n+x]

HI OUT

hr_clock_in

write_data_in[2n+x]datain dataout

HI Q

write_data_in[x]

LO

HI

Half-rate tosingle-rate outputenable registers

Output phasealignment registers

Alignmentclock

Writeclock

01

LO

01

datain dataout01

DDR output registersWriteclock

Alignmentclock

write_data_out[x]

Half-rate tosingle-rateoutput registers

Alignmentclock




010

1

01

Series terminationcontrol

LO

write_oe_in[x]

(to DQ pin)write_data_in[x]

write_data_in[n+x]

DFF

Alignmentclock

Writeclock

Series terminationcontrol

The alignment clock comes from the write-leveling delay chains. For more information, refer to “Leveling Circuitry”section in the External Memory Interfaces in Stratix V Devices chapter in the Stratix V Device Handbook.

The write clock comes from the PLL or the write-leveling delay chains. For more information, refer to “LevelingCircuitry” section in the External Memory Interfaces in Stratix V Devices chapter in the Stratix V Device Handbook.

The series termination control connects to the ALTOCT megafunction.

For bidirectional DQ, the output of the bufferconnects to the read_write_data_io[x] port.

The following figure shows the DQ and DQS output path for additional DQ pins usage, where y = 0 to (m-1)and m= the number of DQ pins


Send Feedback

19DQ and DQS Output PathUG-010892014.07.07

http://www.altera.com/literature/hb/external-memory/emi_uniphy_ref_EMIF_toolkit.pdf?GSA_pos=3&WT.oss_r=1&WT.oss=UniPHY%20Calibration


Figure 12: DQ and DQS Output Path (for Additional DQ Pins Usage) for Stratix V Devices

extra_write_data_in[3m+y]

hr_clock_in

datain dataoutHI OUT

extra_write_data_in[2m+y]

HI OUT

hr_clock_in

extra_write_data_in[m+y] datain dataoutHI OUT

extra_write_data_in[y]

LO

Half-rate tosingle-rate outputenable registers


Alignmentclock

01

Alignmentclock



010

1

01

VCC

DDR output registers

extra_write_data_out[y]

Write clock

LO

LO

extra_write_data_in[y] (to DQ pin)

Alignmentclock

Write clock

The alignment clock comes from the write-leveling delay chains.

The write clock comes from the PLL or the write-leveling delay chains.

Related Information

• External Memory Interfaces in Stratix V Devices

Blocks in DQ and DQS Output Path

The following table lists the blocks in the DQ and DQS output path.

Table 3: Blocks in the DQ and DQS Output Path

DescriptionBlock Name

Represents a group of registers that convert half-rate data tosingle-rate data.

Half-rate to single-rate output enable registers

Represents the circuitry required to phase shift theDQ-outputsignals. Use this block for write-leveling purposes in DDR3SDRAM interfaces.

Output phase alignment registers

Represents theDDIO registers that transferDDR signals fromthe core to the DQ/DQS pins.

DDR output registers

Related Information

• External Memory Interfaces in Arria V Devices

• External Memory Interfaces in Cyclone V Devices

• External Memory Interfaces in Stratix V Devices


Send Feedback

UG-01089Blocks in DQ and DQS Output Path20 2014.07.07

http://www.altera.com/literature/hb/stratix-v/stx5_51008.pdf


DQ and DQS Output Path for Arria V and Cyclone V Devices

The data output path for Arria V and Cyclone V families is similar to the output paths for Stratix V andearlier families, except for the output phase alignment registers. These registers are not available in Arria Vand Cyclone V devices and do not support leveled interfaces.

The following figure shows the DQ and DQS output path for Arria V and Cyclone V devices.

Figure 13: DQ and DQS Output Path for Arria V and Cyclone V Devices

DATAOUTDDIOOut

DATAOUT[0]

DATAOUT[1]

DATAOUT[2]

DATAOUT[3] DDIOOut

DDIOOut

CLK_HRCLK_FR

OCT from DQS LogicOE from Output Enable Path

You must connect the ALTDQ_DQS2 IP core to the ALTOCT, ALTDLL, and ALTERA_PLL IP cores toutilize their features.

Related Information

• Instantiating IP cores

ALTDQ_DQS2 PortsThe following figure shows the data strobe, data, termination control, PLL, DLL, hard FIFO, and dynamicconfiguration ports of the IP core.


Send Feedback

21DQ and DQS Output Path for Arria V and Cyclone V DevicesUG-010892014.07.07


Figure 14: ALTDQ_DQS2 Block Diagram by Port Types

-

ALTDQ_DQS2

config_clock_inconfig_data_inconfig_dqs_ena

config_dqs_io_enaconfig_update

core_clock_infr_clock_inhr_clock_in

lfifo_rdenreset_n_core_clock_in

rfifo_reset_nstrobe_ena_hr_clock_in

vfifo_reset_nwrite_strobe_clock_in

dll_delayctrl_in[]capture_strobe_ena[]output_strobe_ena[]

oct_ena_in[]parallelterminationcontrol_in[]seriesterminationcontrol_in[]

write_oe_in[]

output_strobe_n_outoutput_strobe_outextra_write_data_out[]write_data_out[]strobe_n_io

capture_strobe_out

read_data_out[]strobe_io

read_write_data_io[]

write_data_in[]config_io_ena[]

lfifo_rdata_en_full[]lfifo_rd_latency[]

vfifo_qvld[]vfifo_inc_wr_ptr[]

capture_strobe_n_inextra_write_data_in[]

read_data_in[]config_extra_io_ena[]

lfifo_reset_n

capture_strobe_in

This signal is used for QDRII. This clock, unlikeother clocks, can be held at zero during initialization,which is a requirement for QDRII. Use the coreclock signal for internal purposes. In a half-rateapplication, the core clock signal is unconnected. Ina full-rate application, you must connect the coreclock signal to the full-rate clock.

ALTDQ_DQS2 Data Strobe Ports

Table 4: ALTDQ_DQS2 Data Strobe Ports

DescriptionWidthTypePort Name

Controls the DQS enable controlblock by acting as the gating signalfor signals coming from the inputregisters (capture_strobe_in) toreach the DQS delay chain block.

This port is only supported inStratix V devices.

1Inputcapture_strobe_ena


Send Feedback

UG-01089ALTDQ_DQS2 Data Strobe Ports22 2014.07.07



Receives the negative polarityclock signal from the externaldevice. For example, a DQSn signalfrom the external memory. Thisport is available when the capturestrobe type is set to differential orcomplementary.

This port is supported in Arria V,Cyclone V, and Stratix V devices.

1Inputcapture_strobe_n_in

Receives the clock signal from theexternal device, for example, aDQS signal from the externalmemory.


1Inputcapture_strobe_in

Sends the delayed clock signal tothe core. For example, a delayedDQS signal from the DQS delaychain.


1Outputcapture_strobe_out

The gating signal for the output_strobe_out port.


2 = half-rate

1 = full-rate

Inputoutput_strobe_ena

Controls the dynamic on-chip-termination signal for all data andstrobe ports.


2 = half-rate

1 = full-rate

Inputoct_ena_in

Asynchronous reset used inQDRII-like interfaces to reset thewrite strobe.


1Inputreset_n_core_clock_in


Send Feedback

23ALTDQ_DQS2 Data Strobe PortsUG-010892014.07.07



Receives the clock signal from thecore. For example, a DQS signalfrom the core. Clocks the DDIOthat generates the output strobesignal.


1Inputwrite_strobe_clock_in

Receives the clock signal from theclock pin or the PLL to clock theDQS enable control block.

Also a half-rate signal that, aftergoing through the DQS_ENABLE_CTRL input, controls the gating ofthe input strobe.


1Inputstrobe_ena_hr_clock_in

Sends and receives the bidirec-tional clock signal.


1Bidirectionalstrobe_io

Sends and receives the negativepolarity clock signal for differen-tial or complementary strobeconfiguration.


1Bidirectionalstrobe_n_io

Sends clock signal to the externaldevice. For example, a DQS signalto the external memory.


1Outputoutput_strobe_out


Send Feedback

UG-01089ALTDQ_DQS2 Data Strobe Ports24 2014.07.07



Sends the negative polarity clocksignal to the external device (Forexample, DQSn signal to theexternal memory). This port isavailable when you set the outputstrobe type to differential orcomplementary.


1Outputoutput_strobe_n_out

ALTDQ_DQS2 Data PortsThe following table lists theALTDQ_DQS2data portswheren=number ofDQpins,m=number of additionaloutput-only DQ pins, x = 0 to (n-1), and y= 0 to (m-1).

Table 5: ALTDQ_DQS2 Data Ports

DescriptionWidth(2)

TypePort Name

Receives data signal from the core.

This port connects to the inputport of the half-rate data to single-rate data output registers block(Figure 12). In full-rate mode,only the extra_write_data_in[y] and extra_write_data_

in[m+y] ports are used.


2m = full-rate

4m = half-rate

Inputextra_write_data_in[]

Sends data to the external device.

This port connects to the outputport of the output buffer (Figure12).


mOutputextra_write_data_out[]

(2) The port width applies to full-rate mode, unless otherwise specified.


Send Feedback

25ALTDQ_DQS2 Data PortsUG-010892014.07.07


DescriptionWidth(2)

TypePort Name

Receives data from the externaldevice.

This port connects to the inputport of the input buffer locatedbetween the DQ pin and the DDRinput registers block. This is aninput-only DQ port that receivesdata from the external device(Figure 7).


nInputread_data_in[]

Sends the captured data from theexternal device to the core.

This port connects to the outputport of the DDR input registerblock (Figure 7). The read_data_out[x] port outputs the positive-edge triggered data, and the read_data_out[n+x] port outputs thenegative-edge triggered data.


2n = full-rate

4n = half-rate

Outputread_data_out[]

Receives and sends data betweenthe core and the external device.

You must assign the bidirectionalDQ port with the output termina-tion and input terminationassignments.


nBidirec-tional

read_write_data_io[]



Send Feedback

UG-01089ALTDQ_DQS2 Data Ports26 2014.07.07


DescriptionWidth(2)

TypePort Name

ReceivesDDRdata signal from thecore to be sent out to the externaldevice. For example, data to bewritten to the external memoryduring write operation.

This port connects to the inputport of the half-rate data to single-rate data output registers block(Figure 11). In full-rate mode, theIP core uses only the write_data_in[x] and write_data_in[n+x]

ports.


2n = full-rate

4n = half-rate

Inputwrite_data_in[]

Sends the DDR data signal to theexternal device. For example, datato be written to the externalmemory during write operation.

This port connects to the outputport of the output buffer locatedbetween theDDRoutput registersblock and the DQ-out pin (Figure11).


nOutputwrite_data_out[]

Receives the gating signal from thecore to control the output buffer.For example, gating control whenwriting data to the externalmemory during write operation.

This port connects to the inputport of the half-rate data to single-rate data output-enable registersblock (Figure 11). In full-ratemode, the IP core uses only thewrite_oe_in[x] port.


n = full-rate

2n = half-rate

Inputwrite_oe_in[]



Send Feedback

27ALTDQ_DQS2 Data PortsUG-010892014.07.07


To understand how these ports connect to the IOEs, refer to “I/O Elements” in theExternalMemoryInterfaces in Stratix V Devices chapter of the Stratix V Device Handbook.

Note:

ALTDQ_DQS2 Termination Control Ports

Table 6: ALTDQ_DQS2 Termination Control Ports

DescriptionWidthTypePort name

Controls the calibratedparallel termination ports ofthe input buffers.

You must connect this portto the paralleltermina-tioncontrol[15:0] port oftheALTOCT IP core. Ensurethat the termination blocklocated in the ALTOCTinstance is assigned with thetermination control blockassignment.

This port is supported inArria V, Cyclone V, andStratix V devices.

16Inputparallelterminationcontrol_in[]

Controls the calibrated seriestermination ports of theoutput buffers.

You must connect this portto the seriestermination-control[15:0] port of theALTOCT IP core. Ensurethat the termination blocklocated in the ALTOCTinstance is assigned with thetermination control blockassignment.

This port is supported inArria V, Cyclone V, andStratix V devices.

16Inputseriesterminationcontrol_in[]

Related Information

• DC and Switching Characteristics for Stratix V DevicesDescribes the dynamic OCT control in Stratix V devices.


Send Feedback

UG-01089ALTDQ_DQS2 Termination Control Ports28 2014.07.07





ALTDQ_DQS2 PLL and DLL Ports

Table 7: ALTDQ_DQS2 PLL and DLL Ports


Receives the 7-bit delay settings fromthe dll_delayctrlout port of theALTDLL instance. This 7-bit signalcontrols delay through theDQSdelaychains. Compilation error occurs ifthis port is not connected to a DLL.


7Inputdll_delayctrl_in[]

Receives the full-rate clock signal froma clock pin, or the PLL clock outputport.


1Inputfr_clock_in

Receives the half-rate clock signalfrom a clock pin, or the PLL clockoutput port.


1Inputhr_clock_in

For more information about DLL in Stratix V device, refer to “Delay-Locked Loop” in the ExternalMemory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook.

Note:

For more information about PLL in Stratix V devices, refer to “PLL Specifications” in DC andSwitching Characteristics for Stratix V Devices chapter of the Stratix V Device Handbook.

Note:


Send Feedback

29ALTDQ_DQS2 PLL and DLL PortsUG-010892014.07.07






ALTDQ_DQS2 Hard FIFO Ports

Table 8: Hard FIFO Ports

DescriptionWidthTypePorts

Data input to the latency shifterFIFO. This signal is the full readenable token generated by userlogic and is asserted for the lengthof the desired read burst. Thistoken is delayed by a variablenumber of integer cycles insidethe latency shifter FIFO and usedto feed the read enable signal ofthe read FIFO.

This port is only supported inArria V and Cyclone V devices.

2Inputlfifo_rdata_en_full

Data input to the Read FIFOReadEnable. This signal is the full readenable token generated by userlogic and is asserted for the lengthof the desired read burst.

This port is only supported inStratix V devices.

1Inputlfifo_rden

Active high reset to the latencyshifter FIFO


1Inputlfifo_reset_n

The number of cycles to delay datainputs feeding the latency shifterFIFO. A maximum of 31 cycles issupported.


5Inputlfifo_rd_latency[]


Send Feedback

UG-01089ALTDQ_DQS2 Hard FIFO Ports30 2014.07.07


DescriptionWidthTypePorts

Data input to the data valid FIFO.This signal is the full read enabletoken generated by user logic andis asserted for the length of thedesired read burst. This signal isdriven by the same user logic thatdrives the lfifo_rdata_en_fullsignal.

In general applications, you canleave this port unconnected.


Arria V andCyclone Vdevices: 2

Stratix Vdevices: 1

Inputvfifo_qvld

Increments the latencyimplemented by the data validFIFO by one cycle.


2Inputvfifo_inc_wr_ptr

Active high reset to the data validFIFO


1Inputvfifo_reset_n

Active high reset to the read FIFO.


1Inputrfifo_reset_n

The I/O and DQS configuration blocks represent a set of serial-to-parallel shift registers that dynamicallychanges the settings of various device configuration bits. The I/O and DQS configuration blocks shift a serialconfiguration data stream into the shift registers, and then load the data stream into the configurationregisters. The shift registers power-up low. Every I/O pin contains an I/O configuration block. Every DQSgroup contains a DQS configuration block and an I/O configuration block.

ALTDQ_DQS2 Dynamic Configuration PortsThe following table lists the dynamic configuration ports where n= number of DQ pins and m= number ofadditional DQ pins.


Send Feedback

31ALTDQ_DQS2 Dynamic Configuration PortsUG-010892014.07.07


Table 9: ALTDQ_DQS2 Dynamic Configuration Ports


The ALTDQ_DQS2 dynamicconfiguration interface consistsof this input port.

Receives the clock signal to clockall dynamic configuration blocks.You can connect this port to aclock pin, or the PLL clock outputport.

This is the clock signal. All otherinput signals must be treated assynchronous to this clock.

This port is supported inArria V,Cyclone V, and Stratix V devices.

1Inputconfig_clock_in


The 1-bit serial input throughwhich data is scanned into thecalibration blocks. It is commonto all configuration blocks, but itwill only be scanned into calibra-tions blocks whose enable inputis asserted.


1Inputconfig_data

An input port that controls theenable input on the DQ I/Oconfigurations. Receives the clockenable signal for the I/O configu-ration block.

Refer to Dynamic Reconfigura-tion for ALTDQ_DQS2 on page34


nInputconfig_io_ena[]


Send Feedback

UG-01089ALTDQ_DQS2 Dynamic Configuration Ports32 2014.07.07



An input port that controls theenable input on the DQS I/Oconfigurations. Receives the clockenable signal for the DQS I/Oconfiguration block.



1Inputconfig_dqs_io_ena

An input port that controls theenable input on the DQS logic.Receives the clock enable signalfor the DQS configuration block.



1Inputconfig_dqs_ena


Receives the signal to load the bitsfrom the serial-to-parallel shiftregisters to the configurationregisters.

After scanning all the bits into thedesired scan chain blocks, the bitscan be copied at once into theconfiguration register by assertingthe config_update signal forone clock cycle.


1Inputconfig_update

Receives the serial configurationdata stream that shifts into theserial-to-parallel shift registers.


1Inputconfig_data_in


Send Feedback

33ALTDQ_DQS2 Dynamic Configuration PortsUG-010892014.07.07



Receives the clock enable signalfor the additional I/O configura-tion block.


mInputconfig_extra_io_ena[]

For more information about the dynamic configuration blocks in Stratix V device, refer to “I/OConfiguration Block and DQS Configuration Block” in the External Memory Interfaces in StratixV Devices chapter of the Stratix V Device Handbook.

Note:

Dynamic Reconfiguration for ALTDQ_DQS2When static timing closure is challenging (for example, high frequency, high board trace skew, and hightiming uncertainty), dynamically reconfiguring the ALTDQ_DQS2 IP core may provide additional timingmargin. Arria V, Cyclone V, and Stratix V devices contain reconfigurable logic, allowing you to adjust thedelay of several datapaths at runtime.

The I/O configuration block and the DQS configuration block are shift registers that you can use todynamically change the settings of various device configuration bits. The shift registers are configured withthe rest of the device when the Programmer Object File (.pof). In dynamic mode, you can override the staticvalues at runtime with a scan chain. You can reconfigure the I/Os by turning on the Use dynamic configu-ration scan chains option.

The following figure shows the Use dynamic configuration scan chains option.

Figure 15: Use Dynamic Configuration Scan Chains Option

The following figure shows the dynamic reconfiguration scan chain implementation.


Send Feedback

UG-01089Dynamic Reconfiguration for ALTDQ_DQS234 2014.07.07




Figure 16: Reconfiguration Scan Chain

din

update

enable

clk

DQ0din

update

enable

clk

DQ1din

update

enable

clk

DQS

config_data

config_updateconfig_clock_in

config_io_ena[0] config_io_ena[1] config_dqs_ena

Each I/O contains a scan chain block. The DQS logic also contains its own scan chain block. You can useI/O scan chain blocks to configure DQ and DQS I/O configuration registers (for example, delay chain) andyou can use the DQS logic scan chain to configure DQS logic configuration (for example, DQS postamblephase). You can serially scan configuration bits into each scan chain block with the following operatingsequence:

The ALTDQ_DQS2 dynamic configuration interface is made of four input ports:

• config_clock_in—This is the clock signal. All other input signals must be treated as synchronous tothis clock. The typical frequency is 25 MHz.

• config_data—This is the 1-bit serial input through which data is scanned into the calibration blocks.This is common to all configuration blocks, but it will only be scanned into calibrations blocks whoseenable input is asserted. Configuration datamust be input in LSB first ordering. For example, the Stratix VI/O configuration block data must start with padtoinputregisterdelaysetting[0].

• config_enable—In a generic ALTDQ_DQS2 IP core, the following three config_enable inputs areavailable:

• config_io_ena[]—Controls the enable input on the DQ I/Os• config_dqs_io_ena[]—Controls the enable input on the DQS I/Os• config_dqs_ena[]—Controls the enable input on the DQS logic

Each of these inputs is wide to control all the scan chain blocks instantiated in the ALTDQ_DQS2IP core. In a general application, you must assert only one enable input at a time to scan thedesired data in the corresponding scan chain block. The enable input must be held high for theentire duration of the scanning process. All other inputs must be held at 0.

Note:

You must deassert the config_enable signal after the last bit of config_data to prevent furtherdata from scanning in. Then, assert the update signal whenever you are ready to copy the scannedin data to the configuration registers.

Note:

• config_update—After scanning all the bits into the desired scan chain blocks, copy them into theconfiguration register by asserting the config_update signal for one clock cycle.


Send Feedback

35Dynamic Reconfiguration for ALTDQ_DQS2UG-010892014.07.07


I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V DevicesFigure 17: I/O and DQS Delay Chains for Arria V GZ and Stratix V Devices

10

DQD1DelayChain

D1DelayChain

AB

Positive EdgeRead Data

Negative EdgeRead Data

D4DelayChain

D4DelayChain

EF

DQSDelayChain

T

DQS

T11DelayChain

T11DelayChain

R

To dqsenablePort

To dqsdisablenPort

DQSEnableControl

QS

Fromdqsenableout

Port

Clock PhaseSelect

Clock PhaseSelect (0 Degree)

Tolevelingclk

Port

Tozerophaseclk

Port

M N

X V

OutputAlignment


OutputAlignment

W U

OutputAlignment

OutputAlignment

Negative EdgeWrite Data

Positive EdgeWrite Data

W U

OutputAlignment

10

Negative EdgeWrite Data

Positive EdgeWrite Data

X V

OutputAlignment

Output EnableSignal

Clock PhaseSelect


I J

LevelingDelayChain

Clock Signalfrom Core

Clock PhaseSelect

K L

Output EnableSignal

O P

OutputAlignment

OCT ControlSignal

DQD5DelayChain

D5DelayChain

D6 OCTDelayChain

D6 OEDelayChain

D5 OCTDelayChain

D5 OEDelayChain

DQSD5DelayChain

D5DelayChain

D5 OCTDelayChain

D5 OEDelayChain

D6 OCTDelayChain

D6 OEDelayChain

C

D

G

H

D2DelayChain

D3DelayChain

-

D6DelayChain

D6DelayChain

D5 OCTDelayChain

D5 OEDelayChain

D5 OCTDelayChain

D5 OEDelayChain

Use the combination of D1, D2, D3, and D4 delay chains for calibration. Use D1, D2, and D3 to delayDQ, and D4 delay chain to delay DQS. D5 and D6 delay chains are the output delay chains.

The D2 and D3 delay chains are static input delay chains. The D6 delay chain is static output delaychain. You can only set the settings in the Quartus II Settings File (.qsf) or the Fitter sets the settingsautomatically based on the timing constraints. You cannot dynamically set the settings.

The following tables lists the I/O configuration block bit sequence, description, and settings for Arria V GZand Stratix V devices.

Table 10: I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices

DescriptionBit NameBitLegendin

Figure17

Connects to the delayctrlin port of theD1 delay chain to control the first I/Obuffer-to-input register delay chain (D1).

Sets to tune the DQ delay (read calibra-tion) for DDR applications.

For delay values, refer to the“Programmable IOEDelay” section in theStratix V Device Datasheet.

padtoinputregisterdelaysetting5..0A


Send Feedback

UG-01089I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices36 2014.07.07



DescriptionBit NameBitLegendin

Figure17

Connects to the delayctrlin port of thesecond D1 delay chain to control thesecond pad-to-input register delay chain(D1).


padtoinputregisterrisefalldelaysetting11..6B

Connects to the delayctrlin port of theD5 delay chain to control the outputregister-to-I/O buffer delay chain (D5) inthe output path and output enable paths.

This delay is for write calibration forDDRapplication.


outputdelaysetting117..12C

Connects to the delayctrlin port of thesecond D5 delay chain to control theoutput register-to-I/O buffer delay chain(secondD5) in the output path and outputenable paths.

This delay is for write calibration forDDRapplication.


outputdelaysetting223..18D

Unconfigurable bits.

Always set bits to its default value.

inputclkndelaysetting

inputclkdelaysetting

dutycycledelaymode

dutycycledelaysetting

39..24—

Table 11: I/O Configuration Block Bit Value for Arria V GZ and Stratix V Devices

Inc. ValueMax. ValueMin.Value

Default Value(Binary)

Bit Name/

Bit

Bit

12.5 ps787.5 ps +intrinsicdelay

intrinsicdelay

000000padtoinputregisterdelaysetting5..0


Send Feedback

37I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V DevicesUG-010892014.07.07





Inc. ValueMax. ValueMin.Value

Default Value(Binary)

Bit Name/

Bit

Bit


intrinsicdelay

000000padtoinputregisterrisefalldelaysetting11..6


intrinsicdelay

000000outputdelaysetting117..12


intrinsicdelay

000000outputdelaysetting223..18

———0000000000000000inputclkndelaysetting

inputclkdelaysetting

dutycycledelaymode

dutycycledelaysetting

39..24

Related InformationStratix V Device Datasheet

DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V DevicesThe following tables lists the DQS configuration block bit sequence, description, and settings for Arria VGZ and Stratix V devices.

Table 12: DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices

DescriptionBit NameBitLegend in I/O Configura-tion Block Bit Sequence

for Arria V GZ andStratix V Devices on

page 36

Connects to the delayctrlin port ofthe first D4 delay chain.

Controls the first D4 delay chainin DQS delay chain path (after theDQS delay chain). This is the delaytuning of the DQS signal feedinginto the DQS bus.

For delay values, refer to the“Programmable IOE Delay”section in the Stratix V DeviceDatasheet.

dqsbusoutdelaysetting5..0E


Send Feedback

UG-01089DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices38 2014.07.07







page 36

Connects to the delayctrlin port ofthe second D4 delay chain.

Controls the second D4 delaychain in DQS delay chain path(after the first D4 delay chain).

This is the delay tuning of theDQSsignal feeding into the DQS bus.


dqsbusoutdelaysetting211..6F

Connects to the delayctrlin port ofthe D5 OCT delay chain.

Controls the dynamicOCToutputregister-to-I/O buffer delay chain(D5).


octdelaysetting117..12G

Connects to the delayctrlin portof the secondD5OCTdelay chain.

Controls the dynamicOCToutputregister-to-I/O buffer delay chain(second D5).


octdelaysetting223..18H



addrphasesetting

addrpowerdown

addrphaseinvert

27..24—

Connects to the phasectrlin portof the clock phase select (in theDQS output path) to selectbetween phase shifts of 0°, 45°, 90°,and 135°.

Use this bit to level the DQS writeoutput.

dqsoutputphasesetting29..28I


Send Feedback

39DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V DevicesUG-010892014.07.07










page 36



dqsoutputpowerdown30—

Connects to the phaseinvertctrlport of the clock phase select (inthe DQS output path) to selectbetween the non-inverted andinverted output.

This setting allows the phaseoutput from the delay chain to beinverted to gain additional phases.

dqsoutputphaseinvert31J

Connects to the phasectrlin portof the clock phase select (in theDQoutput path) to select betweenphase shifts of 0°, 45°, 90°, and135°.

DQ leveling clock select. nUse thisbit to level the DQ write output.

dqoutputphasesetting33..32K



dqoutputpowerdown35..34—

Connects to the phaseinvertctrlport of the clock phase select (inthe DQ output path) to selectbetween the non-inverted andinverted output.


dqoutputphaseinvert36L



resyncinputphasesetting

resyncinputpowerdown

resyncinputphaseinvert

40..37—


Send Feedback





page 36

Connects to the phasectrlin portof the clock phase select (for theDQS enable control block) to selectbetween phase shifts of 0°, 45°, 90°,and 135°.

Use this clock phase select blockto level the postamble (dqsenableinsignal at the DQS enable controlblock).

postamblephasesetting42..41M



postamblepowerdown44..43—

Connects to the phaseinvertctrlport of the clock phase select (forthe DQS enable control block) toselect between the non-invertedand inverted output.

Use this clock phase select blockto level the postamble (dqsenableinsignal at the DQS enable controlblock).


postamblephaseinvert45N


Send Feedback





page 36



dqs2xoutputphasesetting

n dqs2xoutputpowerdown

dqs2xoutputphaseinvert

dq2xoutputphasesetting

dq2xoutputpowerdown

dq2xoutputphaseinvert

ck2xoutputphasesetting

ck2xoutputpowerdown

ck2xoutputphaseinvert

dqoutputzerophasesetting

postamblezerophasesetting

postamblepowerdown

dividerioehratephaseinvert

dividerphaseinvert

65..46—

Connects to the enaoutputcy-cledelay port of the outputalignment block (in the dynamicOCT control path) to allowadditional registers to be used.

Use this bit to adjust the phase ofthe write-leveled OCT or outputdata signal.

enaoctcycledelaysetting68..66O

Connects to the enaphasetrans-ferreg port of the output alignmentblock (in the dynamicOCTcontrolpath) to allow an additionalnegative edge-triggered register tobe added to the OCT, output data,or output enable path to satisfy thesetup or hold time requirement forthe phase transfer.

enaoctphasetransferreg69P


Send Feedback





page 36

Connects to the delayctrlin port ofthe T11 delay chain (locatedbetween the dqsenableout port ofthe DQS enable control block andthe dqsdisablen port of the DQSdelay chain).

This is to align post-amble signalin terms ofDQS signal by selectingdifferent delays.

dqsdisablendelaysetting77..70Q

Connects to the delayctrlin port ofthe T11 delay chain (locatedbetween the dqsenableout port ofthe DQS enable control block andthe dqsenable port of the DQSdelay chain).

This is to align post-amble signalin terms ofDQS signal by selectingdifferent delays.

dqsenabledelaysetting85..78R

Connects to the enaphasetrans-ferreg port of the DQS enablecontrol block to allow anadditional negative edge-triggeredregister to be added to the DQSenable control path to satisfy thesetup or hold time requirement forthe phase transfer.

enadqsenablephasetransferreg86S

Connects to the phasectrlin portof the DQS delay chain block.

To control the phase selection forthe DQS delay chain.

The frequency range that thisworks at is 300 MHz to 800 MHz.

dqsinputphasesetting88..87T

Connects to the enaphasetrans-ferreg port of the output alignmentblock (in theDQSoutput path andOE path) to allow an additionalnegative edge-triggered register tobe used.

enadqsphasetransferreg89U


Send Feedback





page 36

Connects to the enaphasetrans-ferreg port of the output alignmentblock (in the DQ output path andOE path) to allow an additionalnegative edge-triggered register tobe added to the output data oroutput enable path to satisfy thesetup or hold time requirement forthe phase transfer.

enaoutputphasetransferreg90V

Connects to the enaoutputcy-cledelay port of the outputalignment block (in the DQSoutput path and OE path) to allowadditional registers to be enabledin the output alignment block ofthe output data or output enablepath of a DQS I/O.

This is normally used to adjust thephase of the write-leveled OCT oroutput data signal.

enadqscycledelaysetting93..91W

Connects to the enaoutputcy-cledelay port of the outputalignment block (in theDQoutputpath and OE path) to allowadditional registers to be enabledin the output alignment block ofthe output data or output enablepath of a DQ I/O.

Use this bit to adjust the phase ofthe write-leveled OCT or outputdata signal.

enaoutputcycledelaysetting96..94X



enainputcycledelaysetting

enainputphasetransferreg

100..97—

Table 13: DQS Configuration Block Bit Value for Arria V GZ and Stratix V Device

Inc. UnitMax ValueMinValue

Default Value (Binary)Bit NameBit


intrinsicdelay

0dqsbusoutdelaysetting5..0


Send Feedback






intrinsicdelay

0dqsbusoutdelaysetting211..6


intrinsicdelay

0octdelaysetting117..12


intrinsicdelay

0octdelaysetting223..18

———100addrphasesetting

addrpowerdown

addrphaseinvert

27..24

00 = 0°

01 = 45°

10 = 90°

11 = 135°

0dqsoutputphasesetting29..28

—1dqsoutputpowerdown30

0 = bypass

1 = enable

0dqsoutputphaseinvert31

00 = 0°

01 = 45°

10 = 90°

11 = 135°

0dqoutputphasesetting33..32

—10dqoutputpowerdown35..34

0 = bypass

1 = enable

0dqoutputphaseinvert36

—100resyncinputphasesetting

resyncinputpowerdown

resyncinputphaseinvert

40..37

00 = 0°

01 = 45°

10 = 90°

11 = 135°

0postamblephasesetting42..41


Send Feedback





—10postamblepowerdown44..43

0 = bypass

1 = enable

0postamblephaseinvert45

—0010_0000_1000_1000_0100

dqs2xoutputphasesetting

dqs2xoutputpowerdown

dqs2xoutputphaseinvert

dq2xoutputphasesetting

dq2xoutputpowerdown

dq2xoutputphaseinvert

ck2xoutputphasesetting

ck2xoutputpowerdown

ck2xoutputphaseinvert

dqoutputzerophasesetting

postamblezerophasesetting

postamblepowerdown

dividerioehratephaseinvert

dividerphaseinvert

65..46

000: Not supported

001: Not supported

010: No delay

011: 1 cycle delay

100: 2 cycle delay

101: 3 cycle delay

110: Not supported

111: Not supported

10enaoctcycledelaysetting68..66

0 = bypass

1 = enable

0enaoctphasetransferreg69

12.5 ps3.2 ns +intrinsicdelay

intrinsicdelay

0dqsdisablendelaysetting77..70

12.5 ps3.2 ns +intrinsicdelay

intrinsicdelay

0dqsenabledelaysetting85..78


Send Feedback





0 = bypass

1 = enable

0enadqsenablephasetrans-ferreg

86

00 = 0°

01 = 45°

10 = 90°

11 = 135°

0dqsinputphasesetting88..87

0 = bypass

1 = enable

0enadqsphasetransferreg89

0 = bypass

1 = enable

0enaoutputphasetransferreg90

000: Not supported

001: Not supported

010: No delay

011: 1 cycle delay

100: 2 cycle delay

101: 3 cycle delay

110: Not supported

111: Not supported

10enadqscycledelaysetting93..91

000: Not supported

001: Not supported

010: No delay

011: 1 cycle delay

100: 2 cycle delay

101: 3 cycle delay

110: Not supported

111: Not supported

10enaoutputcycledelaysetting96..94

—0enainputcycledelaysetting

enainputphasetransferreg

100..97

Related Information

• Stratix V Device Datasheet


Send Feedback




I/O Configuration Block Bit Sequence for Arria V and Cyclone V DevicesFigure 18: I/O and DQS Delay Chains for Arria V and Cyclone V Devices

4

Open Drain

ProgrammablePull-Up Resistor

4

PRND Q

PRND Q

PRND Q

PRND Q

PRND Q

clkout

D5 Delay

PRND Q

PRND Q

D5_OCT

2

FromCore

OE fromCore

Write Datafrom Core

To Core

To Core

Read Datato Core

ReadFIFO

D3_1Delay

Half DataRate Block

Half DataRate Block

DQS Logic Block

Dynamic OCT Control (2)

VCCIO

D5 Delay

Output Buffer

Input Buffer

ProgrammableCurrent Strengthand Slew Rate Control From OCT

CalibrationBlock

On-ChipTermination

Bus Hold Circuit

D3_0Delay

D1Delay

Output Register

Output Register

OE Register

OE Register

Input Register

Input Register Input Register

DQ

DQSDelayChain

D4DelayChain

LevelingDelayChain

I

K

G

H

N M L

DMode

rdclk

A

CF

B

J

E Read FIFOClock Select

DQS

T11GatingDelayChain

T11UngatingDelayChain

DQSEnableControl

LatencyShifter FIFO

Data ValidFIFOClock

PhaseSelect

Clock Signalfrom Core

Clock Select

The following table lists the I/O configuration block bit sequence, description, and settings for Arria V andCyclone V devices.


Send Feedback

UG-01089I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices48 2014.07.07


Table 14: I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices

DescriptionExternal Bit NameBitLegend in Figure 18

Connects to the delayctrlinport of the D1 delay chain.

Controls the I/O buffer-to-input register delay chain (D1).

Tunes the DQ delay (readcalibration) for DDR applica-tions.

For delay values, refer to the“Programmable IOE Delay”sections in theArriaVDeviceDatasheet and the CycloneVDevice Datasheet,respectively.

padtoinputregisterdelaysetting4..0A


Controls the output register-to-I/O buffer delay chain (D5)in the output enable paths.This delay is used for writecalibration for DDR applica-tion.


outputenabledelaysetting9..5B


Controls the output register-to-IO Buffer delay chain (D5)in the output path paths. Thisdelay is used for write calibra-tion for DDR application.


outputregdelaysetting14..10C


Send Feedback

49I/O Configuration Block Bit Sequence for Arria V and Cyclone V DevicesUG-010892014.07.07

http://www.altera.com/literature/hb/arria-v/av_51002.pdf


http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf











DescriptionExternal Bit NameBitLegend in Figure 18

Connects to the dynfifomodeport of input register readFIFO block. The read FIFOcan be configured as a readFIFO or a Unified SerDesBlock.

readfifomode17..15D

Connects to the clksel port ofthe read FIFO clock selectblock. This controls the readFIFORead clock source Select.

readfiforeadclockselect19..18E

Sets the multiplexer in theoutput enable and output datapath logic to dynamicallybypass the half-rate to full-rateDDIO. Used only with thehard PHY.

outputhalfratebypass20F

Unconfigurable bits. Alwaysset bits to its default value.

Not mapped to any port24..21—

Table 15: I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices

Inc. ValueMax. ValueMin. ValueDefaultValue

(Binary)

Bit NameBit

25 ps775 ps + intrinsicdelay

intrinsic delay0padtoinputregisterdelayset-ting

4..0


intrinsic delay0outputenabledelaysetting9..5


intrinsic delay0outputregdelaysetting14..10

000: Half-rate Read FIFO Mode

001: Full-rate Read FIFO Mode

010: Deserializer Bit Slip Mode

011: Deserializer with Input from Bit Slip

100: Deserializer with Input from I/O

101: Serializer mode

110: Not supported

111: Not supported

0readfifomode17..15


Send Feedback

UG-01089I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices50 2014.07.07



(Binary)

Bit NameBit

00: Select Core CLKIN1

01: Select DQS_CLK (PHY_CLK)

10: Select SEQ_HR_CLK (PHY_CLK)

11: Select VCC (Disabled)

0readfiforeadclockselect19..18

0: Engage Half-Rate Register

1: Bypass Half-Rate Register

0outputhalfratebypass20

———0Not mapped to any port24..21

Related Information

• Arria V Device Datasheet

• Cyclone V Device Datasheet

DQS Configuration Block Bit Sequence for Arria V and Cyclone V DevicesThe following tables lists the DQS configuration block bit sequence, description, and settings for Arria Vand Cyclone V devices.

Table 16: DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices

DescriptionBit NameBitLegend in Figure 18

Connects to the delayctrlin portof postamble T11 delay chain(ungated). Aligns the postamblesignal in terms of DQS signal byselecting different delays.

dqsenableungatingdelaysetting4..0G

Connects to the delayctrlin portof the postamble T11 delay chain(gated). Aligns the postamblesignal in terms of DQS signal byselecting different delays.

dqsenablegatingdelaysetting9..5H

Connects to the enaphasetrans-ferreg port of the DQS EnableControl block to allow anadditional negative edge-triggered register to be added tothe DQS enable control path tosatisfy the setup or hold timerequirement for the phasetransfer.

enadqsenablephasetransferreg10I


Send Feedback

51DQS Configuration Block Bit Sequence for Arria V and Cyclone V DevicesUG-010892014.07.07




DescriptionBit NameBitLegend in Figure 18

Connects to the delayctrlin portof the D5 delay chain.

Controls the dynamic OCToutput register-to-I/O bufferdelay chain (D5).

For delay values, refer to the“Programmable IOE Delay”sections in the Arria V DeviceDatasheet and the Cyclone VDevice Datasheet, respectively.

octdelaysetting15..11J

Sets the multiplexers in the DQSenable logic, OCT logic, andFIFO control logic to dynamicallyswitch from half-rate to full-rateconfiguration.

dqshalfratebypass16K

Connects to the delayctrlin portof the read DQS D4 delay chain.Controls the delay tuning of theDQS signal feeding into the DQSbus.

dqsbusoutdelaysetting21..17L

Connects to the phaseinvertctrlport of the clock phase selectblock to select between the non-inverted and inverted output.This clock phase select block isused to level the postamble clock(in leveling multiplexer). Thissetting allows the phase outputfrom the delay chain to beinverted to gain additionalphases.

postamblephaseinvert22M

Connects to the phasectrlin portof the clock phase select block toselect between phase shifts of 0°,45°, 90°, and 135°. This particularclock phase select block is used tolevel the postamble clock (inleveling multiplexer).

postamblephasesetting24..23N

Unconfigurable bits. Always setbits to its default value.

Not mapped to any port29..25—


Send Feedback

UG-01089DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices52 2014.07.07






Table 17: DQS Configuration Block Bit Value for Arria V and Cyclone V Devices


(Binary)

External Bit NameBit

25 ps775 ps +intrinsic delay

intrinsic delay0dqsenableungatingdelayset-ting

4..0


intrinsic delay0dqsenablegatingdelaysetting9..5

0: Disable Neg-Edge Register

1: Enable Neg-Edge Register

0enadqsenablephasetrans-ferreg

10


intrinsic delay0octdelaysetting15..11

0: Engage Half-Rate Register

1: Bypass Half-Rate Register

0dqshalfratebypass16


intrinsic delay0dqsbusoutdelaysetting21..17

0 = Non-invert

1 = Invert

0postamblephaseinvert22

00 = 0°

01 = 45°

10 = 90°

11 = 135°

0postamblephasesetting24..23

—0Not mapped to any port29..25

Related Information

• Arria V Device Datasheet

• Cyclone V Device Datasheet


Send Feedback

53DQS Configuration Block Bit Sequence for Arria V and Cyclone V DevicesUG-010892014.07.07




Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2

Figure 19: Example Usage of Dynamic Reconfiguration

When the scanning process begins, assert each config_io_enabit for 40 cycles to enable the 40 bits config_data (based on theI/O configuration block bits) for each DQ I/O. Each DQS groupconsists of a configuration block per one DQ pin. Theconfig_ena_io is eight bit because the DQ pin width is set to 8.

Assert config_dqs_io_ena for 40 cycles toshift the 40 bits config_data (based on I/Oconfiguration block bits) for the DQS pin.

Assert config_dqs_ena for 101 cycles to shiftthe 101 bits config_data (based on DQSconfiguration block bits) for the DQS logic.

Assert config_update forone cycle. The scan chainprocess is complete.

config_ena_io[7:0]config_dqs_io_ena[0:0]

config_dqs_ena[0:0]config_data

config_update

01 02 04 08 10 20 80 001 0

010

0

40

The bitstream for the config_datasignal is LSB first (from LSB toMSB).

Stratix V Design ExampleThis section describes how to instantiate the ALTDQ_DQS2, ALTERA_PLL, ALTDLL, ALT_OCT IP coresusing the Top_SV_13.0sp1.qar design example.

Instantiating ALTDQ_DQS2 IP CoreTo instantiate the ALTDQ_DQS2 IP core, perform the following steps:

1. In the Quartus II software, open theTop_SV_13.0sp1.qar and restore the archived file into your workingdirectory.



4. On the Parameter Settings tab, on the General page, specify the parameters as shown in the followingfigure. These parameters configure the general settings for the ALTDQD_DQS2 instance.


Send Feedback

UG-01089Example Usage of Dynamic Reconfiguration for ALTDQ_DQS254 2014.07.07


Figure 20: ALTDQ_DQS2 Parameter Settings for Stratix V Devices

5. Click Finish.

Because the memory frequency is less than the DLL minimum frequency, the DLL needs to be driven bya 2 x frequency (2 x 250 MHz = 500 MHz).

Because the DLL is driven at doubled frequency, the effective DQS delay is only half of the memoryfrequency. In this case, to achieve 90 degree shift for memory frequency, the closest setting is 135 degreein the ALTDQ_DQS2 GUI (which is effectively only 135 degree of 500 MHz, or 67.5 degree of 250 MHz).

The settings in Figure 20 enables free-running read and write clock. DQS enable block is notneeded.

Note:

If your design requires bidirectional strobe, turn on the Make capture strobe bidirectionaloption. The timing of the capture strobe enables the DQS enable block to know the arrival of the

Note:

capture strobe which requires round-trip delay information. However, the use of the DQS enableblock requires runtime calibration which is not a feature of the ALTDQ_DQS2 IP core.

Instantiating the ALTDLL IP CoreTo instantiate the ALTDLL IP core, follow these steps:



3. On the Parameter Settings tab, on the General page, specify the parameters as shown in the followingfigure.


Send Feedback

55Instantiating the ALTDLL IP CoreUG-010892014.07.07


Figure 21: ALTDLL Parameter Settings Tab

4. Click Finish.

Instantiating ALT_OCT IP Core1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.

The parameter editor appears.2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in

your project. If prompted, also specify the target Altera device family and output file HDL preference.Click OK.


Figure 22: ALT_OCT Parameter Settings Tab

4. Click Finish.

Instantiating Altera PLL1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.



3. On the General tab, specify the parameters as shown in the following figures.


Send Feedback

UG-01089Instantiating ALT_OCT IP Core56 2014.07.07


Figure 23: Altera PLL Parameter Settings for Stratix V Devices

4. Click Finish.

Altera PLL Clock Settings Information

The following table lists the clock settings Information. You can either merge the similar frequency countersin their design, or the Fitter performs the merging automatically.

Table 18: Altera PLL Clock Settings Information

DescriptionClock

500 MHz, used as 2x frequency if necessary.outclk_0

250 MHz, used as strobe/dqs clock.outclk_1

250 MHz, 270 degrees phase shifted. Used as data/dq clock.outclk_2

125 MHz, used as half-rate clock.outclk_3

500MHz, used to drive theALTDLL IP core. Theminimum frequency for theALTDLLIP core for Stratix V devices is 300 MHz.

outclk_4

250 MHz, used to drive the full rate core clock.outclk_5

125 MHz, used to drive the half rate core clock.outclk_6

25 MHz, used as config_clk.outclk_7

lf thememory frequency is less than theALTDLL IP coreminimum frequency, then drive theALTDLLIP core at 2x or 4x of the memory frequency. The DQS phase settings decrease as well.

Note:

Setting Up NativeLink and Simulation SettingsTo set up the NativeLink and simulation settings, follow these steps:

1. In the Quartus II software, on the Tools menu, select Options.2. In the Options dialog box, under Category list, expand General and then select EDA Tool Options.3. In the EDA Tools Options window, follow the settings as shown in the following figure:


Send Feedback

57Altera PLL Clock Settings InformationUG-010892014.07.07


Figure 24: EDA Tools Options Dialog Box

4. In the Quartus II software, on the Assignments menu, click Settings.5. In the Settings dialog box, under the Category list, expand EDA Tool Settings. Click Simulation.6. Enter the necessary NativeLink settings. The following figure shows an example settings. In this design

example, a testbench (tb.v) is provided together with other supporting files.

Figure 25: Simulation Dialog Box

Figure 26: Test Benches Dialog Box


Send Feedback

UG-01089Setting Up NativeLink and Simulation Settings58 2014.07.07


Figure 27: Edit Test Bench Settings Dialog Box

7. Run Analysis and Synthesis.8. To view the simulation results, on the Tools menu, select Run Simulation Tool and then click RTL

Simulation.For a successful simulation, you may need to manually change alterapll.vo to alterapll.v in the auto-generated top_run_msim_rtl_verilog.do file.

9. Before running the Fitter, ensure that the following settings are done in the Assignment Editor.

• I/O Standard• Input Termination• Output Termination• DQ Group• Location assignment for strobe pin—this helps the Fitter to fit the related DQ pins in the appropriate

l/O sub-banks. You can then back-annotate the locations if desired.

The following figures show a setting example in the Assignment Editor and the Pin Planner result:

Figure 28: Setting Example in Assignment Editor


Send Feedback

59Setting Up NativeLink and Simulation SettingsUG-010892014.07.07


Figure 29: Pin Planner

10. Run the Fitter, Timing Analysis, and Assembler. An SDC example (top.sdc) is included in the exampledesign.

Related Information

• Understanding Simulation Results—Stratix V Design Example on page 60

Understanding Simulation Results—Stratix V Design Exampleln the Stratix V design example, a generic testbench is used to test the write and read operations in theALTDQ_DQS2 IP core. The following table lists the components in the testbench.

Table 19: Testbench Components

DescriptionComponent

• Acts as a host controller, sends read/write commands to the ALTDQ_DQS2 IP core.

• Compares data read back from a DQS agent to what it should be.• Has a side channel (side reads/writes) communicating directly with the

DQS agent, bypassing the ALTDQ_DQS2 IP core. Use the data in the sidereads/writes to compare with the data sent to or received from theALTDQ_DQS2 IP core.

DQS Driver

• Acts as an external memory device.• Has a side channel (side reads/writes) communicating directly with the

DQS driver, bypassing the ALTDQ_DQS2 IP core. Use the data in theside reads/writes to compare with the data sent to or received from theALTDQ_DQS2 IP core.

DQS Agent

Random data is generated and used in the testbench. You may see other data values if you are usinga different operating system and seeds.

Note:

The following figure shows the waveform for the testbench generated after executing thetop_run_msim_rtl_verilog.do file.


Send Feedback

UG-01089Understanding Simulation Results—Stratix V Design Example60 2014.07.07


Figure 30: Waveform Example

All ports are in resetmode until the reset_n signal is asserted at 70 ns. Then, the core_clk_fr and core_clk_hrclocks start to toggle. The agent_reset_n_to_dqs signal is asserted at 91 ns to reset the ALTDQ_DQS2 IPcore, which is located in top_inst.

Dynamic Configuration

At 100 ns, there is a high pulse on the beginscan signal. When the agent_output_enable signal is pulledlow, some internal calibration is being carried out. Dynamic configuration is themain feature used. At 18.675us, the enable_driver signal is asserted to specify that the internal calibration is completed. The DQS driver,which acts as the host controller, performs a read/write operation.

For RTL related to dynamic configuration operations in this design example, refer toconfig_controller.sv file.

Note:

To help you achieve static timing closure, the dynamic configuration feature allows you to override the staticvalues at runtime with a scan chain. Each l/O and the DQS logic contains its own scan chain block (shiftregisters). This section shows you how to serially scan configuration bits into each scan chain block, between100 ns and 18.675 us.

The following figure shows thewaveform for the dynamic configuration simulation generated after executingtopwave.do (located in the simulation/modelsim folder), in between the high pulses of beginscan and


Send Feedback

61Dynamic ConfigurationUG-010892014.07.07


scandone. There is a pulse between 18.035 us and 18.075 us on the config_data_in signal. This is becausethe dqsinputphasesetting of the DQS configuration is set to 2'b01 in the testbench.

For the results of this settings, refer to DQS Delay Chain on page 64.Note:

Figure 31: Dynamic Configuration Waveform

Because the enable_driver signal is asserted at 18.675 us, the DQS driver performs the following operations:

• DQS Write Operation on page 62• Side Read Operation on page 63• Side Write Operation on page 63• DQS Read Operation on page 64

The driver_clk clock is running at the same rate as the core).Note:

Related Information

• Dynamic Reconfiguration for ALTDQ_DQS2 on page 34

DQS Write Operation

The driver asserting the dqs_enable signal at 18.803 µs begins the write operation. The dqs_write signalis asserted at 18.811 µs. The write_oe_in signal of the ALTDQ_DQS2 IP core is set to high and is ready tosend data to the DQS agent. Data are written to the dqs_writedata of the DQS driver and then reflected inthe dq signal of theALTDQ_DQS2 IP core. The datawritten out from theDQSdriver are stored in check/i/o.The dqs_write signal deasserts at 18.851 µs. The dqs_enable deasserts at 18.859 µs. Outgoing data fromthe ALTDQ_DQS2 (dq) is center aligned to the write clock (dqs_ios_to_agent).

The following figure shows the DQS write operation waveform.

Figure 32: DQS Write Operation Waveform

Before and after the DQS write operation, the dq signal is in Hi-Z mode to filter any unwanted glitchon the bidirectional port.

Note:


Send Feedback

UG-01089DQS Write Operation62 2014.07.07


The following figure shows the waveform after executing the topwave.do file. The write_oe_in signal isheld high throughout the five sets of valid write_data_in between 18.811 µs and 18.851 µs. Centre alignedoutput data appears on read_write_data_io between 18.822 µs and 18.86 2µs. The output_strobe_outis a free running clock while the read_write_data_io is driven at Hi-Z when there is no data transaction.

Figure 33: DQS Write Operation Waveform After Executing the topwave.do File

Side Read Operation

The side read operation is performed between 18.923 µs and 18.963 µs. The DQS agent sends data to theDQS driver with the side_readdata signal. Data validation is carried out in parallel, by comparing theside_readdata signal against the content of the check/i/o (data which was written out during the DQSwrite operation). If there is a mismatch, the software generates an error message.

The following figure shows the waveform for the side read operation.

Figure 34: Side Read Operation Waveform

Side Write Operation

The side write operation begins between 19.011 µs and 19.067 µs. The data written out from the DQS driveris also stored in check/i/o.

The following figure shows the waveform for the side write operation.

Figure 35: Side Write Operation Waveform

The incoming data at dq is edge-aligned to the dqs_agent_to_ios.Note:


Send Feedback

63Side Read OperationUG-010892014.07.07


DQS Read Operation

Between 19.227 µs and 19.275 µs when the dqs_readdata_valid signal is held high, data validation is doneby comparing data received by the ALTDQ_DQS2 core (read_data_out) against the content in thecheck/i/o.

ln Stratix V devices, you can choose to enable or disable the hard read FlFO. The read FlFO is in every inputdata paths. The read FlFO handles full-rate and half-rate conversion only. This example design uses the hardread FlFO. The testbench determines the timing to assert the write enable and read enable ports via thev/i/o_qvld and l/i/o_rden. ln an actual application, you must design your own logic to do so.

The DQS driver begins the DQS read operation when the dqs_read signal is asserted at 19.139 µs, for theentire length of the desired read burst, which in this case is 12 full-rate cycles. The DQS agent also receivethe read command, and is ready to send out data. After a specific latency, the agent_output_enable signalis asserted beginning from 19.167 µs to 19.219 µs. During this period, the DQS agent drives clock and datalines of the external memory interface. The oct_enable signal is asserted between 19.155 µs and 19.211 µs.The incoming data (dq) is edge-aligned to the clock (dqs_agent_to_ios).

Figure 36: DQS Read Operation Waveform

DQS Delay Chain

Because the DQS enable block is not applicable for this example design, the dqsenable signal is held at Hi-Z at all time. The dqsbusout signal is the delayed dqsin signal that drives to the dedicatedDQS clock networkto clock theDQ capture registers, so that data are captured at the center of the eye. If you disable the dynamicconfiguration feature, you should see a 67.5° phase shift (or 735 ps) between dqsin and dqsbusout, asexpected due to the settings in Figure 20. The following figure shows that the phasectrlin signal is held atHi-Z.

Figure 37: DQS Delay Chain Waveform

However, when you enable the dynamic configuration feature, phasectrlin (which is set via thedqsinputphasesetting port of the DQS configuration) determines the phase applied to the dqsbusoutoutput.

Observe the following waveform. Before dynamic configuration, phasectrlinwas set to 2'b00 and the shiftbetween dqsin and dqsbusout is about 245 ps (should be 0 ps). Meanwhile after performing dynamicconfiguration, phasectrlin was set to 2'b11 and the shift between dqsin and dqsbusout is about 980 ps(should be 735 ps, which is 67.5°). This is consistent with the settings in Figure 20 .


Send Feedback

UG-01089DQS Read Operation64 2014.07.07


There is a simulation error for the phasectrlin. The current incorrect modeled setting is as follows:00 = 45°, 01 = 90°, 10 = 135°, 11 = 180°. It is scheduled to be fixed at QII 14.0, to be modeled correctlyas: 00 = 0°, 01 = 45°, 10 = 90°, 11 = 135°

Note:


Hard Read FIFO

As seen in thewaveformbelow, the incoming read data is available on read_write_data_io between 19.171µs and 19.219 µs. The capture DDlO block captures input data (DQ) on the rising and falling edges of thecapture clock (DQS). For Stratix V devices, the capture DDlO block feeds the hard read FlFO or bypassesthe hard read FlFO and goes directly to the core. The data transfer from the capture DDlO block and thenext stage is referred to as zero-cycle transfer. This means that the transfer must happen on the same clockedge.

To ensure correct timing analysis, use the set_multicycle SDC command.Note:

This design example uses a hard read FIFO. When the first data is available at 19.174 µs, the v/i/o_qvld isasserted. This signal passes through the write_enable_ctrl of the DDlO OUT before driving the readenable port of the read FIFO. As the write enable signal of the read FlFO block is asserted, data is written tothe read FlFO between 19.174 µs and 19.222 µs . The l/i/o_rden, which is connected to the read enableport of the read FlFO block through a fifo_enable block, is then asserted between 19.219 µs and 19.267 µs.Read data is available in the core between 19.179 µs and 19.275 µs on read_data_out. You may furtheroptimize the timing to read the read FlFO by adjusting the l/i/o_rden to create enough space between theread and write pointers in the read FlFO to maximize the throughput.


Send Feedback

65Hard Read FIFOUG-010892014.07.07


Figure 39:

Hardened in ALTDQ_DQS2 Megafunction.ReadFIFO

DOUT DIN

REN WREN

LatencyShifterFIFO

DataValidFIFO



Implement as Soft FIFOs

Figure 40:

The write enable (we) and read enable (re) signals of the hard read FIFO are different from the wrreqand rdreq signals of the DCFIFO. In DCFIFO, the data is only available at the FIFO output ports

Note:

when the rdreq is asserted. For the hard read FIFO, the we signal controls when to advance the writeaddress counter, while the re signal controls when to advance the readaddress counter. When theread/write address pointers are the same, write data appears at the read port as soon as the writeoperation is completed. When the re signal is asserted, it will advance to the next read address andthen only the second written data is available at the FIFO output port.


Send Feedback

UG-01089Hard Read FIFO66 2014.07.07


Simulation Results

The following figure shows the simulation results in the message panel. lf the simulation failed, it is due tothe data sent/received at the ALTDQ_DQS2 is not the same as the expected ones.

Figure 41: Simulation Results

SDC Walkthrough

To create a new .sdc, follow these steps:

1. Constrain the clocks coming into the FPGA with a create_clock command. The following commandcreates the base clock for the input clock port driving the PLL:create_clock -name refclk -period 10.000 [get_ports {refclk}]

2. Create the generated clocks for the PLL with the following command:derive_pll_clocks

3. Constraint the virtual input clock (for incoming DQS strobe) and the capture_strobe_in port. ln thisexample design, it is based on a 250 MHz input clock, with a 50% duty cycle, where the first rising edgeoccurs at 0 ns.

create_clock -name virtual_dqs_in -period 4.000

create_clock -name dqs_in -period 4.000[get_ports {capture_strobe_in}]

4. lncoming data is edge aligned to the DQS strobe, and minimum and maximum input delay is assumedto be ± 0.3ns in this design example. Youmustmodify constraints to reflect the data and clock relationshipin the system.Use the -add option to add the user-defined delay constraint instead of overriding previousconstraints.set_input_delay -clock {virtual_dqs_in} -max -add_delay 0.300 [get_ports

{read_write_data_io[*]}]

set_input_delay -clock {virtual_dqs_in} -min -add_delay -0.300

[get_ports{read_write_data_io[*]}]

set_input_delay -clock {virtual_dqs_in} -clock_fall -max -add_delay 0.300 [get_ports


set_input_delay -clock {virtual_dqs_in} -clock_fall -min -add_delay -0.300 [get_ports



Send Feedback

67Simulation ResultsUG-010892014.07.07


Figure 42:

Analyzing Same Edge Transfer

The following set_false_path commands ensure that you are analyzing only the same edge transfers, byremoving the opposite edge transfers.

These assignments are optional.Note:

Example 2: set_false_path Commands

set_false_path -setup -rise_from [get_clocks {virtual_dqs_in}] -fall_to [get_clocks

{dqs_in}]

set_false_path -setup -fall_from [get_clocks {virtual_dqs_in}] -rise_to [get_clocks

{dqs_in}]

set_false_path -hold -rise_from [get_clocks {virtual_dqs_in}] -rise_to [get_clocks

{dqs_in}]

set_false_path -hold -fall_from [get_clocks {virtual_dqs_in}] -fall_to [get_clocks

{dqs_in}]

The default setup relationship is to latch data on the next edge. The following set_multicycles_pathcommands direct the TimeQuest Timing Analyzer to analyze the paths as a same-edge transfer,whereby the same edge that launches data is latched to it. The reason it is latched on the same edgeis that latch edge will be delayed by the DQS circuitry (67.5° in this design example) into the middleof the data eye.

Example 3: set_multicycle_path Commands

set_multicycle_path -rise_from [get_clocks {virtual_dqs_in}] -rise_to [get_clocks

{dqs_in}] -setup -end 0

set_multicycle_path -fall_from [get_clocks {virtual_dqs_in}] -fall_to [get_clocks


Constraining Outgoing DQS StrobeThe following commands constraint the outgoing DQS strobe. The design sends the data out by a clockshifted 270°, so that the non-shifted clock is center-aligned. These constraints specifies that the external


Send Feedback

UG-01089Analyzing Same Edge Transfer68 2014.07.07


device adds ±150 ps of skew, which could also be described as a setup requirement and hold requirementof 150 ps. These numbers are an example, and you must modify constraints to reflect data/clock relationshipin their system. Use the -add option to add your delay constraint instead of overriding previous constraints.

Example 4: Constraining DQS Strobe Commands

create_generated_clock -name dqs_out -source

[get_pins{pll_inst/alterapll_inst/altera_pll_i/general[1].gpll PLL_OUTPUT_COUNTER/divclk}]

-phase 0 [get_ports{output_strobe_out}]

set_output_delay -clock { dqs_out } -max 0.150 [get_ports {read_write_data_io[*]}]

-add_delay

set_output_delay -clock { dqs_out } -max 0.150 -clock_fall [get_ports

{read_write_data_io[*]}] -add_delay

set_output_delay -clock { dqs_out } -min -0.150 [get_ports {read_write_data_io[*]}]

-add_delay

set_output_delay -clock { dqs_out } -min -0.150 -clock_fall [get_ports

{read_write_data_io[*]}] -add_delay

Figure 43:

The following set_false_path commands ensure that we are analyzing only the same edge transfers,by removing the opposite edge transfers.

These assignments areoptional.

Note:


set_false_path -setup -rise_from

[get_clocks{pll_inst/alterapll_inst/altera_pll_i/general[2].gpll PLL_OUTPUT_COUNTER/divclk}]

-fall_to [get_clocks{dqs_out}]

set_false_path -setup -fall_from


-rise_to [get_clocks{dqs_out}]


Send Feedback

69Constraining Outgoing DQS StrobeUG-010892014.07.07


set_false_path -hold -rise_from


-rise_to [get_clocks{dqs_out}]

set_false_path -hold -fall_from


-fall_to [get_clocks{dqs_out}]

The following set_multicycle_path commands ensure that the correct transfer between the DDlO andRead FlFO.


set_multicycle_path -from

{*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].capture_reg HIGH_DFF} -

to

{*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr INPUT_DFF_*}

-setup -end 0

set_multicycle_path -from

{*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].capture_reg LOW_DFF} -

to

{*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr INPUT_DFF_*}

-setup -end 0

FIFO control algorithm is necessary. Consider designing some soft FlFOs for this purpose. Thefollowing paths can only be set to false path or multicycle if there is calibration algorithm in thesystem to ensure correct functionalities.


#set_false_path -from

{*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr WRITE_LOAD_DFF_*}

-to

{*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr READ_LOAD_DFF_*}

Related Information

• FIFO Control on page 18Describes the hard data valid FlFO and hard latency shifter FlFO of the Arria V and Cyclone V devices.

tq_analysis.tcl

The tq_analysis.tcl is a script that analyzes specific dqdqs I/O timing paths. Because you might be changingthe l/O constraints for your specific implementation, this TCL script helps you to quickly run specific timinganalysis.


Send Feedback

UG-01089tq_analysis.tcl70 2014.07.07


Arria V Design ExampleThis section describes how to instantiate the ALTDQ_DQS2, ALTERA_PLL, ALTDLL, ALT_OCT IP coresusing the Top_AV_13.0sp1.qar design example.

Instantiating the ALTDQ_DQS2 IP CoreTo instantiate the ALTDQ_DQS2 IP core, perform the following steps:

1. In the Quartus II software, open the Top_AV_13.0sp1.qar design example and restore the archived fileinto your working directory.



4. On the Parameter Settings tab, on the General page, specify the parameters as shown in the followingfigure. These parameters configure the general settings for the ALTDQD_DQS2 instance.

Figure 44: ALTDQ_DQS2 Parameter Settings for Arria V Devices

5. Click Finish.

Because your design requires bidirectional strobe, you must use the DQS enable block by turningon the Make capture strobe bidirectional. In such case, the timing of the capture strobe enable

Note:

block requires knowledge of the arrival time of the capture strobe which typically requires round-trip delay information. However, the use of the DQS enable block requires runtime calibrationwhich is not a feature of the ALTDQ_DQS2 IP core.


Send Feedback

71Arria V Design ExampleUG-010892014.07.07


Instantiating the ALTDLL IP CoreTo instantiate the ALTDLL IP core, follow these steps:




Figure 45: ALTDLL Parameter Settings

4. Click Finish.

Instantiating ALT_OCT IP Core1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.





Send Feedback

UG-01089Instantiating the ALTDLL IP Core72 2014.07.07


Figure 46: ALT_OCT Parameter Settings Tab

4. Click Finish.

Instantiating Altera PLL1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.



3. On the General tab, specify the parameters as shown in the following figures.

Figure 47: Altera PLL Parameter Settings for Arria V Devices

4. Click Finish.

Altera PLL Clock Settings Information

The following table lists the clock settings Information. You may merge the similar frequency counters intheir design, or the Fitter performs the merging automatically.


Send Feedback

73Instantiating Altera PLLUG-010892014.07.07


Table 20: Altera PLL Clock Settings Information

DescriptionClock

400 MHz. Used as 2x frequency if necessary.outclk_0

200 MHz. Used as strobe/dqs clock.outclk_1

200 MHz. 270° phase shifted. Used as data/dq clock.outclk_2

100 MHz. Used as half-rate clock.outclk_3

200MHz.Used to drive theALTDLL IP core. The following are theALTDLLminimumfrequency:

• Arria V devices: 200 MHZ• Arria V GZ: 300 MHz

outclk_4

200 MHz. Used to drive the full-rate core clock.outclk_5

100 MHz. Used to drive the half-rate core clock.outclk_6

25 MHz. Used as config_clk.outclk_7

lf thememory frequency is less than theALTDLL IP coreminimum frequency, then drive theALTDLLIP core at 2x or 4x of the memory frequency. Relatively, the DQS phase settings decrease as well.

Note:

Setting Up NativeLink and Simulation SettingsTo set up the NativeLink and simulation settings, follow these steps:

1. In the Quartus II software, on the Tools menu, select Options.2. In the Options dialog box, under Category list, expand General and then select EDA Tool Options.3. In the EDA Tools Options window, follow the settings as shown in the following figure:


Send Feedback



Figure 48: EDA Tools Options Dialog Box

4. In the Quartus II software, on the Assignments menu, click Settings.5. In the Settings dialog box, under the Category list, expand EDA Tool Settings. Click Simulation.6. Enter the necessary NativeLink settings. The following figure shows an example settings. In this design

example, a testbench (tb.v) is provided together with other supporting files.

Figure 49: Simulation Dialog Box

Figure 50: Test Benches Dialog Box


Send Feedback

75Setting Up NativeLink and Simulation SettingsUG-010892014.07.07


Figure 51: Edit Test Bench Settings Dialog Box

7. Run Analysis and Synthesis.8. To view the simulation results, on the Tools menu, select Run Simulation Tool and then click RTL

Simulation.For a successful simulation, you may need to manually change alterapll.vo to alterapll.v in the auto-generated top_run_msim_rtl_verilog.do file.

9. Before running the Fitter, ensure that the following settings are done in the Assignment Editor.

• I/O Standard• Input Termination• Output Termination• DQ Group• Location assignment for strobe pin—this helps the Fitter to fit the related DQ pins in the appropriate

l/O sub-banks. You can then back-annotate the locations if desired.

The following figure shows an example setting in the Assignment Editor and the Pin Planner results:

Figure 52: Assignment Editor Window


Send Feedback



Figure 53: Pin Planner

10. Run the Fitter, Timing Analysis, and Assembler. An SDC example (top.sdc) is included in the exampledesign.

Related Information

• Understanding Simulation Results—Stratix V Design Example on page 60

Understanding Simulation Results—Arria V Design Exampleln the Arria V design example, a generic testbench is used to test the write and read operations in theALTDQ_DQS2 IP core. The following table lists the components in the testbench.

Table 21: Testbench Components

DescriptionComponent

• Acts as a host controller, sends read/write commands to the ALTDQ_DQS2 IP core.

• Compares data read back from the DQSAgent to what it should be• Has a side channel (side reads/writes) communicating directly with the

DQS agent, bypassing the ALTDQ_DQS2 IP core. Use the data in the sidereads/writes to compare with the data sent to or received from theALTDQ_DQS2 IP core.

DQS Driver

• Acts as an external memory device.• Has a side channel (side reads/writes) communicating directly with the

DQS Driver, bypassing the ALTDQ_DQS2 IP core. Use the data in theside reads/writes to compare with the data sent to or received from theALTDQ_DQS2 IP core.

DQS Agent

Random data is generated and used in the testbench. You may see other data values if you are usingdifferent operating system and seeds.

Note:

The following figure shows the waveform for the testbench generated after executing thetop_run_msim_rtl_verilog.do file.


Send Feedback

77Understanding Simulation Results—Arria V Design ExampleUG-010892014.07.07


Figure 54: Example Waveform

All ports are in reset mode until the reset_n signal is asserted at 70 ns. Then, the core_clk_fr andcore_clk_hr clocks start to toggle. The agent_reset_n_to_dqs signal is asserted at 95 ns to reset theALTDQ_DQS2 IP core located in top_inst.

Dynamic Configuration

At 100 ns, there is a high pulse on the beginscan signal. When the agent_output_enable signal is pulledlow, the strobe_io and agent_dqs_in goes to Hi-Z between 110 ns and 8.795 us time mark, some internalcalibration is being carried out. Dynamic configuration is the main feature used. At 8.795 us time mark, theenable_driver signal is asserted. This specifies that the internal calibration is completed, and the controlis passed on to the host controller (the DQS driver) to perform the normal read/write operation.

For RTL related to dynamic configuration operations in this design example, refer toconfig_controller.sv file.

Note:

You can override the static values at runtime with a scan chain using the dynamic configuration feature inthe ALTDQ_DQS2 IP core. To help you achieve static timing closure, the dynamic configuration featureallows you to override the static values at runtime with a scan chain. Each I/O and the DQS logic containits own scan chain block (shift registers). This section shows you how to serially scan configuration bits intoeach scan chain block, between 100 ns and 8.795 us time mark.


Send Feedback

UG-01089Dynamic Configuration78 2014.07.07


The following figure shows thewaveform for the dynamic configuration simulation generated after executingtopwave.do (located in the simulation/modelsim folder), between the high pulses of beginscan andscandone.

Figure 55: Dynamic Configuration Waveform

Because the enable_driver signal is asserted at 8.795 us time mark, following read and write operationswill be executed by DQS driver.

The driver_clk is running at the same rate as the coreNote:

Related Information

• Dynamic Reconfiguration for ALTDQ_DQS2 on page 34

DQS Write Operation

The driver asserting the dqs_enable signal at 8.925 µs begins the write operation. This will configure theALTDQ_DQS2’s output_strobe_ena to high, getting ready to send out strobe to the DQS agent. Thedqs_write signal is asserted at 8.935 µs. This sets the write_oe_in signal of the ALTDQ_DQS2 IP core tohigh, getting ready to send out data to the DQS agent. The data are written to the dqs_writedata of theDQS driver, and then reflected in the dq signal of the ALTDQ_DQS2 IP core. The data written out from theDQS driver is also stored in checkfifo. During the DQS write operation, the strobe_io and agent_dqs_in

is toggling. Dqs_write deasserts at 8.985 us and dqs_enable deasserts at 8.995 us. Outgoing data from thedq signal of the ALTDQ_DQS2 IP core is center-aligned to the strobe (strobe_io).

The following figure shows the DQS write operation waveform.

Figure 56: DQS Write Operation Waveform

Before and after the DQS write operation, the strobe_io signal is in Hi-Z mode.Note:


Send Feedback

79DQS Write OperationUG-010892014.07.07


The following figure shows thewaveform for the dynamic configuration simulation generated after executingtopwave.do (located in the simulation/modelsim folder). The output_strobe_ena is held high from 8.925us to 8.995 us while the strobe_io signal starts toggling only between 8.94 us and 9.01 us. The write_oe_insignal is held high throughout the five sets of valid write_data_in, which is between 8.935 us and 8.955 us.Center-aligned output data appears on the read_write_data_io signal between 8.949 us and 8.999 us.

Figure 57: DQS Write Operation Waveform After Executing the topwave.do File

Side Read Operation

The side read operation is performed between 9.075 µs and 9.125 µs, in which the DQS agent sends data tothe DQS driver with the side_readdata signal. Data validation is carried out in parallel, by comparing theside_readdata signal against the content of the checkfifo (data which was written out during the DQSwrite operation). If there is a mismatch, the software generates an error message.

The following figure shows the waveform for the side read operation.

Figure 58: Side Read Operation Waveform

Side Write Operation

The side write operation begins between 9.185 µs and 9.255 µs. The data written out from the DQS driveris also stored in checkfifo.

The following figure shows the waveform for the side write operation.


Send Feedback

UG-01089Side Read Operation80 2014.07.07


Figure 59: Side Write Operation Waveform

The incoming data at dq is edge-aligned to the strobe_io.Note:

DQS Read Operation

Data validation is done by comparing data received by the ALTDQ_DQS2 core (read_data_out) againstthe content of the checkfifo.

DQS read is initiated by the DQS driver when dqs_read is asserted at 9.345 us. The lfifo_rdata_en_full(dqs_read) of the ALTDQ_DQS2 IP core is also asserted for the entire length of the desired read burst,which in this case is 12 full-rate cycles. As the DQS agent receive the read command, it is then ready to sendsout data as per requested. This is shown with agent_output_enable being asserted from 9.380 us to 9.445us. During this period, the DQS agent drives the strobe and data lines of the external memory interface. Inthis test bench, strobe_io is driven by dqs_agent_to_ios. When output enable is deasserted, strobe_iowill be set to Hi-Z.

Figure 60: DQS Read Operation Waveform

As the incoming data arrives at the ALTDQ_DQS2 IP core, the edge-aligned data on read_write_data_io,and strobe on strobe_io ports. Following will discuss how the data is captured in the FPGA before it ismade available in the core.

DQS Delay Chain

The dqsenable signal grounds the DQS input strobe after the strobe goes to Hi-Z. This is important forbidirectional strobes, where glitches can be filtered effectively through the DQS enable. The dqsbusoutsignal is the delayed dqsin signal that drives into the dedicated DQS clock network to clock the DQ captureregisters so that data is captured at the centre of the eye. The following figure shows a 90° phase shift between


Send Feedback

81DQS Read OperationUG-010892014.07.07


the dqsin and dqsbusout signals. This is consistent with the settings in Instantiating the ALTDQ_DQS2IP Core on page 71.


VFIFO, LFIFO, and Read FIFO

In Arria V and Cyclone V devices, the data valid FIFO (VFIFO) generates the input signal to theDQS_ENABLE_CTRL block and connects to the write enable port of the read FIFO. The latency shifterFIFO (LFIFO) connects to the read enable port of the read FIFO. The LFIFO and VFIFO implement eachconfigurable latencies to determine the time to read enable and write enable for the Read FIFO respectively.The lfifo_rd_latency signal determines the latency setting in the LFIFO while the vfifo_inc_wr_ptrsignal determines the latency setting for the VFIFO. The read FIFO is in every input data paths, and you canset the read FIFO to control the conversion between FR-FR or FR-HR in Arria V and Cyclone V devices.

Figure 62: VFIFO, LFIFO and Read FIFO in Arria V and Cyclone V Devices

ReadFIFO

DOUT DIN

REN WREN

LatencyShifterFIFO

DataValidFIFO



When the host sends out a read command, a token is also sent to the LFIFO and the VFIFO. This tokenshould be asserted for the length of the desired read burst. This token is referred to lfifo_rdata_en_full

(for LFIFO) and vfifo_qvld (for VFIFO). In this testbench, the lfifo_rd_latency is set to 15d. Note thatthis is consistent with the latency noticed between rdataenfull of the LFIFO and readenable of the readFIFO, which is 16 half- rate clock cycles. The lfifo_rdata_en_full and vfifo_qvld signals pass througheach HR-FR DDIO before it reaches the rdataenfull of the LFIFO and the qvldin of the VFIFO at 9.355us. The delayed qvldreg of the VFIFO (1.5 half-rate cycles) feeds the DQSENABLEIN of theDQS_ENABLE_CTRL block. Meanwhile, the rden signal of the LFIFO, which is delayed by 16 half-ratecycles, feeds the READENABLE of the read FIFO.

The dqsenable signal is asserted at 9.3825 us. Edge-aligned input data starts at 9.385 us and ends at 9.445us. The dqsenable signal is deasserted at 9.44 us. In an actual application, you are required to have someformofDQS enable runtime calibration to obtain the correctDQS gating-ungatingwindow. The strobe_iosignal goes to Hi-Z when the DQS read operation completes. Because the writeenable signal of the readFIFO is always asserted, data is written into the read FIFO whenever the read FIFO is available, which is asearly as 9.395 us. However, data is only read out when the readenable signal is asserted between 9.515 us


Send Feedback

UG-01089VFIFO, LFIFO, and Read FIFO82 2014.07.07


and 9.575 us. The data are available in the read_data_out signal. You can further optimize the timing toread the read FIFO by adjusting the LFIFO latency delay to create sufficient space between the read andwrite pointers in the read FIFO to maximize the throughput.

Figure 63:

The write enable (we) and read enable (re) signals of the hard read FIFO are different from the wrreqand rdreq signals of the DCFIFO. In DCFIFO, the data are only available at the FIFO output ports

Note:

when the rdreq signal is asserted. In hard read FIFO, the we signal controls when to advance thewrite address counter while the re signal controls when to advance the read address counter. Whenthe read and write address pointers are the same, write data appear at the read port as soon as a writeoperation is completed. This explains why we see the first written data available almost immediatelyat the FIFO output port. When the signal is asserted, it will advance to the next read address, andthen only the second written data is available at the FIFO output port.

Beginning from the Quartus II software version 13.1, the lfifo_rdata_en and lfifo_rdata_valid

signals will be removed.Note:

DQS Enable Control

The goal of DQS enable calibration is to find settings that satisfy the following conditions:

• The DQS enable signal rises before the first rising edge of DQS.• The DQS enable signal is high after the second-last falling edge of DQS.• The DQS enable signal falls before the last falling edge of DQS.

The ideal position for the falling edge of the DQS enable signal is centered between the second-last and lastfalling edges of DQS.

Related Information

• Functional Description—UniPHY


Send Feedback

83DQS Enable ControlUG-010892014.07.07

http://www.altera.com/literature/hb/external-memory/emi_fd_uniphy.pdf


Simulation Results

The following figure shows the simulation results in the message panel. lf the simulation failed, it is due tothe data sent/received at the ALTDQ_DQS2 is not the same as the expected ones.

Figure 64: Simulation Results

SDC Walkthrough

To create a new .sdc, follow these steps:

1. Constrain the clocks coming into the FPGA with the create_clock command. The following commandcreates the base clock for the input clock port driving the PLL:create_clock -name refclk -period 10.000 [get_ports {refclk}]

2. Create the generated clocks for the PLL with the following command:derive_pll_clocks

3. Constraint the virtual input clock (for incoming DQS strobe) and the strobe_in port. ln this designexample, it is based on a 200 MHz input clock, with a 50% duty cycle, where the first rising edge occursat 0 ns.

create_clock -name virtual_dqs_in -period 5.000

create_clock -name dqs_in -period 5.000[get_ports {strobe_in}]

4. lncoming data is edge-aligned to theDQS strobe, and theminimumandmaximum input delay is assumedto be ± 0.4 ns in this design example. You must modify constraints to reflect the data and clockrelationship in the system. Use the -add option to add the your delay constraint instead of overridingprevious constraints.set_input_delay -clock {virtual_dqs_in} -max -add_delay 0.400 [get_ports


set_input_delay -clock {virtual_dqs_in} -min -add_delay -0.400

[get_ports{read_write_data_io[*]}]

set_input_delay -clock {virtual_dqs_in} -clock_fall -max -add_delay 0.400 [get_ports


set_input_delay -clock {virtual_dqs_in} -clock_fall -min -add_delay -0.400 [get_ports

{read_write_data_data_io[*]}]


Send Feedback

UG-01089Simulation Results84 2014.07.07


Figure 65:

Analyzing Same Edge Transfer

The following set_false_path commands ensure that you are analyzing only the same edge transfers, byremoving the opposite edge transfers.

These assignments are optional.Note:


set_false_path -setup -rise_from [get_clocks {virtual_dqs_in}] -fall_to [get_clocks

{dqs_in}]

set_false_path -setup -fall_from [get_clocks {virtual_dqs_in}] -rise_to [get_clocks

{dqs_in}]

set_false_path -hold -rise_from [get_clocks {virtual_dqs_in}] -rise_to [get_clocks

{dqs_in}]

set_false_path -hold -fall_from [get_clocks {virtual_dqs_in}] -fall_to [get_clocks

{dqs_in}]

The default setup relationship is to latch data on the next edge. The following set_multicycle_pathcommands direct the TimeQuest Timing Analyzer to analyze the paths as a same-edge transfer,whereby the same edge that launches data is going to latch it. The reason it is latched on the sameedge is that latch edge will be delayed by the DQS circuitry (hardened 90° in this design example)into the middle of the data eye.


set_multicycle_path -rise_from [get_clocks {virtual_dqs_in}] -rise_to [get_clocks


set_multicycle_path -fall_from [get_clocks {virtual_dqs_in}] -fall_to [get_clocks


Constraining Outgoing DQS Strobe

The design sends the data out by a clock shifted 270° so that the non-shifted clock is center-aligned. Theseconstraints state that the external device adds ±250ps of skew, which could also be described as a setup


Send Feedback

85Analyzing Same Edge TransferUG-010892014.07.07


requirement andhold requirement of 250 ps. These numbers are an example, and youmustmodify constraintsto reflect the data and clock relationship in the system. Use the -add option to add your delay constraintinstead of overriding previous constraints.

Use the –add option for the create_generated_clock command for the strobe_io port becausethe port is bidirectional.

Note:

The following commands constraint the outgoing DQS strobe.

Example 10: Constraining DQS Strobe Commands

create_generated_clock -name dqs_out -source

[get_pins{dqdqs2_inst|bidir_hardfifo_dqdqs2_inst|altdq_dqs2_inst|phy_clkbuf|outclk[1]

}] -phase 0 [get_ports {strobe_io}] -add

set_output_delay -clock {dqs_out} -max 0.250 [get_ports {read_write_data_io[*]}]

-add_delay

set_output_delay -clock { dqs_out } -max 0.250 -clock_fall [get_ports

{read_write_data_io[*]}] - add_delay

set_output_delay -clock {dqs_out} -min -0.250 [get_ports {read_write_data_io[*]}]

-add_delay

set_output_delay -clock { dqs_out } -min -0.250 -clock_fall [get_ports

{read_write_data_io[*]}] - add_delay

Figure 66:

The following set_false_path commands ensure that we are analyzing only the same edge transfers,by removing the opposite edge transfers.

These assignments areoptional.

Note:


set_false_path -setup -rise_from

[get_clocks{pll_inst|alterapll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]

-fall_to [get_clocks {dqs_out}]


Send Feedback

UG-01089Constraining Outgoing DQS Strobe86 2014.07.07


set_false_path -setup -fall_from


-rise_to [get_clocks {dqs_out}]

set_false_path -hold -rise_from


-rise_to [get_clocks {dqs_out}]

set_false_path -hold -fall_from


-fall_to [get_clocks {dqs_out}]

The strobe port functions as input or output at a time. Non-related transfers below should be set to falsepath and do not need to be analyzed.

set_false_path -from [get_clocks {virtual_dqs_in}] -to [get_clocks {dqs_out}]

Timing Violation

The following figure shows a timing violation in the example design. This path is related to DQS enablecontrol and is valid. Some calibration algorithm is required to control the DQS enable block.

Figure 67: Timing Violation

Without any calibration algorithm in place, this path cannot be set as false path in the static timing analysis.

Example 12: set_false_path Command

#set_false_path -from [get_keepers {*|dqs_enable_ctrl~DQSENABLEOUT_DFF}] -to

[get_clocks{dqs_out}]

Related Information

• External Memory Interfaces in Arria V Devices

For more information related to the PHY Clock and DQS Logic Blocks.

• Functional Description—UniPHY

For more information on some basic calibration.

tq_analysis.tcl

The tq_analysis.tcl is a script that analyzes specific dqdqs I/O timing paths. Because you might be changingthe l/O constraints for your specific implementation, this TCL script helps you to quickly run specific timinganalysis.


Send Feedback

87Timing ViolationUG-010892014.07.07


http://www.altera.com/literature/hb/external-memory/emi_fd_uniphy.pdf


IP-Generate CommandYou can use the ip-generatecommand to create custom variations of the ALTDQ_DQS2 IP core.

Using IP-Generate CommandYou can use ip-generate.exe, a command-line executable, to configure parameters. The command createsor modifies custom IP core variations, which you can then instantiate in a design file.

To run the ip-generate command, follow these steps:

1. Locate the ip-generate.exe executable file in the<quartus_install_dir>\quartus\sopc_builder\bin folder.Ensure that you include the directory path into your operating system environment.

2. To obtain the options for the ip-generate command, type the following command in the commandprompt:

ip-generate –help

3. To instantiate the IP core using the executable file, type the following syntax:

ip-generate --component-name=altdq_dqs2 -–component-system-param=DEVICE_FAMILY=”Stratix V” -–file-set=QUARTUS_SYNTH --output-name[=<file_name>] –-component- param[=<parameter_name>][=<parameter_value>]

The <file_name> is the instance name. For example, my_dqdqs2. The <parameter_name> is the nameof the parameter that you configure with the value stated in <parameter_value>.

You must use the –-component-param[=<parameter_name>][=<parameter_value>] option for everyparameter assignment. Parameters that are not assigned take the default values. Ensure that you type theexact case and spaces for the parameter names and values.

The following list describes two examples of how you can use this command:

• To create an ALTDQ_DQS2 instance named my_dqdqs2 with all the default parameter values, typethe following command:

ip-generate --component-name=altdq_dqs2 -–component-system-param=DEVICE_FAMILY=”Stratix V” --output-name=my_dqdqs2 -–file-set=QUARTUS_SYNTH

• To create an ALTDQ_DQS2 instance named mydq_dqs2without output strobe ports, and with a 135°DQS phase shift, type the following command:

ip-generate --component-name=altdq_dqs2 –-component-system-param=DEVICE_FAMILY=”Stratix V” --output-name=my_dqdqs2 -–file-set=QUARTUS_SYNTH --component-param=USE_OUTPUT_STROBE=”False” --component-param=DQS_PHASE_SETTING=”3”

This command generates two files—my_dqdqs2.v and my_dqdqs2_altdq_dqs2.sv. The my_dqdqs2.vfile contains the my_dqdqs2 top-levelmodule, and themy_dqdqs2_altdq_dqs2.sv file contains the sourcecode. The files are in Verilog HDL format.

The ip-generate command generates the ports for the instance based on the parameter values.

Related Information

• ALTDQ_DQS2 Ports on page 21


Send Feedback

UG-01089IP-Generate Command88 2014.07.07


• ALTDQ_DQS2 Parameter Settings on page 8

Document Revision History

Table 22: Document Revision History

ChangesVersionDate

• Replaced MegaWizard Plug-In Managerinformation with IP Catalog.

• Added standard information about upgradingIP cores.

• Added standard installation and licensinginformation.

• Clarified that configuration datamust be inputin LSB first ordering and updated the typicalfrequency for config_clock_in from50MHzto 25 MHz in the Dynamic Reconfigurationfor ALTDQ_DQS2 on page 34 section.

• Updated vfifo_qvld[] inTable 8 to clarify thatthis signal is also supported in Stratix Vdevices. Also clarified that the this signal is 1-bit wide for Stratix V devices and 2-bits widefor Arria V and Cyclone V devices.

• UpdatedTable 10,Table 12, and Figure 17 toupdate IOE delay settings information.

• Removed lfifo_rdata_en and lfifo_rdata_validports information from Figure 14 and Table8.

• Added information about checking the validityof the data coming from the read FIFO inFIFO Control on page 18.

• Added Arria V Design Example on page 71and Stratix V Design Example on page 54sections.

• Updated DQS Configuration Block BitSequence for Arria V GZ and Stratix VDevices on page 38 and I/O ConfigurationBlock Bit Sequence for Arria V GZ andStratix VDevices on page 36 to include ArriaV GZ devices.

• Clarified that the ALTDQ_DQS2 does notsupport DQS tracking.

2014.07.07July 2014

• Updated note in Figure 3–8 on page 3–10.• Added “Additional Information” section.

2.2January 2013


Send Feedback

89Document Revision HistoryUG-010892014.07.07


ChangesVersionDate

• Replaced previous design examples with thefollowing design examples:

• ForArriaVdevices: 12.1_AV_BasicDesign.qar• For Stratix V devices: 12.1_SV_BasicDe-

sign.qar• Made necessary changes in the document to

reflect the design examples replacement.

2.1December 2012

• Major enhancement to include:• Arria V and Cyclone V devices information.• Updated “Features” on page 1–1:• Included read FIFO, hard FIFO, latency shifter

FIFO, and data valid FIFO.• “Device Support” on page 1–2• Included Arria V and Cyclone V devices.• Updated “Parameter Settings” on page 2–1:• UpdatedTable 2–1 on page 2–1 to include new

parameters and to update old parameters.• Updated “ALTDQ_DQS2 Datapaths” on

page 3–1:• Updated Figure 3–1 and added notes (3), (4)

, and (5) to clarify the usage of soft and hardFIFO for different devices and to explain thelocation of an inversion.

• Added the following new sections: “DQSLogic” on page 3–2, “Capture DDIO to ReadFIFO Path” on page 3–3, and “FIFO Control”on page 3–4.

• Updated “ALTDQ_DQS2Ports”onpage 3–10:• Updated “DQ and DQS Output Path” on

page 3–6 to include DQS output pathinformation.

• Updated Figure 3–5 on page 3–6 and addednotes to the figure to help distinguish thedevice support.

• Updated Figure 3–6 on page 3–7 to fix thevariable typo and to clarify that the figure isfor additional pin usage for Stratix V devices.

• Combined and converted IP cores informationto Table 3–3 on page 3–8 for ease of reference.

• Added Figure 3–7 on page 3–8 to shows theDQ and DQS output path for Arria V andCyclone V devices.

2.0December 2012


Send Feedback

UG-01089Document Revision History90 2014.07.07


ChangesVersionDate

• Updated “ALTDQ_DQS2Ports”onpage 3–10:• Major update to Figure 3–8 on page 3–10 to

clearly define the device family support andthe port types.

• UpdatedTable 3–3 on page 3–8 to include newALTDQ_DQS2data strobe ports and updatedold ALTDQ_DQS2 ports.

• Updated Table 3–5 on page 3–12 to includenew ALTDQ_DQS2 data ports and updatedold ALTDQ_DQS2 data ports.

• Updated Table 3–7 on page 3–14 to update thedescription of the ALTDQ_DQS2 PLL andDLL ports

• Added Table 3–8 on page 3–14 to introducethe new ALTDQ_DQS2 hard FIFO ports.

• Updated Table 3–9 on page 3–15 to add newALTDQ_DQS2 dynamic configuration portsand to update old ports.

• Added new chapter: “Dynamic Reconfigura-tion for ALTDQ_DQS2 Megafunction” onpage 4–1.

• Added new chapter: “InstantiatingMegafunc-tions” on page 5–1

• Added design examples.

2.0December 2012

Initial release.1.0September 2010


Send Feedback

91Document Revision HistoryUG-010892014.07.07


altdq dqs2 ip core user guide · for the data (dq) and data strobe (dqs) signals in arria®v,...

Documents