A Flexible 4 x 16 MIMO Testbed with250 MHz - 6 GHz Tuning Range

Steven W. EllingsonVirginia Polytechnic Institute & State University, ellingsonovt. edu

Abstract

The Matrix Channel Measurement System (MCMS) is a new instrument for multiple-input multiple-output (MIMO) channel measurements up to 4 x 16, and other applications. Notable features are (1) Tuningrange from 250 MHz to 6 GHz; (2) Support for up to 16 receive antennas simultaneously, achieved using anovel data aggregation architecture using concurrent serial buses; (3) Sustained instantaneous bandwidth of1 MHz continuously or up to 40 MHz in an asynchronously-triggered "burst" mode; and (4) Portable designsuitable for operation in field conditions under battery power.

I. INTRODUCTIONIt is well-known that multiple-input multiple-output (MIMO) wireless communications

systems have the potential to provide capacity improvements which increase linearly withthe number of antennas, as opposed to logarithmically as is the case for traditional smartantenna schemes [1]. However, this level of performance requires multipath scattering suf-ficient to fully decorrelate the desired spatial channels. It is now well-known that thisfrequently does not occur. An extreme example is the fully-degenerate "keyhole" scenario[2], but there are many ways in which MIMO performance can be limited: For example,by anomalous propagation, such as in hallways [3]; or by antenna design issues, such asclose spacing, cross-polarization, and mutual coupling [4]. Identifying and understandingthe impact of these limiting phenomena is a matter of great concern in the deployment ofMIMO systems such as the emerging wireless LAN standard IEEE 802.11n. For this, fieldmeasurements and in situ trials are essential.

The Matrix Channel Measurement System (MCMS), shown in Figure 1, has been devel-oped for this purpose. The system consists of a multichannel transmitter (MCT) capable ofgenerating independent RF waveforms for 4 antennas, and a multichannel receiver (MCR)consisting of independent receivers and data aggregation for coherent sampling of up to 16antennas simultaneously. The relatively large number of receive channels was chosen to fa-cilitate enhanced analysis of propagation conditions (for example, high-resolution directionof arrival estimation) simultaneously with the operation of the MIMO communication link,and also to facilitate simultaneous multi-frequency operation. Captured data can be eitherrouted to a commercial digital signal processing card for baseband or symbol-rate process-ing, or saved directly to a hard drive for off-line processing. Continuous sampling can besustained for 16 antennas and bandwidths up to about 1 MHz, or the MCR can be operatedin a "burst" mode which facilitates a bandwidth of up to 40 MHz. This is achieved using anovel serial bus data aggregation strategy which is described in greater detail in Section II.

Other notable features of MCMS are large tuning range, software-defined configuration,and portability. A tuning range of 250 MHz to 6 GHz was specified to ensure access to theU.S. ISM bands at 2.4 GHz and 5.7 GHz and also to support various commercial, military,and public safety applications throughout the VHF and UHF spectrum. This flexibility intuning range is also useful in conducting simultaneous dual-frequency measurements neededfor measurement of spectral coherence, often of interest in systems using very large band-widths or frequency division duplexing. MCMS can be reconfigured, for example, as two2 x 8 systems using the same or different antennas at completely independent frequencies.

MIMO channel studies are quite often limited in scope by the onerous logistics associatedwith the necessary experiments; in particular, the transportation and operation of cumber-some equipment. As shown in Figure 1, MCMS is self-contained in transportable racks andlight enough to be moved over short distances by 2 persons. Both MCT and MCR use

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Fig. I. Left: MCMS in the "stowed" configuration. The left and right cases are the MCT and MCRrespectively. The o-tall case above the MCT is a battery unit; the-r is oae foe the MCT an,d one for theMCR. Iiqhl: MCT front panel. The foIs RF upeonverter modules (gold-colored) lie flat in stackh of 2towards the center. The MCT is 55.9 c wide x 59.7 em deep x 71 c high and weighs about 57 kg.

+24VDC power, whichl in field conditions is provided by a battery pack which powers thesystern with all clainniels active for over 1 lir.

The MCMS project has been a collaboration with Aeroflex Corp. and colleagues (see Ac-knowledgemnents). The project began in October 2002 withi a design and proof-of-conceptphase at the principal investigator's home institution (at that time, the Ohio State Uni-versity) anid moved to Aeroflexas Powell, OH facility in Sumnmer 2003 for design of controland power systenis; revisioti of the proof-of-conicept design for manufacturability; construc-tion; assembly; and initegration. Recently (December 2004), the system was delivered andis now being commissioned at Virginia Tech, with an emphasis on development of software.Additional/current irifortnation about MCMS is available via the project web site [5].

11. DESCRIPTION OF THE SYSTEMThe MCT is shown in Figure 1. The MCT synthesizes four analog IF signals, each up to

40 MHz wide and centereel at 78 MHz, using a board consisting of 14-bit, 200 MSPS AnalogDevices AD9857 qtcadrature digital upconverter (QDUC) ICs [6]. These outputs are routedto bank of fosir RF upconverters, identified in Figure 1.

The MCR includes 16 independent downiconverter/digitizer iimodules, as shown in Fig-ure 2. 250 -2000 MHz is upconverted to 3 GHz anid then downconverted to 1250 MHz,whereas 1.6--6.0 GHz is dowoiconverted directly to 1250 MHz. 1250 MHz is then down-converted to 78 MHz atid digitized at 104 MSPS using 12 bits. Direct sampling of the78 MHz IF haa the conmpelling advantage of making subsequent signal processing free oferrors associateti with anialog processing in particuilar, I-Q balance is nearly perfect sincereal aind imaginary componietits are obtained digitally, as described below. A programmableatteniuator in the 78 MHz IF section provides 0-28 dB attenuation to allow optimization ofdigitizer dytianiic range. The digitizer otutput is separated inito "even" and "odd" samplestreains, serialized, and transmitted using low voltage differential signaling (LVDS). The ag-gregate oittptit is 1.248 Gb/s, and is transmitted over common "CAT-5" unshielded twisted

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Fig. 2. Left: MCR front panel. The rack is 55.9 cm wide x 59.7 cm deep x 99.0 cm high and weighs about90 kg. ight: MCR data aggregation architecture.

pair cable. These are received by a digital IF processor card, where the signals are dese-rialized and delivered to an Altera "Stratix" field programmable gate array (FPGA). ThisFPGA performs a multiplier-less "Fs/4" spectral shift, centering the 78 MHz IF at zeroHz by rearranging the samples into real and imaginary streams and alternating signs. Theresult is low-pass filtered with 20 MHz cutoff using a 63-tap FIR with 12 bit coefficients,and then decimated by two, yielding a 52 MSPS complex-valued sample stream encoding40 MHz of bandwidth. This signal can be routed either to the board output for capture, oralternatively can be filtered and decimated again, this time to 26 MSPS encoding 20 MHzbandwidth using a 46-tap FIR with 12-bit coefficients. This signal can also be either cap-tured as output or processed further. For further processing, the signal is routed to anAnalog Devices AD6620 digital downconverter (DDC) integrated circuit [71. This DDC canbe used to achieve further reductions in sample rate and bandwidth and is dynamicallyreprogrammable by the user. Normally the device would be programmed for a sample rateand bandwidth that is convenient for subsequent processing (typically, demodulation), andthe device works best for output bandwidths of about 1.5 MHz or less.

The process of combining and reordering data into "snapshots" consisting of one sampleper channel for a given time index - sometimes called "corner turning" - is traditionallya difficult problem in high-bandwidth array receivers. The limitation is typically a simplebut vexing issue of interconnect density - that is, it turns out to be impossible to bring bit-parallel data from all receivers to a common location for corner turning. In the MCR, forexample, bringing together 16 32-bit samples requires a device with 512 pins, which is notreasonable. This problem is avoided using a novel technique originally developed and suc-cessfully implemented for another project [81, [9]. As shown in Figure 2, digital IF processorcards are organized into groups of 4 and connected in "daisy chain" fashion with a 5th boardknown as the "corner turner." The daisy chain is implemented using the same protocol-lessLVDS serial bus technology used to connect digitizers to digital IF boards, but in this caseruns at 320 Mb/s. The daisy chain collects one sample from each digital IF board (cor-ner turning these "on the fly"); and delivers these 4-sample snapshots to the corner turnerboard, which is simultaneously collecting 4-sample snapshots from the other 3 groups of 4channels. The backplane carrying these 4 daisy chains is very simple because each LVDSserial connection requires only 2 traces. On the corner turner board, only 128 pins are re-quired to accommodate the deserialized data (4 daisy chains x 2 (input+output) x 16 bits(real and imaginary multiplexed)), which fits within a single large FPGA. The final stage of

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corner turning - combining the four 4-sample snapshot streams into one 16-sample snapshotstream - is accomplished within the FPGA. The snapshot stream emerges from the cornerturner board in 32-bit parallel form and is captured by a commercially-available high-speeddigital I/O board mounted in a compact PCI (cPCI) chassis with an embedded PC-basedcontroller. Data can be routed from the digital I/O board to either system memory, a harddrive, or a DSP board in real-time using direct memory access (DMA) transfers over thePCI bus. The maximum continuously-available bandwidth is about 1.5 MHz/channel whenDDCs are used.

This same architecture facilitates control of this processing in an elegant manner. Controldata is sent to the corner via the digital I/O board, and from there is disseminated to digitalIF boards via the same daisy chains used for data aggregation. At each digital IF board,control data is "dropped off" and signal data is "picked up." This approach greatly simpli-fies the design by eliminating the need for additional interconnections for control purposes,and does not reduce available throughput since the daisy chain data "outbound" from thecorner turner contains no signal data.

The DSP board mentioned above is a Bittware Quad DSP board which contains four Ana-log Devices ADSP-21160 "Hammerhead" DSPs and 256MB SDRAM for additional receivesignal processing. Because the FPGAs on the digital IF board are not fully utilized underthe conditions described above, it is possible to distribute additional signal processing tasksbetween these FPGAs, the DSPs, and the embedded PC flexibly and in what ever mannermakes sense for the current application. For example, digital tuning, channelization, cor-relation (in the case of direct sequence spread spectrum waveforms), and other simple butcompute-intensive operations can be implemented on digital IF boards, which are clockedat the digitizer sample rate of 104 MHz. The DSPs would typically be used for subsequentsymbol-rate and/or array signal processing, but can alternatively be used to implement allfunctionality in a completely software-defined fashion for sufficiently small bandwidths.

ACKNOWLEDGMENTSThis material is based upon work supported by the National Science Foundation under

Grant No. ECS-0215990. Essential contributions to the development of MCMS have beenmade by P. Bohley, S. Fisher, G. Hampson, S. Horst, M. Nuhfer, B. Reynolds, W. Taylor,and W. Theunissen. This project would not have been possible without the generous supportof the Aeroflex Corporation.

REFERENCES[1] G.J. Foschini and M.J. Gans, "On Limits of Wireless Communications in a Fading Environment when

Using Multiple Antennas", Wireless Personal Communications (Kluwer), 6:311-335, 1998.[2] D. Chizhik, G.J. Foschini, and R.A. Valenzuela, "Capacities of Multi-Element Transmit and Receive

Antennas: Correlations and Keyholes," Electronics Letters, Vol. 36, No. 13, June 2000, pp. 1109-10.[3] D. Porrat, P. Kyritsi, and D.C. Cox, "MIMO Capacity in Hallways and Adjacent Rooms," IEEE

GLOBECOM 2002, 2:1930-4, Nov 2002.[4] C. Waldschmidt, S. Schulteis, and W. Wiesbeck, "Complete RF System Model for Analysis of Compact

MIMO Arrays," IEEE Trans. Vehicular Technology, Vol. 53, No. 3, pp. 579-586, May 2004.[5] MCMS Project Weh Site, http://www.ece.vt.edu/.swe/mcms/.[6] Analog Devices, Inc., "CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter AD9857" (data sheet),

Rev. C, 2004. Available at http://www.analog.com.[7] Analog Devices, Inc., "67 MSPS Digital Receive Signal Processor AD6620" (data sheet), Rev. A, 2001.

Available at http://www.analog.com.[8] S.W. Ellingson and G.A. Hampson, "Argus: an L-Band Array for Detection of Astronomical Transients,"

Proc. 2003 IEEE Ant. & Prop. Soc. Int'l Sym., Columbus, OH, Vol. 3, pp. 256-249, June 2003.[9] Argus Project Web Site, http://www.ece.vt.edu/.swe/argus/.

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