advanced modeling and multi-objective optimization / … · 2017. 9. 26. · triple-interleaved ....

110
2015 WiPDA Ralph M. Burkart & Johann W. Kolar ETH Zurich, Switzerland Power Electronic Systems Laboratory www.pes.ee.ethz.ch Advanced Modeling and Multi-Objective Optimization / Evaluation of SiC Converter Systems Tutorial

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  • 1/110

    2015

    WiPDA

    Ralph M. Burkart & Johann W. Kolar ETH Zurich, Switzerland

    Power Electronic Systems Laboratory www.pes.ee.ethz.ch

    Advanced Modeling and Multi-Objective Optimization / Evaluation of

    SiC Converter Systems

    Tutorial

  • 2/110

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    Outline

    ► Introduction ► Basic Multi-Objective Optimization Approach ► Component Models incl. Costs ► Converter Optimization / Evaluation – Example I ► Converter Optimization / Evaluation – Example II ► Conclusions

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    Introduction Performance Trends Performance Space

    Pareto Front Design Space

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    ► Power Electronics Converters Performance Trends

    ─ Power Density [kW/dm3] ─ Power per Unit Weight [kW/kg] ─ Relative Costs [kW/$] ─ Relative Losses [%] ─ Failure Rate [h-1]

    ■ Performance Indices

    [kgFe /kW] [kgCu /kW] [kgAl /kW] [cm2Si /kW] ►

    Environmental Impact…

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    ► Performance Improvements (1)

    ─ Telecom Power Supply Modules: Typ. Factor 2 over 10 Years

    ■ Power Density

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    ► Performance Improvements (2)

    Inefficiency (Losses)…

    ■ Efficiency

    ─ PV Inverters: Typ. Loss Red. of Typ. Factor 2 over 5 Years

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    Source: 2006

    ► Performance Improvements (3)

    ■ Costs

    ─ Importance of Economy of Scale

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    ► Performance Improvements (4)

    ■ Costs

    ─ Automotive: Typ. 10% / a ─ Economy of Scale !

    Source: PCIM 2013

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    ► Design Challenge

    ■ Mutual Coupling of Performance Indices Trade-Off Analysis (!)

    ─ For Optimized Systems Several Performance Indices Cannot be Improved Simultaneously

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    ► Design Challenge

    ■ Mutual Coupling of Performance Indices Trade-Off Analysis (!)

    ─ For Optimized Systems Several Performance Indices Cannot be Improved Simultaneously

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    ■ Design for Specific Performance Profiles / Trade-Offs Dependent on Application

    ► Graphical Representation of Performance

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    ► Mutual Coupling of Performances (1)

    ■ Experimental Exploration of the Power Density Improvement of a Three-Phase PFC Rectifier System with Increasing Switching Frequency

    w/o Heat Sink

    fP = 50 kHz ρ = 3 kW/dm3

    fP = 72 kHz ρ = 4.6 kW/dm3

    fP = 250 kHz ρ = 10 kW/dm3

    fP = 1 MHz ρ = 14.1 kW/dm3

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    ► Mutual Coupling of Performances (2)

    ■ Experimental Exploration of the Power Density Improvement of a Three-Phase PFC Rectifier System with Increasing Switching Frequency

    Consideration of a Single Performance Index is NOT Sufficient (!)

    fP = 50 kHz ρ = 3 kW/dm3

    fP = 72 kHz ρ = 4.6 kW/dm3

    fP = 250 kHz ρ = 10 kW/dm3

    fP = 1 MHz ρ = 14.1 kW/dm3

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    ► Mutual Coupling of Performances (3)

    ■ Consideration of a Single Performance Index is NOT Sufficient (!)

    ■ Trade-Off of Performances Must be Considered η-ρ-Performance Limit

    η-ρ-Performance Space

    fP = 50 kHz ρ = 3 kW/dm3

    fP = 72 kHz ρ = 4.6 kW/dm3

    fP = 250 kHz ρ = 10 kW/dm3

    fP = 1 MHz ρ = 14.1 kW/dm3

  • 15/110

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    ► Si CoolMOS, 99mΩ/600V ► SiC Diodes, 10A/600V

    PO=3.2kW UN=230V±10% UO=365V fP=33kHz ±3kHz Two Interleaved 1.6kW Systems

    99.2% @ 1.1kW/dm3

    ► Example of η-ρ-Trade-Off (1)

    ■ 1-Ф Boost-Type PFC Rectifier

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    PO=3.2kW UN=230V±10% UO=400V fP=450kHz ±50kHz Two Interleaved 1.6kW Systems

    ► Si CoolMOS ► SiC Diodes

    5.5kW/dm3 @ 95.8%

    ► Example of η-ρ-Trade-Off (2)

    ■ 1-Ф Boost-Type PFC Rectifier

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    Derivation of the η-ρ-Performance Characteristic

    * Semiconductors / Heatsink * Output Capacitor

    * Inductor

    fP

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    ► Analysis of η-ρ-Performance Characteristic (1)

    ■ Specifications / Assumptions

    ─ Rated Output Power P2 ─ Const. Input Current Ripple ΔiL ─ Const. Output Capacitance CO (Energy Storage) ─ Const. Tj of Power Semiconductors ≈ Ts ─ Def. Ambient Temperature Ta

    ■ Dependency of Component Losses / Volumes on Switching Frequency fP

    ─ Input Inductor ─ Output Capacitor ─ Semiconductors /Heatsink

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    ■ Input Inductor

    21 1 1

    O

    i

    P

    O O O OP

    P i P i P

    U U U U Iii T LI LIL I LI f f f

    212

    O OL L P

    P L

    P PV LI ff V

    ─ Inductor Power Density

    ► Analysis of η-ρ-Performance Characteristic (2)

    ─ Relative Inductor Losses

    0 (1 ) L LLL W C L P L L PO

    PP P P P k f fP

    ■ Output Capacitor

    0 0 C LP21 const. const.

    2 OC O C

    C

    PV CUV

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    ■ Semiconductors & Heatsink

    ► Analysis of η-ρ-Performance Characteristic (3)

    ─ Relative Semiconductor Losses

    (1 ) SS C P C P P S P PO

    PP P P P k f fP

    ─ Heatsink Volume / “Power Density”

    11

    th S O OS s a s a S

    S s a S S S

    G P P PCSPI T CSPI T CSPIV T V V P

    WK

    3dm

    CSPI

    Cooling System

    Performance Index

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    ■ System Efficiency & Power Density in Dependency of fP

    ► Analysis of η-ρ-Performance Characteristic (4)

    ─ Efficiency

    ─ Power Density

    ( ) ( ) ( )1 1 1 ( ) O i L S L S L S L Si i i O

    P P P P P P P PP P P P

    1

    O O

    S CLL S C

    O O O

    P PV VVV V V V

    P P P1 1 1 1( ) L C S

    ─ fP as Parameter of η = η{ρ}- Characteristic

    fP

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    ■ Only the Consideration of All Possible Designs / Degrees of Freedom Clarifies the Absolute η-ρ-Performance Limit

    ► Analysis of η-ρ-Performance Characteristic (5)

    ■ Specific Design Only fP as Variable Design Parameter

    fP =100kHz

    “Pareto Front”

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    ► Determination of the η-ρ-Pareto Front

    ─ Core Geometry / Material ─ Single / Multiple Airgaps ─ Solid / Litz Wire, Foils ─ Winding Topology ─ Natural / Forced Conv. Cooling ─ Hard-/Soft-Switching ─ Si / SiC ─ etc. ─ etc. ─ etc.

    ─ Circuit Topology ─ Modulation Scheme ─ etc. ─ etc. ─ etc.

    ■ System-Level Degrees of Freedom

    ■ Comp.-Level Degrees of Freedom of the Design

    ■ Only η-ρ-Pareto Front Allows Comprehensive Comparison of Converter Concepts (!)

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    Basic Multi-Objective Optimization Approach

    Abstraction of Converter Design Component / System Modeling

    Design / Performance Space Pareto Front

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    ► Mapping of Design Space into System Performance Space

    Performance Space

    Design Space

    ► Abstraction of Power Converter Design

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    ► Modeling and Multi- Objective Optimization of Converter Design

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    ► Multi-Objective Converter Design Optimization

    ■ Pareto Front - Limit of Feasible Performance Space

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    ■ Sensitivity to Technology Advancements ■ Trade-off Analysis

    ► Technology Sensitivity Analysis Based on η-ρ-Pareto Front

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    ► Converter Performance Evaluation Based on η-ρ-Pareto Front

    ■ Performance Indicator

    ■ Design Space Diversity

    Design Variables & Constraints Related to Two Adjacent Points of the Pareto Front

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    ► Converter Performance Evaluation Based on η-ρ-Pareto Front

    Triple-Interleaved TCM Rectifier (56kHz)

    Double-Interleaved Double-Boost CCM Rectifier (450kHz)

    Double-Interleaved Double-Boost CCM Rectifier (33kHz)

    Triple-Interleaved TCM Rectifier (33kHz)

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    3D-Performance Space Including Costs

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    ■ Priorities 1. Costs 2. Costs 3. Costs

    4. Robustness 5. Power Density 6. Efficiency …………

    ─ Basic Discrepancy (!) * Most Important Industry Figure ”Unknown” to Univ. * Costs Not Considered in Applic.-Oriented Research

    ► Industry Perspective

    + Modularity / Scalability / Ease of Integration into Systems / etc.

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    ► Requirement for Quantitative Cost Models

    ─ Considering Only Volumes is Insufficient ─ Initial / Manufacturing Costs ─ Life Cycle Costs

    ─ Complexity / Reliability ─ Functionality

    State-of-the-Art Si IGBTs

    Advanced SiC MOSFETs

    ■ Advantages / Competitiveness of SiC Can Only be Revealed Considering Full System Costs

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    ■ σ: kW/$

    ► Converter Performance Evaluation Based on η-ρ-σ-Pareto Surface

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    ► Converter Performance Evaluation Based on η-ρ-σ-Pareto Surface ■ Maximum σ [kW/$], Related Efficiency and Power Density ■ Definition of “Technology Node” (η*,ρ*,σ*,fP*)

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    Modeling of Components

    Efficiency Power Density

    Costs

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    Power Semiconductors and Cooling Systems

    * Cond./Switching Loss Models * Thermal Models

    * Cost Models

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    ► Modeling Tasks and Design Variables

    ■ Thermal Model

    ■ Design Routine

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    ► Conduction Losses ■ MOSFET Conduction Losses

    Source: CREE

    Take from Data Sheet

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    ► Switching Losses

    ■ Measurement Results Layout-Dependent / Measurements Required

    ■ MOSFET Switching Losses

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    ► Semiconductor Costs

    Fitted Manufacturer Data for MOQ = 50k

    ─ Distributors ─ Better: Manufacturer Data @ MOQ = const.

    ■ Source of Cost Data

    ■ Cost Model ─ Parameters Based on Fitted Data

    ─ Inter-/Extrapolation of Semiconductor Costs

    MOQ … Minimum Order Quantity

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    ► Cooling System Modeling

    Geometry, Fans

    ─ Experimental Verification

    ► ─ Fluid Dynamics Models ─ Thermodynamics Models

    ─ Heat Sink Dimensions ─ Heat Sink Material ─ Fan Type ─ # of Fans

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    ► Cooling System Costs

    ─ Distributors ─ Better: Manufacturer Data @ MOQ = const.

    ■ Fan Costs

    ■ Cost Model for Heat Sinks

    ─ Based on Fitted Manufacturer Data

    ─ Fitted Manufacturer Data for MOQ = 10k

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    Magnetic Components * Core/Winding Loss Models

    * Reluctance Models * Thermal Models

    * Cost Models

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    ► Modeling Tasks and Design Variables ■ Design Routine

    www.pack-feindraehte.de www.jiricek.de

    http://www.ferroxcube.com/prod/assets/ecores.htm

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    ► Core Losses ■ Improved2 Steinmetz Equation

    ─ Improvement (1): Arbitrary Waveforms ─ Improvement (2): Operating Point-Dependent Parameters

    ─ Requires Extensive Measurements ─ Sweeps: f, Bac, Bdc, Tcore, lag

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    ► Winding Losses

    ■ Winding Losses

    ─ Skin and Proximity Effects Contribute to Winding Losses

    ─ Frequency-, Temperature- and Geometry-Dependency

    ─ Analytical Formulas for Fskin, Gprox and Hext Available

    50 Hz 5 kHz 20 kHz 100 kHz

    Skin Effect ►

    Proximity Effect ►

    Hext

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    ► Thermal Models

    ■ 3D Equiv. Thermal Network

    ─ Conduction ─ Radiation ─ Natural Convection

    ■ Heat Transfer Mechanisms ─ Avoid Overheating ─ Improve Loss Calculation

    ■ Significance

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    ► Verification of Multi-Physics Models

    ■ Setup ■ Test Inductors

    ■ Loss Model Verification ■ Thermal Model Verification

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    ► Magnetics Costs

    Example: Manufact. Data for Litz Wire for MOQ = 1 Metric Ton

    ■ Source of Data ─ Core Manufacturers ─ Conductor Manufacturers ─ Suppliers of Magn. Components

    ■ Model ►

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    Capacitors * Loss Models * Cost Models

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    ► Modeling Tasks & Design Variables

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    ► Capacitor Losses ■ Electrolytic Capacitor Losses

    ─ Take from Data Sheet

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    ► Capacitor Costs ►

    Fitted Manufact. Data for MOQ = 50k ─ Distributors ─ Better: Manufact. Data @ MOQ = const.

    ■ Source of Cost Data

    ■ Cost Models

    ─ Parameters Based on Fitted Data

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    Converter Optimization Example I

    Isolated DC/DC Converter Topologies/Modulation Schemes

    Materials/Components Optimization

    η-ρ-σ-Pareto Surface Hardware Prototype

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    ► Application

    ─ Renewable Energy Sources, Local Storage Systems ─ DC Distribution Bus ─ Intelligent Load Management Algorithm ─ Possible Element of Future Smart Grid System ─ DC Microgrids Already Employed in Data Centers, Ships, Airplanes

    ■ Next Generation Residential Energy Management System

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    ► Bidirectional Wide Input Voltage Range Isolated DC/DC Converter

    ─ Bidirectional Power Flow ─ Galvanic Isolation ─ Wide Voltage Range ─ High Partial Load Efficiency

    ■ Universal DC/DC Converter

    Structure of DC Microgrid ►

    Universal DC/DC Converter

    ─ Reduced System Complexity ─ Lower Overall Development Costs ─ Economies of Scale

    ■ Advantages

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    ► Converter Topologies

    ■ Conv. 3-Level Dual Active Bridge (3L-DAB)

    ■ Advanced 5-Level Dual Active Bridge (5L-DAB)

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    ► Modulation Schemes ■ 3-Level Dual Active Bridge ■ 5-Level Dual Active Bridge

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    ► Modulation Schemes

    ■ 3-Level Dual Active Bridge ■ 5-Level Dual Active Bridge

    ─ Significantly Lower RMS Currents of 5L-DAB Due to Higher DOF of Modulation

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    ► Modulation Schemes - Zero Voltage Switching (1)

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    ► Modulation Schemes - Zero Voltage Switching (2)

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    ► Modulation Schemes - Zero Voltage Switching (3)

    ► ►

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    ─ Lσ Usually Provides Not Enough Charge ─ Add Lm for Additional (Reactive) Current ─ At Low Power and/or Too Short Dead Time Intervals Still not Sufficient Partial ZVS / Add. Switching Losses

    ■ Achieving ZVS

    ► Modulation Schemes - Zero Voltage Switching (4)

    ■ 3-Level Dual Active Bridge

    ■ 5-Level Dual Active Bridge

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    ► Components and Materials

    ─ Inexpensive ─ 1200 V ─ Cond. Losses Not Scalable ─ No ZVS Possible ─ Tail Currents ─ ZCS Difficult to Achieve

    ■ Si IGBT

    ─ Conduction Losses Scalable ─ ZVS But Non-Zero Sw. Losses (!) ─ Large Specific Coss ─ Only 650 V ─ NPC Half-Bridge Necessary ─ Increased Part Count

    ■ Si SJ MOSFET

    ─ Cond. Losses Scalable ─ Very Low ZVS Losses ─ 1200 V ─ Low Specific Coss ─ Costs

    ■ SiC VD-MOSFET

    ■ Power Semiconductors

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    ► Overview of Components and Materials

    ─ CREE SiC MOSFET 80 m 1200 V ─ 2 x on Variable Voltage Side ─ 1 x on Fixed Voltage Side

    ─ CREE SiC MOSFET 80 m 1200 V ─ Scaled 600 V SiC Switch ─ Variable Chip Sizes ─ Same Total Semicond. Cost as 3L-DAB

    ─ Optimized Aluminum Heat Sinks ─ Range of Low Power DC Fans

    ─ EPCOS N87 Ferrite E & ELP Cores ─ Litz Wire with Range of Strand Diameters

    ─ EPCOS MKP DC Film Capacitors ─ 575 V and 1100 V Rated

    ■ 3-Level Dual Active Bridge ■ 5-Level Dual Active Bridge

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    ► Global Optimization Routine (1)

    ► Local Component Optimization

    Global System Optimization

    ► Dependent Global Design Variables

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    ► Global Optimization Routine (2)

    ─ Lσ ,Lm and n Determine Waveforms ─ Optimize with Chip Area Distribution

    ► Minimum Semiconductor Losses ► ZVS for All Operating Points ► Design Frequency: 50 kHz

    ■ Offline Design Variable Optimization

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    ► Optimization Results - Pareto Surfaces (1)

    ■ 3-Level Dual Active Bridge

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    ► Optimization Results - Pareto Surfaces (2)

    ■ 5-Level Dual Active Bridge

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    ► Optimization Results - Component Breakdown (1) ► 5L-DAB ► 3L-DAB

    ■ Lower RMS Currents Overcompensated by Low Chip Utilization ■ Higher 5L-DAB Conduction Losses Pc ■ Lower 5L-DAB Switching Losses Psw and Incomplete ZVS PiZVS Losses Due to More Uniform Current Waveforms

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    ■ Higher 5L-DAB Volume Mainly Due to Higher Capacitance for Midpoint Balancing ■ Increase of Magnetics Volume at High fsw Due to High Core Losses ■ Auxiliary Based on Prototype – Industrial Auxiliary Approx. Half the Volume

    ► Optimization Results - Component Breakdown (2) ► 5L-DAB ► 3L-DAB

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    ■ Higher fsw Allows for Lower Volume of Passives ■ However, Magnetics Require More Expensive Litz Wire, Capacitors are Inexpensive ■ Main Costs are Semiconductors and Auxiliary ■ Auxiliary (incl. Gate Drivers) Based on Prototype – Industrial Auxiliary Approx. Half the Costs

    ► 5L-DAB ► 3L-DAB

    ► Optimization Results - Component Breakdown (3)

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    ► Experimental Verification (1)

    ■ Hardware Prototype of Three-Level Dual Active Bridge (3L-DAB)

    P = 5 kW Vi = [100, 700] V Vo= 750 V fsw = 50 kHz Vbox = 2.8 dm3 (171 in3)

    ■ Power Density 1.8 kW/dm3 ■ Peak Efficiency 98.5% ■ Average Efficiency 97.6%

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    ─ Peak Efficiencies of 98.8% (Without Auxiliary) and 98.5% (incl. 10W Aux. Power) ─ High Efficiency Over Extremely Wide Parameter Range ─ ZVS in Most Operating Points

    ► Experimental Verification (2)

    ■ Very High Efficiency Despite High Functionality

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    ─ Average Error 2.5% ─ Maximum Error 7.8% ─ Widely Varying Mix of Loss Contributions

    ► Experimental Verification (3)

    ■ Very High Model Accuracy

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    ─ Supports Calculated Loss Modeling ─ Temperatures Generally Underestimated Wiring, Thermal Coupling

    ► Experimental Verification (4) ■ High Accuracy of Thermal Modeling

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    ─ Non-Linear Switching-Transitions ─ Incomplete ZVS Transitions

    ► Experimental Verification (5) ■ Accuracy Prediction of Voltage and Current Waveforms

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    ─ Prototype Development

    * No Optimization Routine * Target Power Density of 2.0 kW/dm3

    ─ Improvements with Advanced Multi-Objective Optimization * 0.3% Higher Eff. @ Same Volume/Costs * 40% Lower Volume and 20% Lower Costs @ Same Efficiency

    ► Experimental Verification (6) ■ Comparison to Pareto Surface

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    ► Conclusions Example I

    ■ 3L-DAB Clearly Superior over 5L-DAB

    ─ More Efficient (Chip Area Utilization) ─ Higher Power Density (Capacitors) ─ Lower Costs (Gate Drivers) ─ Much Simpler Reliability ─ High Functionality (Voltage Range, Galv. Isolation, Bidir.) @ High Efficiency ─ Could not be Achieved w/o SiC

    ■ ZVS

    ─ Difficult to Achieve at Low Load and/or High Switching Frequencies ─ Parasitic Capacitances (Semicond. Package (!) to Heat Sink, Magnetics, PCB Layout) Become Highly Important Due to Required Add. Charge

    ■ Usefulness of Multi-Objective Optimization Routine

    ─ High Accuracy of Models ─ Improvements for Prototype Revealed

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    Converter Optimization Example II

    DC/AC PV Application Topologies/Modulation Schemes

    Materials/Components Optimization

    Pareto Surfaces LCC Post-Processing

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    ■ Advancements in PV Converter Design and Development

    ─ 1990s – 2000s

    * Main Focus on Efficiency * Improvements from 90% to >98% ─ 2010s

    * Econom. Downturn and Slower Market Growth * Main Focus on Costs (!)

    1992 η=93%

    2007 η=96%

    2011 η=99%

    Future?

    ■ Ongoing Discussion on Whether and How SiC Can Improve PV-Inv. Performance (!)

    ► Motivation (1)

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    ■ Opportunities of SiC in PV Applications

    (1) Same Sw. Frequ. and Higher Eff. @ Same Volume Costs? (2) Higher Sw. Frequ. and Lower Volume @ Same Eff. Costs? (3) Other Topologies/Modul. Schemes (e.g. Higher Voltages, ZVS Operation, 2-Level, etc…)

    5kW 2-Level w/o DC/DC η=96.8% @ 48kHz η=93.0% @ 144kHz = 0.83 kW/dm3

    ■ State of Research

    ─ Only Very Few Contributions with Multi-Objective Optimization ─ Mostly Case Studies of Single Prototype and Single Frequency, Main Inductance etc.

    ► Systematic Multi-Objective Optimization Imperative!

    Source: SMA Source: Fraunhofer ISE

    ► Optimal?

    20.5kW 3-Level w/o DC/DC η=98.6% @ 16kHz = 0.17 kW/dm3 @ 52kg

    ► Motivation (2)

    ► Optimal?

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    ► Application and Goals

    ─ Single-Input/Single-MPP-Tracker Multi-String PV Converter ─ DC/DC Boost Converter for Wide MPP Voltage Range ─ Output EMI Filter ─ Typical Residential Application

    ■ Systematic Multi-Objective η-ρ-σ-Comparison of Si vs. SiC ■ Exploit Excellent Hard- AND Soft-Switching Capabilities of SiC ■ Find Useful Switching Frequency and Current Ripple Ranges ■ Find Appropriate Core Material

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    ■ All Si IGBT 3-Level PWM Inverter (3L-PWM)

    ► Topologies - Converter Stages

    ■ All SiC MOSFET 2-Level Double- Interleaved TCM- Inverter (2L-TCM)

    ■ All SiC MOSFET 2-Level PWM Inverter (2L-PWM)

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    ► Topologies - Filter Stages

    ■ 2-Stage DM & CM Filter for 2L-PWM and 3LP-WM

    ■ 2-Stage DM & CM Filter for 2L-TCM ■ TCM Inductor Acting as DM & CM Inductance

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    ► Modulation Schemes - PWM Converters ■ Three-Level PWM Inverter (3L-PMW)

    ─ Symmetric Boost Converter ─ Interleaved Operation ─ Part. Compensation of LF DC-Link Midpoint Variation

    ─ 3-Level T-Type Converter ─ 3-Level PWM Modulation ─ 3rd Harmonic Injection

    ─ Standard DC/DC Booster ─ Standard Modulation

    ─ 2-Level Converter ─ 2-Level PWM Modulation ─ 3rd Harmonic Injection

    ■ Two-Level PWM Inverter (2L-PMW)

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    ► Modulation Schemes - TCM Converter

    ─ 2-Level/Double Interleaved Booster ─ Interleaved TCM Operation ─ Turn-Off of Branch in Partial Load

    ─ 2-Level/Double Interleaved ─ Interleaved TCM Operation ─ Turn-Off of Branch in Partial Load

    ─ ZVS for All Sw. Transitions ─ Variable fsw ─ Imin to Limit fsw ─ Losses Due to Imin @ Low Loads

    ■ Two-Level TCM Inverter (2L-TCM)

    ■ TCM Operating Principle

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    ► Components and Materials ►

    2L-TCM

    ─ 16 x CREE SiC MOSFET 80 m 1200 V

    ─ Optimized Al Heat Sinks ─ Range of Sanyo Low Power Long Life DC Fans

    ─ METGLAS 2605SA1 Amorphous Iron C Cores ─ Solid Round Wire

    ─ EPCOS MKP DC Film Capacitors 575V and 1100 V for MPP Cap. ─ EPCOS Long Life Al Electrolytic Capacitors 500 V for DC-Link Cap.

    ► 2L-PWM

    ─ 7 x CREE SiC MOSFET 80 m 1200 V ─ 1 x CREE SiC Schottky Diode 20 A 1200 V

    3L-PWM

    ─ 6 x Infineon Si IGBT H3 25 A 1200 V / PiN Diode ─ 6 x Infineon Si IGBT T&F 30 A 600 V / PiN Diode ─ 2 x Infineon Si IGBT T&F 30 A 600 V ─ Infineon Si PiN Diode 45 A 600 V

    ─ EPCOS N87 Ferrite E Cores ─ Litz Wire With Range of Strand Diameters

    Or

    ─ EPCOS X2 (DM/CM) and Y2 (CM) EMI Capacitors ─ Magnetics KoolMu Gapless Powder Cores / Solid Round Wire (DM) ─ VAC Vitroperm 250F/500F Nanocrystalline Toroid Cores / Solid Round Wire (CM)

    Filt

    er

    DC

    Caps

    M

    ain

    Indu

    ct.

    Cool

    ing

    Syst

    em

    Pow

    er

    Sem

    icon

    duct

    ors

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    ► Global Optimization Routine

    ■ Dependent Design Variables

    ─ Main Inductances Function of fsw and IL,maxpp ─ Filter Components Based on CISPR Class B

    ■ European Efficiency

    v ─ Add. Weighted for {525, 575, 625} V MPP Voltage

    ■ Independent Design Variables ─ 3L-PWM

    ─ 2L-PWM

    ─ 2L-TCM

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    ► Optimization Results - Pareto Surfaces (1)

    ─ No Pareto-Optimal Designs for fsw,min> 60 kHz ─ No METGLAS Amorphous Iron Designs

    ─ Pareto-Optimal Designs for Entire Considered fsw Range ─ No METGLAS Amorphous Iron Designs

    ─ Pareto-Optimal Designs for Entire Considered fsw Range ─ METGLAS Amorphous Iron and Ferrite Designs

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    ─ Compact Designs with Amorphous Core Material @ Low Ripples

    ─ Cheap Designs with Ferrite @ High Ripples Despite Larger Volume

    ■ 3L-PWM Core Material

    ─ Only Ferrite for 2L-TCM Due Large HF Excitations

    ─ Expected Result

    ■ 2L-TCM Core Material

    ─ Ferrite @ High Ripples Cheaper AND Smaller - Unexpected Result (!)

    ─ Amorphous Core Material too High Losses Already @ Low Ripples, High Flux Density Not Exploited

    ■ 2L-PWM Core Material

    ► Optimization Results - Pareto Surfaces (2)

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    ► Optimization Results – Component Breakdowns (1)

    ■ Semiconductor Losses Clearly Dominating (35 to 70%)

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    ► Optimization Results – Component Breakdowns (2)

    ■ DC Caps of 3L-PWM Largest Because of Midpoint Variation / Balancing

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    ■ Higher Gate Driver Costs (incl. in Aux.) of 3L-PWM Compensates Lower Si Semicond. Costs

    ► Optimization Results – Component Breakdowns (3)

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    ► Optimization Results - Semiconductor Losses

    ─ 2L-TCM

    * Wide Sw. Frequency Range / Lower Imin Results in Lower Conduction Losses ─ 2L-PWM

    * High Ripple Operation Lower Switching Losses Due ZVS ─ 3L-PWM

    * No ZVS for IGBTs * High Ripples are Causing Higher Cond. Losses

    ■ Sensitivities of Semiconductor Losses

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    ► Extension to Multi-Objective Optimization Approach

    ► Which is the Best Solution Weighting , , σ, e.g. in Form of Life-Cycle Costs (LCC)? ► How Much Better is the Best Design? ► Optimal Switching Frequency?

    ■ Performance Space Analysis ─ 3 Performance Measures: , , σ ─ Reveals Absolute Performance Limits / Trade-Offs Between Performances

    ■ LCC Analysis ─ Post-Processing of Pareto-Optimal Designs ─ Determination of Min.-LCC Design ─ Arbitrary Cost Function Possible

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    ─ Simple Life-Cycle Costs (LCC) Function for Mapping into 1D Cost Space ─ Initial Costs, Capital Costs and Lost Revenue (=Losses) Based on Net-Present-Value (NPV) Analysis

    ► Post-Processing

    ■ LCC – Analysis (1)

    ─ Assumptions

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    ► Post-Processing

    ─ 22% Lower LCC than 3L-PWM ─ 5% Lower LCC than 2L-TCM ─ Simplest Design ─ Probably Highest Reliability ─ Volume Advantage Not Considered Yet (Housing!)

    ■ Best System 2L-PWM @ 44kHz & 50% Ripple

    ■ LCC – Analysis (2)

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    ► Conclusions - Example II

    ■ SiC Systems Superior to State-of-The-Art Si System ─ Generally Higher Efficiency and Power Density of SiC ─ Initial Costs only Marginally Lower (SiC 2L-PWM) or Higher (SiC 2L-TCM) ─ TCM Operated System More Complex but With Highest Potential for Further Improvements

    ■ LCC Analysis to Determine Optimal Design ─ SiC 2L-PWM @ 44 kHz vs. Si 3L-PWM @ 18 kHz 22% Lower LCC of SiC ─ Initial Costs 5% Lower ─ Smaller Housing and Higher Reliability Not Considered Yet

    ■ Usefulness of Multi-Objective Optimization Routine ─ SiC can Improve , , and σ Simultaneously ─ Optimal Switching Frequencies Lower than in Previous Publications

    ─ Results/Findings Not Possible with -, - or --Optimizations or Single Prototypes

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    Conclusions ■

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    ► Overall Summary

    ■ Only Full System Level η-ρ-σ-Optimization Reveals Full Adv. of SiC (!) * Adv. Cannot be Identified for 1:1 Replacement or only 1D-Optimization ■ Rel. Low Optimum SiC Sw. Frequencies Calculated Compared to Literature * 44kHz for 2L-SiC Inverter vs. 18kHz for 3L-Si-IGBT Inverter * Frequently Incomplete Models Employed in Publications ■ Advantages of SiC Concerning Efficiency, Power Density & Costs * Lower System Complexity (2L vs. 3L) / Higher Reliability * Saving in Passives Overcompensates Higher SiC Costs

    ■ SiC Allows Massive η-ρ-Gain vs. 1200V Si for High-Frequ. DC/DC Converters * Design for Minim. Parasitic Cap. to Ensure ZVS @ Low Effort * Research on HF Magnetics / TCM ZVS Schemes / Packaging Mandatory

    ─ Higher Efficiency / Power Density @ Same Costs ─ Lower Complexity / Higher Reliability ─ Higher Functionality SiC

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    Multi-Domain Modeling /

    Simulation/ Optimization

    Hardware Prototyping

    20%

    80%

    2015

    2025

    80%

    20%

    ► Future Design Process

    ■ Main Challenges: Modeling (EMI, etc.) & Transfer to Industry

    ■ Reduces Time-to-Market ■ More Application Specific Solutions (PCB, Power Module, and even Chips) ■ Only Way to Understand Mutual Dependencies of Performances / Sensitivities (!) ■ Simulate What Cannot Any More be Measured (High Integration Level)

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    Future Research

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    ■ Consider Converters like “Integrated Circuits” ■ Extend Analysis to Converter Clusters / Power Supply Chains / etc.

    ─ “Converter” “Systems” (Microgrid) or “Hybrid Systems” (Autom. / Aircraft) ─ “Time” “Integral over Time” ─ “Power” “Energy”

    ─ Power Conversion Energy Management / Distribution ─ Converter Analysis System Analysis (incl. Interactions Conv. / Conv. or Load or Mains) ─ Converter Stability System Stability (Autonom. Cntrl of Distributed Converters) ─ Cap. Filtering Energy Storage & Demand Side Management ─ Costs / Efficiency Life Cycle Costs / Mission Efficiency / Supply Chain Efficiency ─ etc.

    ► Future Challenges

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    ► New Power Electronics Systems Performance Figures/Trends

    ─ Power Density [kW/m2] ─ Environm. Impact [kWs/kW] ─ TCO [$/kW] ─ Mission Efficiency [%] ─ Failure Rate [h-1]

    ■ Complete Set of New Performance Indices

    Supply Chain &

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    ► References [1] J. W. Kolar, J. Biela, S. Waffler, T. Friedli, U. Badstübner, "Performance Trends and Limitations of Power Electronic Systems,“ Invited Plenary Paper at the 6th International Conference on Integrated Power Electronics Systems (CIPS 2010), Nuremberg, Germany, March 16-18, 2010.

    [2] J. W. Kolar, F. Krismer, H. P. Nee, "What are the "Big CHALLENGES" in Power Electronics?,“ Presentation at the 8th Intern. Conf. of Integrated Power Electronics Systems (CIPS 2014), Nuremberg, Germany, February 25-27, 2014.

    [3] J. W. Kolar, U. Drofenik, J. Biela, M. L. Heldwein, H. Ertl, T. Friedli, S. D. Round, "PWM Converter Power Density Barriers,“ Proceedings of the 4th Power Conversion Conference (PCC 2007), Nagoya, Japan, CD-ROM, ISBN: 1- 4244-0844-X, April 2-5, 2007.

    [4] R. M. Burkart, J. W. Kolar, "Comparative Evaluation of SiC and Si PV Inverter Systems Based on Power Density and Efficiency as Indicators of Initial Costs and Operating Revenue,“ Proceedings of the 14th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL 2013), Salt Lake City, USA, June 23-26, 2013.

    [5] R. M. Burkart, J. W. Kolar, "Component Cost Models for Multi-Objective Optimizations of Switched-Mode Power Converters,“ Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE USA 2013), Denver, Colorado, USA, September 15-19, 2013.

    [6] R. M. Burkart, H. Uemura, J. W. Kolar, "Optimal Inductor Design for 3-Phase Voltage-Source PWM Converters Considering Different Magnetic Materials and a Wide Switching Frequency Range,“ Proceedings of the International Power Electronics Conference - ECCE Asia (IPEC 2014), Hiroshima, Japan, May 18-21, 2014.

    [7] P. A. M. Bezerra, F. Krismer, R. M. Burkart, J. W. Kolar, "Bidirectional Isolated Non-Resonant DAB DC-DC Converter for Ultra-Wide Input Voltage Range Applications,“ Proceedings of the IEEE International Power Electronics and Application Conference and Exposition (PEAC 2014), Shanghai, China, November 5-8, 2014.

    [8] M. Kasper, R. M. Burkart, G. Deboy, J. W. Kolar, "ZVS Condition and ZVS Switching Losses Revisited,“ IEEE Transactions on Industrial Electronics, submitted for review.

    [9] R. M. Burkart, J. W. Kolar, "η-ρ-σ Pareto-Optimization of All- SiC Multi-Level Dual Active Bridge Topologies with Ultra-Wide Input Voltage Range,“ IEEE Transactions on Power Electronics, submitted for review.

    [10] R. M. Burkart, C. Dittli, J. W. Kolar, "Comparative Life-Cycle-Cost Analysis of Si and SiC PV Converter Systems Based on Advanced η-ρ-σ Multi-Objective Optimization Techniques,“ IEEE Transactions on Power Electronics, submitted for review.

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    Johann W. Kolar is a Fellow of the IEEE and is currently a Full Professor and the Head of the Power Electronic Systems Laboratory at the Swiss Federal Institute of Technology (ETH) Zurich. He has proposed numerous novel PWM converter topologies, and modulation and control concepts and has supervised over 50 Ph.D. students. He has published over 650 scientific papers in international journals and conference proceedings and 3 book chapters, and has filed more than 120 patents. He received 21 IEEE Transactions and Conference Prize Paper Awards, the 2014 IEEE Middlebrook Award, and the ETH Zurich Golden Owl Award for excellence in teaching. The focus of his current research is on ultra-compact and ultra-efficient SiC and GaN converter systems, wireless power transfer, Solid-State Transformers, Power Supplies on Chip, and ultra-high speed and bearingless motors.

    ► About the Speakers

    Ralph M. Burkart received his M.Sc. degree in electrical engineering from the Federal Institute of Technology (ETH), Zurich, Switzerland, in 2011. During his studies, he majored in power electronics, electrical machines and control engineering. In the framework of his Master Thesis he designed and implemented a high-dynamic inverter system for active magnetic bearings in an ultra-high speed electrical drive system. Since 2011, he has been a Ph.D. student at the Power Electronic Systems Laboratory at ETH Zurich. His main research area is multi-domain modeling of power electronics components and multi-objective optimization of photovoltaic DC/DC and DC/AC converter systems employing SiC power semiconductors.

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    Thank You!

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    Questions