advanced implantation detector array (aida): update & issues presented by tom davinson on behalf...
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Advanced Implantation Detector Array (AIDA):Update & Issues
presented byTom Davinson
on behalf of the DESPEC-DSSD/AIDA collaboration
Tom DavinsonSchool of PhysicsThe University of Edinburgh
DESPEC: Implantation DSSD Concept
• Super FRS Low Energy Branch (LEB)• Exotic nuclei – energies ~50-150MeV/u• Implanted into multi-plane, highly segmented DSSD array• Implant - decay correlations• Multi-GeV DSSD implantation events• Observe subsequent p, 2p, , , , p, n … decays• Measure half lives, branching ratios, decay energies …
Implantation DSSD Configurations
Two configurations proposed:
a) 8cm x 24cm “cocktail” mode many isotopes measured simultaneously
b) 8cm x 8cm high efficiency mode concentrate on particular isotope(s)
DSSD Segmentation
We need to implant at high rates and to observe implant – decay correlationsfor decays with long half lives.
DSSD segmentation ensures average time between implants for given x,yquasi-pixel >> decay half life to be observed.
• Implantation profilex ~ y ~ 2cmz ~ 1mm
• Implantation rate (8cm x 24cm) ~ 10kHz, ~kHz per isotope (say)• Longest half life to be observed ~ seconds
Implies quasi-pixel dimensions ~ 0.5mm x 0.5mm
Segmentation also has instrumentation performance benefits
DSSD
Technology well established(e.g. GLAST LAT tracker)
• 6” wafer technology 10cm x 10cm area
• 1mm wafer thickness
• Integrated components a.c. coupling polysilicon bias resistors … important for ASICs
• Series strip bonding8.95 cm square Hamamatsu-Photonics SSD before cutting from the 6-inch wafer. The thickness is 400 microns, and the strip pitch is 228 microns.
AIDA: DSSD Array Design
• 8cm x 8cm DSSDscommon wafer design for 8cm x 24cm and 8cm x 8cm configurations
• 8cm x 24cm3 adjacent wafers – horizontal strips series bonded
• 128 p+n junction strips, 128 n+n ohmic strips per wafer• strip pitch 625m• wafer thickness 1mm• E, Veto and 6 intermediate planes
4096 channels (8cm x 24cm)• overall package sizes (silicon, PCB, connectors, enclosure … )
~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm
Implantation depth?Stopping power?Ge detector?Calibration?Radiation damage?Cooling?
courtesy B.R
ubio
AIDA: Instrumentation Requirements
Large number of channels required, limited available space and cost mandateuse of Application Specific Integrated Circuit (ASIC) technology.
Requirements
• Selectable gain: low 20GeV FSR (use reset) :
intermediate 1GeV FSR :
high 20MeV FSR• Noise ~ 5keV rms.• Selectable threshold: minimum ~ 25keV @ high gain ( assume 5 )• Integral and differential non-linearity• Autonomous overload recovery ~s• Signal processing time <10s (decay-decay correlations)• Receive timestamp data• Timing trigger for coincidences with other detector systems
DSSD segmentation reduces input loading of preamplifier and enablesexcellent noise performance.
AIDA: ASIC Concept
courtesy I.Lazarus, CCLRC DL
- Example design concept- 1 channel of 16 channel ASIC (shown with external FPGA and ADC)- FEE-integrated DAQ- Digital data via fibre-optic cable to PC-based data concentrator/event builder
AIDA: General Arrangement
DSSD/Kapton Package
ASIC ADC Virtex 4FX FPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
16 ch ASIC (with ADC?)
Estimated size: 80x220mm, Estimated power 25W per 128ch (800W total)
128 detector signals in; 1 data fibre out
EthernetMAC
ASIC ADC
ASIC ADC
ASIC ADC
ASIC ADC
ASIC ADC
ASIC ADC
ASIC ADC
AIDA: 128 channel FEE Card Concept
courtesy I.Lazarus, CCLRC DL
Front End Electronics
Data output stage standard format andoutput medium e.g.10G Ethernet fibre
Correlate by timestamp
Clock andTimestamp
BUTIS CommonClocks
10/200MHz<100ps/km
Slow Control Common database
loaded intolocal
controllersover Ethernet Detector
DetectorHV etc.
NUSTAR: Common DAQ Interfaces
courtesy I.Lazarus, CCLRC DL
Slow Control
BUTIS TimestampsData Output Switch
PC FarmASIC ADCASIC ADC Virtex 4FX
FPGA Power Supplies and other
components
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
AIDA: System Concept
courtesy I.Lazarus, CCLRC DL
AIDA: Current Status
• Edinburgh – Liverpool – CCLRC DL – CCLRC RAL collaboration
- 4 year grant period- DSSD design, prototype and production- ASIC design, prototype and production- Integrated Front End FEE PCB development and production- Systems integration- Software development
Deliverable: fully operational DSSD array to DESPEC
• Proposal approved EPSRC Physics Prioritisation panel meeting April 2006
• EPSRC award announcement letters received June 2006
• Detailed specification development has commenced
• M0 – specification finalised and critical review
Resources
Cost
• Total value of fEC proposal c. £2.3M (incl. PG c. £2.6M)
Support Manpower
• CCLRC DL c. 4.2 SY FEE PCB DesignDAQ h/w & s/w
• CCLRC RAL c. 3.5 SY ASIC Design & simulationASIC Production
• Edinburgh/Liverpool c. 4.5 SY DSSD Design & productionFEE PCB productionMechanical housing/support
• Platform grant support CCLRC DL/Edinburgh/Liverpool
AIDA: Workplan
AIDA: Project Partners
• The University of Edinburgh (lead RO)Phil Woods et al.
• The University of LiverpoolRob Page et al.
• CCLRC DL & RALJohn Simpson et al.
Project Manager: Tom Davinson
Further information: http://www.ph.ed.ac.uk/~td/AIDA
Outstanding Issues
• ThresholdHow low is low enough?
• Package size10cm x 26cm x 4cm (10cm x 10cm x 4cm)
• Range of implantation energies and species50-150MeV/u … ?Corresponding ranges in Si
U 0.6 - 3.0mmSn 0.8 - 4.5mmNi 1.0 – 6.5mm
• Energy and time resolution (decay)< 10keV FWHM< 10ns FWHM
• Energy and time resolution (implant)1% … ??
• External trigger (to gamma/neutron/whatever arrays)prompt? delayed? time resolution?
Acknowledgements
Presentation includes material from other people.
Thanks to:Ian Lazarus (CCLRC DL)Haik Simon (GSI)Berta Rubio (IFIC, CSIC University of Valencia)