advanced electronic equalization and signal processing for...

All Rights Reserved © Alcatel-Lucent 2006, #####

Advanced electronic equalization and signal

processing for optical communication

Fred BuchaliAlcatel-Lucent, Research & Innovation, Stuttgart, [email protected]

All Rights Reserved © Alcatel-Lucent 20072

Outline

Outline� Introduction� Signal impairments in optical communication systems� Electronic equalization schemes

� FFE and DFE� Viterbi equalizer

� Advanced electronic equalization concepts� Conclusions

Advanced electronic equalization and signal processing for optical communication


Introduction

� State of the art optical transmission systems are operated close to optimum

� Typical system margins are in the range of few dB in OSNR (1dB ... 3dB) allowing a very low degradation, only

� Degradation of system performance is due to limited perfection of transmitter, fiber link and receiver including ageing

� Drivers for future� Increase of data volume� Decrease of cost� Availability of appropriate microelectronics technology


Signal impairments in optical communication systems



Optical transmission systems suffer fromLimitation of system performance by signal impairments� transmitter� transmission channel� receiver

Task of electronic dispersion compensation (EDC)� mitigation of all impairments to improve system performance

Transmitter ReceiverTransmission

channel



Impairments from transmitter� Limited bandwidth

� Extinction ratio (9 ... 12 dBm) � Chirp


channel



Impairments from transmission channel� Noise accumulation� Limitation bandwidth of optical channel 40 Gb/s w. 50 GHz spacing� Chromatic dispersion 10 Gb/s - uncompensated links

40 Gb/s - decreased CD tolerance� PMD especially in older fibers� SPM if launch power > 0 dBm� XPM� FWM


channel



Impairments from receiver

� Limited bandwidth

� Noise (w. and w/o. optical amplifiers)


channel


Electronic equalization schemes



Transmitter and receiver equalization schemes

muxelectronicdispersion compens. o

etransmitter

CDRdemux

electronicdispersion compens.

o e

receiver



Transmitter and receiver equalization schemes

� Adaptation

muxelectronicdispersion compens. o

etransmitter

CDRdemux

o e

receiver

Adaptation via back channel

Adaptation via fixed settinglook up table

mux oe

transmitter

CDRdemux

electronicdispersion compens.

o e

receiver

Adaptation with internal feedback

� For many applications EDC in receiver is optimum



Transmitter based EDC - Electronic predistortion

� Generation of precompensated optical field

� Independent modulation of I and Q

Data Processor(linear & nonlinear)

SP

C

Data in

(electrical)

DAC

DAC

DF

DF 6

6

90

Data out

(optical)

MZ modulators

Opticalsource

DriversFiltersDigitalfilters (opt)

Digital processor (FIR filter)

6-bit converters

I

Q

PMF

� Chipset solution, but very complex Tx� Adaptation: feedback via reverse channel � More than 5000 km w/o. DCM

� J. McNicol et al., "Electrical Domain Compensation of Optical Dispersion", proc. OFC'05, Anaheim, OthJ3.

� Sensitivity to non-linearity's� A. Klekamp, “Nonlinear Limitations of Electronic Dispersion Pre-Compensation by Intrachannel

Effects“ OFC‘06, OWR1, see also OWB1 OFC’06



Receiver based EDC

� Analog and digital approaches after o/e conversion

C6

Tc

C7

�

C0

Tc

C1CUref

TB

-+

B1

FFE DFE

.....

ADC DSP - Viterbi equalizer

channel estimation

� Application of FFE and DFE

� Several prototypes for 10 Gb/s

� First circuits reported at 40 Gb/s� StrataLight, Alcatel

� ADC

� Equalization of signal in DSP (Viterbialgorithm)

� First prototypes reported at 10 Gb/s� CoreOptics, Intersymbol Comm.



0

1

2

3

4

5

6

7

0 500 1000 1500 2000 2500 3000 3500 4000

GVD [ps/nm]

OS

NR

pen

alty

[dB

]

FFE9/50ps+DFE

VE 20GS/s

VE 10GS/s

standardreceiver

0

1

2

3

4

5

6

7

0 25 50 75 100 125 150

DGD [ps]

OS

NR

pen

alty

[dB

]

FFE9/50ps+DFE

VE 20GS/s

VE 10GS/s

standardreceiver

Comparison of analog and digital equalizers

� Sensitivity to GVD and PMD for NRZ at 10 Gb/s

� Standard receiver with 5 GHz bandwidth� VE 10 GS/s with BW of 3.5...5 GHz, 20 GS/s w. 6...8 GHz� Similar behaviour for equalizers for low distortions or low penalty range� VE outperforms FFE/DFE at higher distortions


FFE and DFE

Realization of analog equalizersFFE DFE

C

TB

-+ DATA out

analog feedback

� tap delay line (½ to 1 bit period delay)

� bipolar tap weights

� tap number: 3 ... 5 sufficient

� low number of building blocks

� 1 bipolar tap weight, 1 bit period delay

� FFE and DFE are feasible up to 40 Gb/s, technology CMOS and SiGe

� 40 Gb/s FFE with 5 taps� SiGe technology� area 2.0 x 1.5 mm2, <2W power diss.


FFE and DFE

10-4

10-3

10-1

10-2

3 5 7 9 11 13

OSNR [dB]B

ER

FFE - LMS

FFE/DFE - LMS

FFE/DFE - LMN4th order (6th and 8th)

B2B

Xn-1

Adaptation of analog equalizers

� LMS algorithm for FFE/DFE

� LMS algorithm not optimum for optical noise loaded signals� LMN improves performance, difficult for implementation� Highest speed adaptation for FFE and DFE up to MHz range


FFE and DFE

Eye monitor feedback for analog equalizers

EX OR

decision circuits

C0

recovered data

dtUeye

C1

U0

U1

data input

PC

C6

Tc

C7

�

C0

Tc

C1CUref

TB

-+

B1

FFE DFE

.....

Adaptation

� Eye monitor available for 10 and 40 Gb/s application

� Requires sequencial adaptation of tap weights

� Improved performance of EDC at reduced adaptation speed

PER= 10-3...10-1


DGD [ps]0 2 4 6 8 10 12 14 16 18 20

OS

NR

Pen

alty

at B

ER

=10-5

[dB

]

-1

0

1

2

3

4

5

6

7

FFE and DFE

Performance of analog equalizer realization (FFE)� 42.7 Gb/s NRZ � Simulations with optimum adaptation� Experiments with manually optimized parameters

� Performance close to theoretical limits� Suitable for transponder integration

experiment

simulation

w. eq.w/o. eq.


Viterbi equalizer

Digital equalization: Viterbi equalizer at 10 Gb/s


channel estimation

� ADC with 3 to 4 bit resolution

� Sampling with 10 to 20 GS/s

� Viterbi equalization with 4 states

� Determination of most probable sequence


Viterbi equalizer

ADC with flash architecture� 10 GS/s ADCs are feasible� beyond 10 GS/s

� 3 bit at 20 GS/s in SiGe, CoreOptics� 8 bit 20 GS/s in 0.18µm CMOS

Agilent, power dissipation 10 W� 3 bit 40 GS/s in 0.12µm SiGe

TelASIC, power dissipation 3.8 W

� not reported: >>10 GHz bandwidth

� 40 Gb/s requirements� DQPSK: 20 GS/s, 15 GHz bandwidth� NRZ and PSBT: 40 GS/s, 30 GHz bandwidth

S&H

Vref linear to binary encoder

Sele

ctorA

B

S Out

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

-Vref

Sele

ctorA

B

S Out

Sele

ctorA

B

S Out

Sele

ctorA

B

S Out

Comp

Comp

Comp

Comp

Comp

Comp

Comp

flash ADC


BMU ACSUIN OUT

TBU

� Simulations: 512ps+15 ps+512 ps +80 ps (CMOS 130 nm)� Sum: 1,119 ns -> max clock frequency of subrate: 890 MHz

� Parallelization of algorithm necessary

Architecture of Viterbi core

� ACS is most time critical building block in realization

Viterbi equalizer

Branch metric

State metric


Viterbi equalizer

Parallel architecture of Viterbi equalizer

� Minimized Method (Sliding Window method very similar)

n bits in parallel2 x trace back length

3 x trace back length

1st best state estimation

2nd best state estimation

Trace back

Input 10 Gb/s

Output 10 Gb/s

Proc

essi

ng 6

22 M

b/s


Viterbi equalizer

Parallel architecture of Viterbi equalizer

� Minimized Method (Sliding window method very similar)

2 x trace back length

2 x m x trace back length


Viterbi equalizer

x = number of states

Parallel architecture ofViterbi equalizer

� complexity of full matrix


Viterbi equalizer

Parallel Viterbi equalizer realization at 10 and 40 Gb/s: � Minimized method or Sliding window: estimation of building block count

Boundary conditions Hardware effort

Trace back lengthof algorithm

Subrate[MHz]

No. ofACS

No. ofregisters

4 622 128 57610 Gb/s 8 622 128 1152

4 1244 256 115240 Gb/s 8 1244 256 2304

� High number of building blocks, but pure digital

� Consider: 256 ACS units - power dissipation < 2 W


Viterbi equalizer

VE

recovered data

2 bit reg.

MUX

....

00

11

00

01, 10

11

conditional histograms

....

pdf00

pdf11

noisy eye diagram of distorted signal

00

0110

11

(75ps DGD)

“channel model” for VE adaptation

delay

Adaptation of Viterbi equalizer

� Pdf’s can be extracted from conditional histograms

� Adaptation is realized as digital subfunction

� Max. speed up to 1MHz


Viterbi equalizer

-1

0

1

2

3

4

5

6

0 20 40 60 80 100DGD [ps]

pena

lty @

1E-

4 [d

Bm

] experiment

simulation

Performance of digital equalizers� 10.7 Gb/s, NRZ� Automatic adaptation in experiment

� Performance close to theoretical limits� Suitable for transponder integration

A. Faerbert et al., " Performance of a 10.7 Gb/s Rx withDigital Eq. using MLSE", ECOC 2004, Th4.1.5, 2004.


Advanced equalization schemes


Advanced EDC concepts

ADC with 1 or 2 S/Bit


00

01

10

11


channel estimation

Viterbi equalization with oversampling

� Application of 2 S/bit - already realized by CoreOptics

Correlation sensitive algorithm

� Cope with noise correlation in bandwidth limited systems (OFC’05, OFO 2) see also OWB6 OFC‘06




ADC with 1 or 2 S/Bit ADC

with 1 or 2 S/BitADC

with 1 or 2 S/Bit

t

+p/4

t

-p/4

� DQPSK requires 2 receivers

� joint symbol VE for both channels (I and Q)

Viterbi equalization for 2 input signals (e.g. DQPSK)

� M. Cavallari, OFC‘04, TuG2


EDC applications

EDC for DPSK and DQPSK modulation format at 40 Gb/s

BER=10-3

0

2

4

6

8

10

12

14

0 100 200 300 400 500

chromatic dispersion [ps/nm]

OSN

R p

enal

ty [d

B]

DPSK simple receiverDPSK Viterbi

NRZ simple receiverNRZ ViterbiDQPSK simple receiver

DQPSK Viterbi

DQPSKNRZDPSK

� Lower improvement of performance by EDC for DPSK and DQPSK


EDC applications

EDC for advanced Viterbi equalization of DQPSK- very attractive for 40 Gb/s� System simulations for DQPSK

� M. Cavallari, OFC‘04, TuG2

� CD tolerance of 350 ps/nm seems to be possible at 40 Gb/s

250 500 750 @ 20 Gbaud / 40 Gb/s GVD [ps/nm]

feasible approach w. 2x20 GS/s @ 2dB penalty

OSN

R [d

B]


EDC applications

EDC in PSBT systems (very attractive for 10 and 40 Gb/s systems)� Viterbi: 1 S/bit - 40 GS/s feasibility has to be proven

2 S/bit - not feasible� Simulations w. standard PSBT @ 10.7 Gb/s (OFC 05, OThJ4)

� Limited improvement by EDC� Tolerance: >200 ps/nm @ 40 Gb/s

40 GS/s

>200 ps/nm @ 2 dB penalty

GVD[ps/nm] @ 43 Gb/s250125

80 GS/s



Improved architecture for FFE/DFE� Application of non-linear taps

C. Xia, “Performance enhancement for duobinary modulation through nonlinear electrical equalization”, ECOC 2005, Glasgow, 4.2.3.

� Non-linear FFE/DFE outperforms linear FFE/DFE and VE� Requirements on circuit, adaptation?


Coherent DSP equalization

• conversion of phase / polarization information of distorted signal into the electricaldomain

• numerical equalization (DSP) of CD, PMD, (SPM) after analog-to-digital conversionpossible (ADC: 2 samples/symbol)

phase diversityoptical hybrids (OH)

DSP EQ.

ADC

ADC

ITE

ADC

ADC

PBSTE

TM

QTE

ITM

QTM

local oscillator laser (LO)

�/2

�/2

polarizationdiversity

polarizationbeam splitter

I = ETEsignal x ELO

Q = ETEsignal x (ELO x ei�/2)

e.g.:

• S. Tsukamoto et al., OFC/NFOEC2006, OWB4: D?QPSK, 20Gb/s

• S.J. Savory et al, ECOC 2006, Th2.5.5: 40G pol. multiplexedQPSK, 10Gbaud

• S. Tsukamoto, K. Kikuchi et al., ECOC 2006, Mo4.2.1


CD Equalization DQPSK, PM-DPSK heterodyne equalizer / OFDM

OFC 2007

Mitigation of CD (>3000 km SMF) and PMD (up to 25 ps DGD) possible


Tx and Rx signal processing

OFDM with Tx and Rx signal processing

� OFDM setupS/

P

IFFT

1

127128129

256255

. . .

. . .

1

256

. . .

2

code

r

imag

P/S

real

P/S

DA

CD

AC

cos

sin +

MZI

bias

filter

AD

CA

DC

cos

sin

imag

S/P

real

S/P

FFT

1

127128129

256255

P/S

1

256

. . .

2

deco

der

. . .

fiber linkoptical

amplifier

� IFFT and DAC in Tx

� ADC and FFT in Rx

� Realization of all components seems to be feasible


Tx and Rx signal processing

Simulations� A. Lowery, OFC 2006, Anaheim, PDP39

32x10 Gb/s 4000 km without DCM, limit of transmission length by nonlinearities and noise� W. Shieh, Electronics Letters, 42(11)2006

Coherent optical OFDM: improvement of sensitivity, but same dispersion tolerancesNo penalties by CD up to 34.000 ps/nm dispersion

W. Shieh A. Lowery

� I. Djordjevic, IEEE PTL 18(15)2006100 Gb/s @ 25 GHz optical bandwidth, comparison of QPSK and 16-QAM, QPSK outperforms 16QAM, up to 2900 km simulated

Demonstration� 20 Gb/s tranmission with offline processing by KDDI and Monash Univ. (OFC 2007, PDP)


Conclusions

� Performance of electronic processing schemes are close to theoretical limits even at 40 Gb/s

� Realization of analog and digital equalizers are feasible

� Required microelectronics technology is available

� Electronic signal processing increases dispersion tolerances and system robustness

� Suitable approach for channel based application in commercial transponders


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