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Advanced Design System 2004A

Quick Sta r t

September 2004

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NoticeThe inform at ion cont ained in t his docum ent is subject to cha nge without notice.

Agilent Techn ologies ma kes n o warr an ty of an y kind with r egard t o th is mat erial,including, but n ot limited t o, the implied war ra nt ies of mer cha nt ability an d tn essfor a pa rt icula r p ur pose. Agilent Techn ologies sh a ll not be liable for er rors cont ain edher ein or for incidenta l or consequen tial da ma ges in conn ection with th e fur nishing,perform an ce, or use of this m at erial.

Warranty

A copy of the specic warr an ty t erm s t ha t apply to th is softwar e product is availableup on r equest from your Agilent Techn ologies rep res ent a tive.

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Agilent Technologies395 Pa ge Mill RoadPalo Alto, CA 94304 U.S.A.

Copyright 1998-2004, Agilent Technologies. All Right s Res er ved.

Acknowledgments

Mentor Gra phics is a t ra dema rk of Mentor Gra phics Corporat ion in th e U.S. andoth er coun tr ies.

Microsoft , Windows , MS Windows , Windows NT , an d MS-DOS ar e U.S.

registered trademarks of Microsoft Corporation.

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Contents1 Using Projects

Creating Projects ...................................................................................................... 1-2Opening Projects ...................................................................................................... 1-3Sharing Projects ....................................................................................................... 1-4

2 Using DesignsCreating Designs...................................................................................................... 2-2Listing Designs ......................................................................................................... 2-3Opening Designs...................................................................................................... 2-5Using Design Kits ..................................................................................................... 2-6Adding Components ................................................................................................. 2-7Drawing Shapes ....................................................................................................... 2-8Synchronizing Designs ............................................................................................. 2-10

Synchronization Modes ...................................................................................... 2-11Cross-Probing .................................................................................................... 2-11

Documenting Designs .............................................................................................. 2-12

3 Simulating DesignsSimulation Wizard..................................................................................................... 3-2Signal Processing Simulation................................................................................... 3-3

Sources .............................................................................................................. 3-5Sinks................................................................................................................... 3-5Components ....................................................................................................... 3-5

Analog/RF Simulation and Convergence.................................................................. 3-5DC Analysis ........................................................................................................ 3-6Transient Analysis............................................................................................... 3-6Harmonic Balance (HB)...................................................................................... 3-6S-parameter Test Lab......................................................................................... 3-7Design Sequencer.............................................................................................. 3-7RefNets .............................................................................................................. 3-8

Common Circuit Simulation Methods ....................................................................... 3-9Backward Euler .................................................................................................. 3-9

Trapezoidal Rule................................................................................................. 3-9Backward Difference Formulas (Gear's methods).............................................. 3-9Truncation Error .................................................................................................. 3-10Convergence Criteria.......................................................................................... 3-10

Using Continuation Methods .................................................................................... 3-11Preventing Convergence Problems .................................................................... 3-12

Momentum Simulation, Optimization, and Visualization........................................... 3-12Instrument Connectivity............................................................................................ 3-13

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Simulation Controllers .............................................................................................. 3-13Optimization & Statistical Design Controllers ........................................................... 3-15

4 Analyzing ResultsCreating Data Displays ............................................................................................. 4-2Viewing Results ........................................................................................................ 4-4

Display Options .................................................................................................. 4-5Using Functions........................................................................................................ 4-5

5 Inputs and OutputsTranslating Series IV Projects and Designs.............................................................. 5-1Translating MDS Projects and Designs .................................................................... 5-2Formats for Design Exchange .................................................................................. 5-3

Drawing Exchange Format (DXF) ...................................................................... 5-3Engineering Graphics System (EGS)................................................................. 5-3GDSII Stream Format (Calma)........................................................................... 5-4Gerber ................................................................................................................ 5-4Gerber Viewer .................................................................................................... 5-4HPGL/2............................................................................................................... 5-4Intermediate File Format (IFF) ........................................................................... 5-5Initial Graphics Exchange Specication (IGES) ................................................. 5-5Mask................................................................................................................... 5-5MGC/PCB........................................................................................................... 5-5Spice .................................................................................................................. 5-5

Formats for Data Transfer ......................................................................................... 5-6

6 Simulation and Optimization ControllersData Flow Simulation Controller ............................................................................... 6-1DC Simulation Controller .......................................................................................... 6-2AC Simulation Controller .......................................................................................... 6-3S-Parameter Simulation Controller ........................................................................... 6-4Harmonic Balance Simulation Controller.................................................................. 6-5

Simulation Overview........................................................................................... 6-6Advantages......................................................................................................... 6-6Convergence ...................................................................................................... 6-6

Circuit Envelope Simulation Controller ..................................................................... 6-10Simulation Process............................................................................................. 6-11Simulation Steps................................................................................................. 6-14Typical Analyses................................................................................................. 6-14Typical Applications ............................................................................................ 6-15

LSSP Simulation Controller ...................................................................................... 6-16XDB Simulation Controller........................................................................................ 6-17Transient/Conv. Simulation Controller....................................................................... 6-18

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Transient Simulation and Convergence.............................................................. 6-18Transient Convergence Tips ............................................................................... 6-19Typical Convergence Problems .......................................................................... 6-20Convergence Hints ............................................................................................. 6-21Using Convolution .............................................................................................. 6-22

Solving an Invalid Impulse Response................................................................. 6-24Solving a Noncausal Impulse Response............................................................ 6-26RF Budget Controller................................................................................................ 6-27Nominal Optimization Controller............................................................................... 6-28Monte Carlo Controller ............................................................................................. 6-29Yield Analysis Controller........................................................................................... 6-30Yield Optimization Controller .................................................................................... 6-31Design of Experiments Controller............................................................................. 6-32

7 Additional Resources

Documentation ......................................................................................................... 7-1Website..................................................................................................................... 7-1Support Contacts...................................................................................................... 7-2

Index

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Chapter 1: Using ProjectsAdvanced Design System uses projects to au tomat ically organ ize an d st ore t he da tagenera ted when you crea te, s imula te, and ana lyze des igns to accomplish your des igngoals.

A project includes circuit , layout , s imula t ion , analys is , and output informat ion on thedesigns th at you creat e, along with a ny link s you a dd to oth er designs an d projects.

Use the Main window to crea te and open project s. Th is window is d isplayed when youlaun ch Advanced Design System .

Simulation DataMomentum Designs & DataSchematic & Layout DesignsDSP Synthesis DataDesign Rule Checker Data

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Using Projects

Creating ProjectsUse t he Ma in window to crea te a project t ha t you can th en u se to organ ize yourdesigns. A pr oject in cludes circuit , layout, simu lat ion, a na lysis, and out pu tinform at ion on t he designs th at you creat e, along with a ny link s you a dd to oth erdesigns and projects.

To crea te a p roject...

1. ChooseFile > NewProject

2. EnterProject Name& Location

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Opening ProjectsOnly one p roject can be open at a t ime. When you begin t o open a pr oject, you a rep rom pt ed t o s ave a n y ch a n ges you h a ve m a de in t h e cu r r en t ly op en p roject befor e it isclosed automatically.

To open a pr oject...

1. Choose File > Open Project a n d u se t h e dia log box t o loca t e a n d open t h e pr oject .

2. Use t he F ile Browser pa ne of th e Main window to locat e th e project a nddouble-click to open it.

Double-click toopen project

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Using Projects

Sharing ProjectsUse th e Main Window to reu se an d sha re projects with out ha ving to ma nu allyinclude all th e individual pa rts th at ma ke up a project.

Add links to creat e a hierarchical projectChoose File > Include/Remove Projects an d us e th e dialog box to locat e an d link to th e project.

Create a copy to replicat e a project

Choose File > Copy Project an d u se t he dia log box to loca te a nd copy th e project.

Archive/Una rchive to tr an sfer a compa ct project ar chive

Choose File > Archive Project an d us e th e dialog box to locat e an d a rchive th e

project.

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Chapter 2: Using DesignsAdvanced Design Sys tem uses des igns to s tore the schemat ic and layou t in format ionyou gener at e t o accomp lish your design goa ls.

A design ca n con sis t of a sin gle s ch em a tic or la you t , or it ca n be m a de u p of a n u mberof schem at ics a nd layout s em bedded as subn etwork s with in a single design. Alldesigns in a pr oject can be displayed an d open ed directly from t he Ma in window orfrom wit hin a Design window.

In a Design window you can :

Create and modify circuits and layouts

Add var iables and equat ions

Place an d congure component s, sha pes, and simulation cont rollers Specify layer and display preferences

Include ann otat ions using text an d il lustra t ions

Generate layout s from schema tics (an d schema tics from layout s)

The ba sic process of crea ting a design or layout is as illust ra ted:

PlaceComponent

RotateComponent

DeneParameters

Add Ports

ConnectComponent

Generate Reports

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12/902-2 Creating Designs

Using Designs

Creating DesignsYou ca n crea te a new d esign (layout) us ing one of two ways:

Ch oose Window > New Schematic in t h e Ma in win dow or File > New Design in t heSchem a tic (Layout) wind ow an d us e th e dialog box to na me t he le you a recreating.

Ch oose Insert > Template in t h e Sch em a tic win dow a n d s elect a t em pla t e for t h enew le.

When you u se a t emplat e, most of th e initial setu p an d congur at ion for t heschem at ic, the s imulat ion, a nd th e dat a an alysis is done for you au tomat ically.

To crea te a design...

Choose Window >New Schematic

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Listing DesignsEven a fter you close all Schem a tic an d Layout windows, designs t ha t you openedrem ain in m emory unt il you explicitly clear t hem or exit t he pr ogram .

To list design s...

Choose th e design from th e Window menu in th e Schem at ic (Layout ) window.

Double-click t he Net work s directory in t he Ma in window to display all designs,an d t hen double-click a design to list its s chem at ic, layout , an d h ierar chicalinformation.

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Using Designs

To view th e comp onen t h iera rchy with in a design, choose Tools > Hierarchy from th eschema tic wind ow to display th e Hier ar chy dia log box for t he d esign. To view th edesign h iera rchies with in a p roject , choose View > Design Hierarchies from th e Mainwindow to display t he Des ign Hier ar chies dia log box.

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15/90Opening Designs 2-5

Opening DesignsYou can us e eith er t he Ma in window or t he Schem at ic (Layout) wind ow to open adesign (layout).

Ch oose File > Open in t h e S ch em a t ic (La you t ) win dow a n d u se t h e d ia log box t olocat e an d open t he design.

U se t h e F ile Br ows er pa n e of t h e Ma in win dow t o loca t e t h e d es ign (la you t ) a n ddouble-click to open it.

To open a des ign...

Double-click todisplay design

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16/902-6 Using Design Kits

Using Designs

Using Design KitsIn order t o effectively us e th e design en vironm ent in Advan ced Design Syst em a ndtake advan tage of it s powerfu l s imula t ion capabilit ies, des igners mus t have a libra ryof component s th at ar e link ed to model les or s imulat ion da ta . For m an y RFIC

d es ign er s, t h es e com pon en t s a n d m od els a r e d is t ribu t ed by a fou n dr y in t h e for m of adesign kit . A u n iqu e d es ign k it is cr ea t ed for ea ch p roces s a n d ea ch CAD t ool. Th is k itis given to th e foun dry customer t o use when designing t heir circuit.

To help RFIC designer s become m ore su ccessful with our electr onic designau toma tion (EDA) softwa re, Agilent Techn ologies ha s been work ing with popularfoun dr ies to provide ADS comp onen ts a nd t ra ns lat ed model les for dist ribu tion byth e foun dry t o th e IC designer. Man y cust omer s a re a lso crea ting design kitsthemselves.

Design kits in ADS a re n ot only benecial to RFIC designer s. This librar y str uctur ecan be used for an y techn ology or process t o packa ge an d distr ibut e a reu sable set of comp onen ts. With t he ADS Design Kit u ser in ter face, you can n ow easily inst all an dma na ge all of your design kits.

Fr om t he ADS Main window, you can :

Instal l a design kit

Setup th e design kit inst allat ion at different levels

List mu ltiple design kits simu ltan eously Dene a pr oject an d sp ecify a design k it t o be u sed for techn ology les

Once your design k it is insta lled an d congur ed, you can sta rt using it just like a nyother ADS componen t . For more deta iled in format ion on ADS des ign k it s , r efe r to theDesign Kit Inst allation an d Setup documentation.

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Adding ComponentsYou ca n p la ce, con n ect , a n d con gu r e t h e followin g it em s in t h e d ra win g a r ea of you rdesign window to crea te your design.

Com pon en t s

Data items

Measurement sources

Simulation controllers

You can also add ent ire circuits a s s ubn etwork s t o crea te hiera rchical designs. Keepin mind t ha t when you begin a d esign u sing a tem plate, most of th e simulat ion a ndan a lysis setu p an d congu ra tion is done for you a ut oma tically.

To add a comp onen t...

1. SelectComponent2. DeneOrientation3. PlaceComponent4. EditParameters

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18/902-8 Drawing Shapes

Using Designs

Drawing ShapesTo crea te a layout , you can dra w an d modify sha pes in t he dr awing ar ea of yourdesign window to crea te your la yout . You can also add Tr a ces t o repr esen t electricalconnectivity.

To place a sh ap e:

Choose the shape from th e Draw menu or click th e appropriate butt on on th etoolbar

Draw th e sha pe at th e desired locat ion in t he dra wing ar ea.

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To draw a sha pe...

Select the shape and... To draw...

1. Click to start the rst segment

2. Click to end a segment and start a new segment3. Double-click to complete the shape

Polygon

1. Click to start the rst segment2. Click to end a segment and start a new segment3. Double click to end the last segment

Polyline

1. Click to mark the rst corner2. Drag to dene the rectangle3. Click to mark the second corner

Rectangle

1. Click to mark the center2. Click to mark a point on the perimeter

Circle

1. Click to mark the location2. Start typing

Text

1. Select a corner type2. Enter width and corner cutoff ratio3. Click to mark the start4. Click to mark the end

Path

1. Click to mark the start2. Click to mark the center3. Click to mark the end

Arc

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20/902-10 Synchronizing Designs

Using Designs

Synchronizing DesignsUse Design Syn chr onizat ion (Schem a tic wind ow > Layout > Generate/Update LayoutOR Layout window > Schematic > Generate/Update Schematic ) to genera te a ndsynchr onize your schem at ic an d layout ar tworks a nd symbols. The window where

you invoke t he synchr onization opera tion acts a s t he s our ce from which th edestination representa tion is generat ed or u pdated.

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21/90Synchronizing Designs 2-11

Synchronization ModesThe synchronizat ion can be complete or increm ent al a nd can be done t o an d from aschem at ic an d a layout .

Cross-ProbingTo see t he la yout repr esen ta tion of a s pecic wire or pin in your s chem at ic, selectLayout > Show Equivalent Node an d click t he wir e or p in t ha t you would like t o see inth e layout . When you view th e layout , the wire or pin th at you selected in t heschema tic will be highlight ed in red.

To see t he s chem at ic rep res ent a tion of a s pecic wire or p in in your la yout , selectSchematic > Show Equivalent Node a nd click t he wir e or pin t ha t you wou ld lik e t o seein t he schema tic. When you view the s chem at ic, the wire or pin t ha t you selected inth e layout will be h ighlight ed in r ed.

Generate Update Place Component

Place all activatedcomponents, including thosewith no artwork, connectedto the starting component.

Update a previouslygenerated design byplacing componentsthat have beenmodied.

Place items that have nocounterparts in the otherrepresentation.

Components with xedlocation status are notmoved.

Components with xedlocation status are notmoved.

Use the Current Rep onlycomponent placement mode

Components that are not

placed in the otherrepresentation arehighlighted

Wire guides show connectivity

in the other representation

Any component can serveas the starting point forwhich the location,orientation can be specied

Use the Options > Variablescommand to override the defaultresolution path for variable- andsubstrate- references

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22/902-12 Documenting Designs

Using Designs

Documenting DesignsAdvan ced Design System includ es a docum ent at ion t ool for crea tin g HTMLdocuments us ing the des igns and resu lt s with in a project . Th is Elect ron ic Notebookgener a tion tool ca n be us ed to:

Captu re schema tic, layout , and dat a display ima ges in a project, and importima ges from oth er sour ces.

Generate ht ml docum enta tion th at can be distr ibut ed an d viewed out side of ADS.

To document designs...

1. Choose Tools >Electronic Notebook2. Document Design

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Chapter 3: Simulating DesignsAdvanced Design System provides cont rollers t ha t you can add an d congur e t osimula te, optimize, an d t est your designs.

A DSP des ign s imula t ion requ ires a Data F low Cont rolle r while an Ana log/RF des ignsimu lat ion r equir es one or more of var ious cont rollers. You can eith er a dd a ndcongur e th e appr opriat e cont rollers or you can insert a tem plate (choose Inser t >Templat e from a Schem at ic window) th at cont ains th e appr opriat e cont rollers.

To simu lat e a design...

1. Click andplacecontroller

2. Click toeditparameters

3. Click tosimulatedesign

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24/903-2 Simulation Wizard

Simulating Designs

The st at us of th e simula tion is displayed in a messa ge window.

Click to see informat ion on simula t ion and convergence issues and t ips for Analog/RFSimulation.

Simulation WizardAdvanced Design System also provides a s tep-by s tep inter face for circui t s imula t ion .The Sma rt Simulat ion Wizard can be used to:

Create Analog/RF designs

Set up and run s imula t ions

Display s imula t ion r esult s

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25/90Signal Processing Simulation 3-3

To sm ar t simu lat e a d esign...

Signal Processing SimulationADS provides an integra ted en vironmen t for th e design an d validation of RF/ana log/DSP system designs to th e implement at ion level using th e ADS Pt olemysimulator. The ADS signal processing environment enables:

Accur at e RF system m odels for faster developmen t of system specicat ions.

Extensive behaviora l model set for RF system a nd DSP system modeling tha thelps engineers r apidly crea te a nd optimize larger designs.

Co-design between DSP, ana log and RF port ions of th e signa l path .

1. Choose Simulate >Smart SimulationWizard2. Specify CircuitCongurations3. Specify Simulation

Options4. Display Results

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Simulating Designs

Hu ndreds of DSP an d a na log models for development of algorithm s.

Pr opagation an d m at rix models t ha t allow modeling of complete wirelesssystems.

Data export and import capabili ty to measurement instrum entat ion h elps

verify designs us ing virt ua l prototyping concepts.

IP r euse of MATLAB, HDL, & C++ models.

The systems d esigner can ar chitect a comm un icat ions s ystem u sing beha viora lmodels t o validat e a concept. The designer can th en design a nd subst itut e lowerlevels of a bst ra ction t o verify th e RF/mixed signa l design down t o th e circuit level,and expor t the des ign to a var ie ty of manufactu r ing tools. Ava ilab le s ta t is t ica l des igncapability a llow the user to make d ifcu lt t r adeoffs dur ing the des ign process in orderto optimize performance or manufacturing yield.

A lar ge arr ay of beha viora l RF/an alog/DSP m odels work with t he ADS Pt olemysimula tor to provide leading-edge s imula t ion accuracy dur ing the des ign process . Theinclus ion of pr opa gat ion a nd ma t rix models, facilita te m odeling of th e comp letewireless system. ADS comm un icat ions libra ry modules support th e latestcomm un icat ions sta nda rds such a s WLAN, 3GPP, and Edge. These librar ies can beused a t t he front end of th e design process when t he system ar chitectur e isconceptua lized, dur ing th e design a nd implementa tion pr ocess, or a t th e back end of th e design pr ocess dur ing th e na l vericat ion.

Instr umen t links to Agilent Techn ologies test an d m easur ement instru ment at ionpr odu ct s pr ovide virt ua l prototypin g verication for des igns pr ior t o na limplement at ion or ta pe out . For exam ple, a new RF/an alog/DSP tr an smitt er designmodeled in t he s igna l processing schem at ic can be veried by linking t he out put of th e simulat ion with one of th e Agilent E SG signa l genera tor products. The r esultingrea l world signal pr oduced in a virt ua l environm ent will include a ll of the signa ldist ort ions, noise, an d pr opa gat ion effects modeled int o th e design. This signal canthen be fed in to an Agilen t s igna l ana lys is componen t or rea l-wor ld rece iver circu it topr ovide virt ua l prototyping cap a bility, a nd t he a bility to "tu ne" the design u sing

rea l-world ha rdwar e and an alysis.ADS Pt olemy simu lat ion is cont rolled u sing a Dat a Flow Simu lation Cont roller ,sour ces, an d sinks placed on t he design. There mu st be a t least one source or sin k th at is cont rolling th e simulat ion. Cont rolling sinks an d sour ces keep th e simulat ionru nn ing; non-cont rolling sinks a nd sour ces do not.

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27/90Analog/RF Simulation and Convergence 3-5

SourcesSour ces ar e component s with no input s. Sour ces can rea d da ta from les,instr um ent s, an d dat a set s. When a sour ce is cont rolling th e simulat ion, it will keepth e simulation run ning long enough t o out put all its data .

SinksSinks a re component s with n o out put s. When a s ink cont rols t he simu lation, it willkeep th e simulat ion r un ning long enough t o sat isfy its st ar t a nd st op times. When as ink is not con t rolling the s imula t ion , it will s t a r t collect ing da ta a t S ta r t , then collectas m uch da ta as t he simulation pr oduces.

ComponentsTher e a re two basic types of Pt olemy comp onen ts Timed an d Nu mer ic. Timedcomponents have a not ion of sampling ra te , car r ier frequency, and envelope. Numericcomponent s pr ocess int egers, ma tr ixes, oat s, xed point nu mbers an d m odel theDSP p ort ions of a d esign.

For more in form at ion on...

Cosimula tion with a na log/RF designs, refer to the Cosimula tion section of th eADS Pt olemy docum ent a tion .

Connecting to instruments, refer to the Conn ection Man ager docum ent at ion .

Cosimulation with MATLAB IP import , refer to the MATLAB Cosim ulat iondocumentation .

Cosimulat ion a nd HDL IP import , refer to the HDL Cosimulationdocumentation .

C++ IP impor t , refer to the Model Builder docum ent at ion .

Analog/RF Simulation and ConvergenceAna log/RF simu lation compu tes t he r esponse of a circuit to a pa rt icular stimu lus byform ulat ing a system of circuit equat ions an d t hen solving th em n um erically. Ea chsimu lat ion t echn ology accomp lishes t his a na lysis a s follows.

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28/903-6 Analog/RF Simulation and Convergence

Simulating Designs

DC Analysis Solves a system of nonlinear ordinar y differential equat ions (ODEs)

Solves for an equilibrium point

All t ime-derivat ives are const an t (zero) System of nonlinear a lgebra ic equations

Transient Analysis Solves a system of nonlinear ordinar y differential equat ions (ODEs)

Time-derivatives replaced with a n ite-difference approximat ion (int egrat ionmethod)

Sequence of systems of nonlinea r a lgebraic equat ions (one system a t eachtimepoint)

Harmonic Balance (HB) Solves a system of nonlinear ordinar y differential equat ions (ODEs)

S teady-s ta t e me thod

Solution approximated by tr un cat ed Four ier series

System of nonlinear ODEs becomes a system of nonlinear algebraic equationsin t he frequen cy doma in

Solving nonlinear algebraic equations

Nonlinea r algebra ic equat ions ar e solved using t he N ewton-Raphson a lgorith m(Newt on's met hod) a s follows.

Convert t he problem t o a sequence of systems of linear equations

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29/90Analog/RF Simulation and Convergence 3-7

Quadr at ic convergence near t he solution (error squa red at ea ch iterat ion)

S-parameter Test LabAn S-paramete r t e st lab enab les you to ca lcu la te the S-parameter s of mult ip le N-por tnetworks in a single simu lation ru n.

An S-param eter test lab is a schema tic th at cont ains one S-para meter t est labcom pon en t a n d on e or m or e t es t ben ch es. A t es t ben ch is a s ch em a tic t h at con t a in s a nN-port net work an d ter mina tions for ea ch port of th e net work . Its u se is bestillustr at ed in m ultiple sta ge circuit designs where viewing t he int er-sta ge circuitbehavior of all sta ges simu ltan eously is desired. In su ch sit ua tions th e S-par am etertest lab can be used to ter mina te each sta ge in th e applicable inpu t/out putimpedan ces of adjacent st ages rat her t ha n in t he sta nda rd 50 ohm s.

RefNets can also be used in conjun ction with th e S-par am eter t est lab feat ur e.

Design SequencerA Design Sequen cer cont roller en a bles you t o sequ ence mult iple simu lat ions in a

single simu lation r un using a t est bench th at includes all th e desired simu lationcont rollers a nd th e top-level design le.

Some typical ap plicat ions for a Sequen cer cont roller ar e a s follows.

Optimizing a var iable across multiple simulat ions

En abling complex instru ment cont rol in Ptolemy

Runn ing a series of vericat ions t ests on a design

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30/903-8 Analog/RF Simulation and Convergence

Simulating Designs

RefNetsA RefNet (referen ce net work ) comp onen t en a bles the port im peda nce from a noth erdesign le in th e system (the r eferenced network ) to be referenced as a ter mina tingimpedan ce for t he cur ren t design le under test .

Two typical ap plicat ions for RefNet s a re as follows.

Inter-sta ge circuit a na lysis and design: In some design applicat ions it isdesirable t o simulta neously evalua te th e perform an ce of individual circuitsta ges t erminat ed in th e input an d out put impedan ces of adjacent sta ges. Toaccomplish the termina t ion of an ind ividua l s t age refe renced to a specic por t of oth er st ages in the design cha in, the RefNet is ut ilized in t he S-par am eter t estlab.

Design specic ter mina tion: For some t op level DC, AC, or S-par am eter designles, it m a y be d es ir ed t o t er m in a t e a p or t wh os e im ped a nce is ch a r a ct er ized bydat a, from an extern al le (e.g. S-par am eters, Z-par am eters, Y-par am eters) orsome other n etwork .

The t wo RefNet comp onen ts, RefNetTB and RefNetDesign , ha ve th e samefun ctiona lity an d ar e supported un der DC, AC and S-para met er an alysis, with twodifferences:

RefNetTB supports n ested network referencing while RefNetDesign does not. RefNetTB uses a test bench a s th e reference design while RefNetDesign uses a

sta nda rd (non-test -bench) schem at ic design.

Table 3-1. Differences Between S-para met er Test Labs a nd Sequen cer

Sequencer Test Lab

DC, SP, AC, HB, Tran, ENV, Ptolemy SP only

Utilizes Test Bench Controllers Utilizes Test Lab ControllerDifferent temps per test bench possible One simulation temp for all

Opt/Stat/ParamSwp at top level

RefNets supported

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31/90Common Circuit Simulation Methods 3-9

Common Circuit Simulation Methods

Backward Euler

First order meth od tha t a ssumes th e solution waveform is linear over one timestep

One-step met hod (needs one previous t ime point solut ion only)

Adapts faster to abrupt s ignal chan ges

Sta ble on a ll sta ble differential equa tions a nd some un sta ble ones.

Exhibits heavy nu merical damping, increases loss

Require smaller t ime step to maintain accura cy

Trapezoidal Rule Second-order m eth od, ass um es the solution waveform is quadr at ic over one

time step

On e-s t ep m e th od

May exhibit point-to-point r inging on circuits t ha t h ave very small t imecons ta nt compa rin g to tim e step (stiff circuit)

Sta ble only on st able differential equa tions

Exhibits no art icial num erical damping

Backward Difference Formulas (Gear's methods) Multiple order polynomial over one time step

Only the rst s ix orders are avai lable in ADS

First order meth od is identical to backward Euler

Higher-order polynomials allow a lar ger time step with out sacricing accur acy,ar e efcient for sm ooth waveform s

Higher order m eth ods (order > 2) ma y exhibit sta bility problems on light lydam ped circuits

Second-order ba ckwar d difference form ula (Gear 2)

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32/903-10 Common Circuit Simulation Methods

Simulating Designs

Two-s tep method

Sta ble on a ll sta ble differential equa tions a nd some un sta ble ones.

Exhibit some numerica l damping

Truncation ErrorThe er ror made by replacing the t ime der iva t ives with a d iscrete -t ime approximat ion .This err or is difcult to estimat e an d depends on th e type of circuits an d th e timesteps.

Local Truncation Error (LTE)

The tr un cat ion error ma de on a single step

Global Truncation Error (GTE)

Maximum accumulated t ru ncat ion er ror

The circuit with long time const an t is sensitive to these err ors

Logic an d bias circuits ar e not sensitive to th ese errors

Convergence CriteriaNewton 's it e ra t ion is converged if the approximate solu t ion rs t sa t ises the Residuecriter ia at th e end of each Newton iter at ion a nd t he Upda te criter ia once th e residuecriteria a re sa tised.

Residue criterion

KCL sat ised t o a given tolera nce. This is enforced at each node an d is import an twhen impeda nce at a n ode is sma ll.

Update criteriaDifference between t he last two itera tions m ust be small. This is importa nt whenimpedan ce at a n ode is lar ge.

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33/90Using Continuation Methods 3-11

Using Continuation MethodsUse cont inua tion m eth ods to provide a sequence of initial guesses th at ar esu fcient ly close t o th e solut ion t o as su re N ewton's met hod conver gence.

Choose a na tu ra l or cont rived cont inuat ion pa ra meter which cont rols amodication of the circuit

S tep t h e con t in u a t ion p a ra m et er fr om 0 t o 1 (t h e or igin a l cir cu it con gu r a t ion ),using th e solution from t he pr evious st ep as t he st ar ting point

As long a s t he solut ion cha nges cont inu ous ly as a fun ction of th e cont inu at ionpar am eter an d th e steps a re sm all enough, Newton's meth od will converge. Keep inmind t hough t ha t t he rs t t wo met hods, Sour ce an d gmin st epping, will fail if th econt inua tion pa th cont ains a limit point .

Source Stepping

Uses a fra ction of th e sour ce voltages a nd curr ent s app lied to the circuit a s th econtinuation parameter.

Turn off al l sources when th e continuat ion pa ram eter equals 0

Raise source levels to th eir na l levels slowly, gener at ing a sequence of circuitcongurations

Use the solut ion from t he previous congurat ion a s an initial guess for t hecur ren t congur at ion

Gmin Stepping

Uses t he cont inua tion pa ra met er t o cont rol th e value of th e gmin resistors

Sta rt with a lar ge gmin for a n easy to comput e solution becau se nonlineardevice beha vior is mu ted by the presen ce of the sm all resistors

En d with very sma ll gmins for resistors th at a re so large th at t hey no longer

affect th e circuit

Remove th e gmins to comput e the nal solution

Arc-length Continuation

Works best for complicat ed cont inua tion pat hs an d limit point s u sing a cont inua tionpara meter t ha t is a fun ction of th e ar c-length para meter

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34/903-12 Momentum Simulation, Optimization, and Visualization

Simulating Designs

Travel sam e dista nce at each step, as specied by the arc-length

Increase or decrease the continuat ion par ameter a long the path in each st ep

Preventing Convergence ProblemsConver gence problems us ua lly a rise a s a r esu lt of err ors in circuit conn ectivity orun rea sonable (out of ra nge) model or componen t va lues. Some of th e st eps you canta ke a re a s follows.

Turn on the topology checker

Tu r n on wa r n in gs

Act u pon t he messages in t he ADS Status Server window

Elimina te sm all oat ing resistors (or increase I_AbsTol) becau se an y err or incomputed volt ages for nodes with small r e sis tor s resu lt s in la rge er ror cur ren t s

Avoid very lar ge an d very sma ll resista nces conn ected to a node becau se largeresista nces ar e lost dur ing J acobian const ru ction due to nu mer ical r oun d-offs

Momentum Simulation, Optimization, andVisualization

Momentum includes simulation, optimization, and visualization tools for predictingth e per form an ce of mu ltilayer high-frequen cy circuit boar ds, an ten na s, hybrids,mu ltichip m odules, and int egra ted circuits.

Momen tu m en ables you t o:

Simulat e when a circuit model ra nge is exceeded or t he model does not exist

Identify para sitic coupling between component s

Go beyond simple an alysis an d vericat ion t o design a ut oma tion of circuit

performance Visualize cur ren t ow an d 3-dimensiona l displays of far-eld radiat ion

Momentum is an electr oma gnetic simulat or th at compu tes S-par am eters for genera lplan ar circuits, includin g microstr ip, slotline, str ipline, coplan a r waveguide, an doth er t opologies.

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35/90Instrument Connectivity 3-13

Momentum Optimization varies geomet ry par am eters au tomat ically to help youachieve th e optima l str uctur e th at meets th e circuit or device perform an ce goals.

Momentum Visualization pr ovides a 3-dimen siona l perspective of simu lat ion r esu lts,en a blin g you t o view a n d a n im a t e cu r r en t ow in con du ct or s a n d s lot s, a n d view bot h2D and 3D repr esent at ions of far-eld radia tion pa tt ern s.

Instrument ConnectivityConn ection Ma na ger enables the sh ar ing of signa ls, measu rem ent s, algorith ms, anddat a between ADS simu lations a nd Agilent instr um ent s (signa l genera tors an dsigna l an alyzers).

Usin g Conn ection Man ager, you can :

Access an d cont rol instru ment s from ADS dialogs Measure devices and constru ct ADS data sets from th e measurement data

Create simulat ion models based on measured data

Use real-t ime instru ment-generated st imulus and measurement duringsimulations

Simulation ControllersAd d on e or m or e s im u la t ion con t r oller s t o t h e d es ign ba s ed u pon t h e t yp e of d es ign t obe simu lated a nd t he kinds of an alyses desired .

Description Typical Use

Dat a Flow Simu lation Cont rollerControls the ow of mixed numeric and timed signalsfor digital signal processing simulations using theADS Ptolemy simulator.

All signalprocessingdesigns

DC Simu lat ion Contr ollerFundamental to all RF/Analog simulations. It performsa topology check and an analysis of the DC operatingpoint.

All RF/Analogdesigns

AC Simu lat ion Cont rollerObtains small-signal transfer parameters like voltagegain, current gain, and linear noise voltage andcurrents.

FilterAmplier

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36/903-14 Simulation Controllers

Simulating Designs

S-Par am eter Simu lation Contr ollerProvides linear S-parameter, linear noise parameters,transimpedance, and transadmittance. Can be used toachieve many goals of the AC simulator.

FilterOscillatorAmplier

Ha rm onic Balance Simula tion Cont rollerUses nonlinear harmonic-balance techniques to ndthe steady-state solution in the frequency domain.

Mixer

OscillatorPower amplierTransceiver

Circuit E nvelope Simu lat ion Cont rollerUses a combination of frequency- and time-domainanalysis techniques to yield a fast and completeanalysis of complex signals such as digitally modulatedRF signals.

MixerOscillatorPower amplierTransceiverPhase-lockedloop

LSSP Simulat ion Cont rollerPerforms large-signal S-parameter analyses torepresent nonlinear behavior. The accompanying P2Dsimulator can be used to speed up subsequentanalyses.

Power amplier

XDB Simu lat ion Cont rollerSeeks a user-dened gain-compression point at whichan actual power curve deviates from an idealized linearpower curve.

Power amplierMixer

Tra ns ient /Conv. Simu lat ion Cont roller

Solves a nonlinear circuit entirely in the time domainusing simplied models to account for thefrequency-dependent behavior of distributed elements.

Mixer

Power amplierSwitching circuits

RF Budget ControllerDetermines the linear and nonlinear characteristics ofan RF system made up of a cascade of two-port,two-pin linear or nonlinear components.

MixerNonlinearamplier

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37/90Optimization & Statistical Design Controllers 3-15

Optimization & Statistical Design ControllersOptimization an d st at istical design cont rollers a re u sed in conjun ction withRF/Ana log an d signa l processing simu lat ion cont rollers t o:

Ch a ra ct er ize a n d im pr ove a n u n kn own pr oces s s uch a s t h e r es pon se of a des ign

Identify var iables tha t cont ribute signican tly to variations in perform an ce

Var y para meter values t o ident ify combinations th at deliver t he desired yields

Some of th eir design a pplicat ions includ e:

Opt imizing gain and matching

Filter response optimizat ion

Pu lse-r ise t ime tun ing

Carr ier lock time an d residual loop error optimizat ion

Fixed-point bit-width optimizat ion

Maximize manufactur ing yield

Advanced Design System includes the opt imizat ion and sta t is t ica l des ign controllerssh own below. For m ore det ailed inform at ion on opt imizat ion a nd s ta tist ica l design,refer t o th e Tun ing, Optimizat ion, a nd Sta tist ical Design documentation.

Description Used WithNominal Optimization ControllerUsed to compare computed and desiredresponses and modify parameter nominalvalues to bring the computed response closerto the desired optimization goals.

Goal Component (required)A Goal component is used in conjunction tospecify the optimization goals.

Mont e Car lo Cont rollerUses the Monte Carlo method to simulate a

design over a given number of trials in whichthe statistical variables have values that varyrandomly about their nominal values withspecied probability distribution functions.

Yield Specication Component (optional)A Yield Specication component is used in

conjunction to specify the desired yields.Statistical Correlation Component (optional)A Statistical Correlation component is used tospecify statistical correlation between statisticaldesign variables.

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38/903-16 Optimization & Statistical Design Controllers

Simulating Designs

Yield Ana lysis Cont rollerUses the Monte Carlo method describedabove to determine the manufacturing yield.For each trial, the computed response iscompared to the coresponding yieldspecication, and a pass/fail decision is made.

Yield Specication Component (required)A Yield Specication component is used inconjunction to specify the acceptableperformance.

Statistical Correlation Component (optional)A Statistical Correlation component is used tospecify statistical correlation between statisticaldesign variables.

Yield Opt imizat ion Cont rollerUsed to analyze multiple yield analyses andadjust the nominal values to maximize theyield estimate of the statistical designvariables.

Yield Specication Component (required)A Yield Specication component is used inconjunction to specify the acceptableperformance.

Design of Exper imen ts Cont rollerUsed to sequentially and iteratively improvethe statistical performance of a design byidentifying variables that contributesignicantly to performance variation andhoning in on the target statistical response.

DOE Goal Component (required)A DOE Goal component is used in conjunctionto specify the desired goals.

Description Used With

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39/904-1

Chapter 4: Analyzing ResultsAdvanced Design Syst em u ses da ta sets t o store th e simulat ion inform at ion yougenera te when ana lyzing des igns. You can d isplay th is in format ion for ana lys is us ingth e Dat a Display window. A Dat a Display window ca n a lso be used t o display da taimport ed from other sources.

In a Dat a Display window you can :

Display data in a variety of plots a nd forma ts

Use markers to read specic data points on traces

Use equat ions t o perform operat ions on dat a

Annotat e results using text and il lustra t ions

Once a simu lat ion is comp lete, the da t a is displayed a ut oma tically if you did one of th e following (a blan k Da ta Display window is open ed if you did n one of them ):

Specied a data set an d display before simulat ion

Used a schema tic template for a n Ana log/RF simulation

Specied Recta ngular in th e Plot pa ra meter in a sink for a Signal Processingsimulation

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40/90

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41/90Creating Data Displays 4-3

To crea te a da ta display...

1. Click to openData Display

2. Click and placea plot

3. Select dataset,

plot, and traceoptions

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42/904-4

Analyzing Results

Viewing ResultsTo view simu lat ion r esu lts from th e Main , Schem at ic, or La yout window chooseWindow > Open Data Display an d us e th e dialog box to locat e an d open t he r esults.

Note To display a list of da ta display les in t he F ile Browser pa ne of th e Mainwindow you will need to be su re th e Sh ow All Files opt ion ( View > Show All Files ) isselected.

To display simu lat ion r esu lts...

1. Open DataDisplay Window

2. Select ResultsFile

3. DisplaySimulation Results

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43/90Using Functions 4-5

Display OptionsThe following plot, trace, and data options can be used to display data for analysis:

Using Functions

You can use Measurement Equa t ions to per form opera t ions on da ta genera ted dur inga s im u la t ion . Th es e equ a t ion s a r e cr ea t ed u sin g fu n ct ion s t h a t a r e ba s ed on AE L, t h eApplicat ion Exten sion Lan guage.

Note Dat a from a m ar ker can a lso be used as par t of an equa tion. To insert ama rk er, choose Marker > New an d click t he t ra ce where you wan t t o insert it.

Plot Type Trace Type Data Source

Rectangular plotStacked plotSmith chartPolar plot

Auto, Bus,Linear, Scatter,Spectral,Histogram,Digital, Sampled

Simulation datasetFile Formats- Touchstone- MDIF- Citile- ICCAPList

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44/904-6 Using Functions

Analyzing Results

To crea te a nd insert a fun ction...

1. Click and placeEquation

2. Enter Equation

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45/90Translating Series IV Projects and Designs 5-1

Chapter 5: Inputs and OutputsTo import or export a design (schem at ic or la yout ):

Choose File > Import (or E xport ) from a Schema tic or La yout window

Choose a le type

E n ter a le n a me

To import or export dat a:

Choose Window > New File/Instr um ent Server from a Schema tic window

Click Read (or Write)

Specify a le type and path

Translating Series IV Projects and DesignsWhen you tr an slat e a Series IV project or design into Advanced Design System , th ep roces s cr ea t es a cop y a n d t h en t r a n sla t es t h e cop y in t o a n Ad va n ced Des ign Sys t emform at . Ea ch Series IV component is replaced by an equivalent ADS component an dlayout geomet ry is preserved.

Note : Tr an sla te a n en tir e Ser ies IV pr oject wh en you wa nt m or e t ha n on e design orwhen t he design you wan t is hiera rchical.

The ba sic pr ocess of tr an slat ing a S eries IV project or design in to Advan ced DesignSystem is as il lust ra ted:

Importthe Design

Verify Componenttranslation

Simulatethe Design

CompareSimulation Results

Prepare Design forSimulation

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46/905-2 Translating MDS Projects and Designs

Inputs and Outputs

Translating MDS Projects and DesignsWhen you tr an slat e an MDS project or design int o Advanced Design System, t hep roces s cr ea t es a cop y a n d t h en t r a n sla t es t h e cop y in t o a n Ad va n ced Des ign Sys t emform at . Ea ch MDS component is replaced by an equivalent ADS component an d

layout geomet ry is preserved.

Note : Translate an entire MDS project when you want more than one design orwhen t he design you wan t is hiera rchical.

The ba sic pr ocess of tr an slat ing an MDS project or des ign in t o Advan ced DesignSystem is as il lust ra ted:

Importthe Design

Verify Componenttranslation

Simulatethe Design

CompareSimulation Results

Prepare Design forSimulation

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47/90Formats for Design Exchange 5-3

Formats for Design Exchange

Drawing Exchange Format (DXF)This form at was developed by Aut odesk for it s AutoCAD product t o t ra ns fergeomet ric dat a bet ween systems. Like th e ma sk le form at , it pr ovides a s implegeomet ric repr esent at ion of dat a. DXF les can be tr an sferr ed between P C-based orUNIX-based systems.

Engineering Graphics System (EGS)

This form at is a gener al graph ics form at used for captu ring ma nu ally ent ereddesigns. EGS h as been a pplied to ICs, Micro-circuits, Hybrids, an d PC Boar d designapplicat ions. Using th is form at , you can easily excha nge dat a with oth er pr ogram susing EGS form at s. In a ddition, EGS facilita tes bett er a rt work t ra nsla tion withAdvanced Design System.

The Genera te forma t is a att ened list of EGS primitives specied in t heuser-dened u nit s pace.

Format Import Export

DXF (.dxf) Layout

EGS Archive Format (_a) Layout LayoutEGS Generate Format (_g) Layout

SchematicLayout

GDSII Stream Format (.gds) Layout Layout

Gerber (.gbr) Layout

Gerber Viewer (.msk, .gbr) Layout

HPGL/2 (.hpg) LayoutSchematic

Layout

HP IFF (.iff) LayoutSchematic LayoutSchematic

IGES (.igs) Layout Layout

Mask File (.msk) LayoutSchematic

Layout

MGC/PCB (.iff) Layout

Spice (.cir, .cki, .iff, .net) Schematic

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48/905-4 Formats for Design Exchange

Inputs and Outputs

The Archive Form at is a hiera rchically organ ized list of EGS primit ivesspecied in t he u ser-dened un it spa ce. Inform at ion su ch a s dr awing sha pes,layout un its, data base pr ecision, a nd grid spacing is included.

GDSII Stream Format (Calma)This forma t is an industr y stan dard for t ra nslating nal ma sk dat a t o foun dries.Advanced Design System rea ds GDSII versions 4.0 th rough 6.0 and writes GDSIIversion 6.0. Un like oth er da ta form a ts, GDSII str eam form a t is bina ry. You can noteasily view or edit a str eam form at le usin g a t ext editor. This form at is easilytr an slat ed between different CAD systems becau se it repr esent s a h ighly restr ictivedat a type.

GerberThis form at refers t o various da ta input form at s th at Gerber Scientic uses t o driveits ph otoplott ers. The Gerber form at is used by photoplott ers produced by oth erma nu factur ers a lso. The progra m su pport s various t ypes of Gerber out put via m ask les t o either th e Gerber or DXF t ra nsla tor.

Gerber ViewerTh is for ma t a ppea rs a s a n expor t le opt ion . It is n ot a le for ma t , bu t you ca n u se itto view Gerber or m as k les to help verify th e corr ectn ess of your da ta if th e lesmeet th e following crit eria :

Use either a bsolute or incremental data coordinat es

Support apertur es from D10-D999

Have data forma ts from 0.1 to 4.5

HPGL/2This form at is a su bset of th e HP GL/2 print er/plott er lan guage. When creat ing agraph or cha rt in an oth er tool, you can write t he gra phics dat a t o an HP GL/2 out putle, th en import th e le into Advanced Design System . In Advanced Design System ,th e HPGL data is tran sformed into form s an d sha pes tha t can be edited andma nipulat ed like a ny other dra wing. Additiona l text, an notat ion, scaling or editingma y be added.

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49/90Formats for Design Exchange 5-5

Intermediate File Format (IFF)This form at is an ASCII le with a s imple, line-orient ed comm an d st ru ctu re a nd afairly rich set of constructs. This format is machine- and application-independent,th us simplifying design da ta tr an sfer. IFF les ar e used as t he excha nge mecha nism

when t ra nsferring designs between Advanced Design System a nd t hird-part y EDAtools su ch as Mentor Gr aph ics Design Architect an d Ca dence Ana log Art ist.

Initial Graphics Exchange Specication (IGES)This forma t is an approved ANSI sta ndar d th at is used extensively thr oughout th ecompu ter-aided design a nd m an ufactu ring world. It can repr esent both mechan icalan d electr ical design da ta in two an d th ree dimensions. The IGES sta nda rd for t hetr an sfer of electr ica l design d at a is k nown a s CALS specicat ion. Advan ced Design

System su pport s version 4.0 and 5.0 IGES form at s. It r eads a nd writ es IGES CALSLevel 1 (techn ical illus tr at ion) a nd Level 3 (electr ical/elect ronic app licat ions ) les.

MaskThis form at is a sim ple at (non-hiera rchical) geomet ric descript ion. The form a tfacilita tes th e t ra nsfer of simple geomet ric data for na l ma sk processing. Onlygeomet ric form s ar e described in a ma sk le; simula tion da ta , element pa ra met ers,subst ra te denitions, and hiera rchy ar e not included.

MGC/PCBThese les ar e IFF les t ha t ar e used exclusively for Men tor Gra phics designtr an sfers. MGC/PCB les writ e to a specic loca tion each a nd every time. When youselect t his form at , th e lena me a nd locat ion of th e IFF t ra nsport is determ inedautomatically.

SpiceSimulat ion P rogra m with Int egrat ed Circuit Em pha sis (Spice) ha s become asimula tion tool used by engineers th roughout th e world for simula ting circuits of alltypes. Aft er it s developm ent a t t he U niversit y of Californ ia Ber keley, Spice ha s beencomm ercialized a nd modied by a lar ge num ber of vendors a nd also adopted an dmodied by electr onics comp an ies for th eir own in-house u se.

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50/905-6 Formats for Data Transfer

Inputs and Outputs

Formats for Data TransferFormat Description Usage

Touchstone (SnP) Format

SnP Small signal S, H, Y, Z, orG-parameters. May also includeoptional noise data (2 port dataonly). Where n is the number ofports from 1 to 99.

n-Port S-parameter le (SnP)components in the DataItems Library.

When writing data from a dataset to a le, the variable names are limited to S,H,Y,Z or G, forexample, S[1,1], S[1,2], G[1,1], G[1,2]. The variable name is used to determine the type ofdata.The rst set of data in the dataset that matches the data type (name) will be output. It is notpossible to arbitrarily select which data will be will be output.

CITIle FormatCITI A general data format

supported by networkanalyzers. Capable of storingmultiple packages ofmulti-dimensional data.

S#P #-Port S-parameter lecomponents in the DataItems Library.

There are some specic problems with the current version in writing and/or reading this dataformat. Refer to the release notes or on the Agilent EEsof support Web site for moreinformation and workarounds.

Agilent IC-CAP FormatsDUT, MDL, SET Device under test (DUT), model

(MDL), and setup (SET) lesfrom the Agilent IC-CAPsoftware. These les cancontain Measured, Simulated,and/or Transformed data.

Once the data is read into adataset, it can be used withany component (for example,a VtDataset source) that canread data from a dataset.

You can read in IC-CAP data only.Only simple, scaled expressions with numbers or variables and one operator (either +, -, *, or /)are supported for start, stop, step, and number of points parameters, for example, start= 1 GHZ

or stop=icmax/10.

MDIF Formats

DSCR Discrete (indexed) tabular andpossibly statistical density data.

DAC

GCOMP Gain compression data Amplier and Mixer items inthe System - Amps & Mixerslibrary.

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51/90Formats for Data Transfer 5-7

GEN_MDIF Generalized multi-dimensionaltables unifying other MDIFformats.

DAC

IMT Intermodulation product table ofmixer intermodulation products

between the LO and signal thatrelates the mixer IM output levelto signal input level.

MixerIMT in the System -Amps & Mixers library.

MODEL_MDIF Nonlinear model parameters EEFET1, BJTAP, etc.

P2D Large-signal, power-dependent,2-port S, H, Y, Z, or G-parameters.

AmplierP2D item in theSystem - Amps & Mixerslibrary.

PDF User dened, piece-wise linearprobability density functiondata.

With expressions in theStatistics tab.

The PDF format is not yet fully supported.

S2D 2-port S, H, Y, Z, orG-parameters with gaincompression and optional noiseand intermodulation data.

Amplier S2D, Amplier, andMixer items in the System -Amps & Mixers library.

S2PMDIF Multi-dimensional 2-port, S, Y,Z, H, G signal and optional2-port noise parameter (Fmin,Gopt, Rn) data.

With S2PMDIF and DAC

SDF Time-domain voltage data le inHP89440 le format.

TimeFile item in TimedSources and OutFile item inSinks library.

SPW Time-domain voltage data le inCadence Alta Group SPWformat

TimeFile item in TimedSources and OutFile item inSinks library.

TIM Time-domain data TimeFile item in TimedSources and OutFile item inSinks library.

When writing data from a dataset to a le, the variable names are limited to S,H,Y,Z or G, forexample, S[1,1], S[1,2], G[1,1], G[1,2]. The variable name is used to determine the type ofdata.The rst set of data in the dataset that matches the data type (name) will be output. It is notpossible to arbitrarily select which data will be will be output.There are some specic problems with the current version in writing and/or reading this dataformat. Refer to the release notes or on the Agilent EEsof support Web site for moreinformation and workarounds.Obsolete Formats: COD, FIR, LAS, SPE, LIST2, and T2D.

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52/905-8 Formats for Data Transfer

Inputs and Outputs

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53/90Data Flow Simulation Controller 6-1

Chapter 6: Simulation and OptimizationControllers

Data Flow Simulation ControllerUse t he Da ta Flow cont roller to cont rol the ow of mixed nu mer ic an d t imed signalsfor a ll digita l signa l processing simu lat ions wit hin Advan ced Design System . Thiscont roller works with th e sink comp onen ts to provide you exibility t o cont rol th edu ra tion of th e sim ula t ion globally or locally.

Note : While you can n o longer place multiple cont rollers on th e schema tic tosimula te t he sa me design with different cont roller par am eters, you can a chieve th esame funct iona lity by us ing s ingle -poin t sweeps on the paramete r you are in te restedin va rying.

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54/906-2 DC Simulation Controller

Simulation and Optimization Controllers

DC Simulation ControllerThe DC cont roller pr ovides for both single-point an d swept simu lat ions. Sweptvariables can be relat ed t o voltage or cur ren t sour ce values, or to oth er componentpa rameter va lues. By per forming a DC swept b ias or a swept va r iable s imula t ion , you

can check th e opera ting point of th e circuit a gainst a swept par am eter su ch a stem pera tu re or bias su pply voltage.

Use t he DC cont roller t o: Verify the pr oper DC operat ing cha ra cteristics of th e design un der t est.

Determine the power consu mption of your circuit.

Verify model param eters by compar ing the DC t ra nsfer chara cteristics (I-Vcur ves) of th e model with a ctu al mea sur ement s.

Display voltages and current s after a s imulat ion.

A DC simu lation is th e rst a na lysis for m ost other an alyses. It u ses a system of nonlinea r ordin ar y differen tia l equat ions (ODEs ) to solve for a n equ ilibriu m point inth e linea r/nonlinear algebra ic equat ions th at describe a circuit once:

Independent sources are constan t valued

Capacitors an d similar items a re replaced with open circuits

Inductors and similar items ar e replaced with short circuits

Time-derivat ives ar e const an t (zero)

Linear elemen ts ar e replaced by their condu cta nce at zero frequen cy

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55/90AC Simulation Controller 6-3

AC Simulation ControllerA linea r AC an alysis is a sma ll-signa l an alysis. For th is an alysis t he DC opera tingpoint is foun d rst a nd t hen t he nonlinea r devices ar e linear ized around t ha topera t ing point . Sma ll-signa l AC simu lat ion is a lso per form ed before a

ha rm onic-balan ce (spectr al) simula tion t o genera te an initial guess a t t he na lsolution.

Use t he AC cont roller t o:

Perform a swept-frequen cy or swept-var iable sma ll-signa l linea r A simula tion.

Obtain small-signa l tr an sfer para meters, such as voltage gain, curr ent gain,tr an simpedan ce, tr an sadmitt an ce, an d linear noise.

An AC simula tion also offers a linea r noise simu lation option th at can include t hefollowing noise cont ribu tions in its s imu lat ion:

Temperat ur e-dependent th erma l noise from lossy passive elements, includingth ose specied by da ta les.

Temperat ur e and bias-dependent noise from n onlinear devices.

Noise from linea r a ctive devices specied by two-port dat a les th at includenoise par am eters.

Noise from noise sour ce elements.The noise simulat ion compu tes t he n oise genera ted by each element , and t hendeterm ines how th at noise affects th e noise properties of th e net work .

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56/906-4


S-Parameter Simulation ControllerThe S-Para met er cont roller is us ed t o dene t he s igna l-wave response of an n-porte lect r ica l element a t a given frequency. I t is a type of small-s igna l AC s imula t ion tha tis most comm only used to cha ra cter ize a pa ssive RF component an d esta blish th esma ll-signa l cha ra cter istics of a device at a specic bias a nd t empera tu re.

Use th e S-Par am eter cont roller to:

Obt a in t h e s ca t t er in g p a ra m et er s (S -p ar a m et er s) of a com pon en t or cir cu it , a n dconvert th e pa ra met ers to Y- or Z-par am eters.

Plot, for exam ple, th e variations in swept-frequency S-para meters with respectto another cha nging var iable.

Simula te group delay.

Simula te linear noise.

Simulat e th e effects of frequen cy conversion on sma ll-signa l

S-par am eters in a circuit employing a mixer.

S-par am eter simula tion norma lly considers only th e source frequen cy in a noisean a lysis. Use t he E na ble AC Frequ ency Conver sion option if you a lso wan t t ocons ider t he frequ ency from a mixers u pper or lower s ideban d.

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57/90Harmonic Balance Simulation Controller 6-5

Harmonic Balance Simulation ControllerThe H ar monic Balan ce cont roller is best s uited for simu lating a na log RF an dmicrowave circuits. It is a frequ ency-doma in a na lysis techn ique for sim ula tin gdistort ion in n onlinear circuits an d syst ems. Within th e cont ext of high-frequen cy

circuit a nd s ystem simu lat ion, ha rm onic ba lan ce offers t he following benets overconvent iona l time-doma in tr an sient a na lysis:

It captu res the steady-sta te spectr al response directly.

Many linear models are best represent ed in th e frequency doma in at highfrequencies.

The frequency in tegra t ion required for t r ans ien t ana lys is is p roh ibit ive in manypractical cases.

Use t he H ar monic Balan ce cont roller t o: Determine the spectr al cont ent of voltages or cur rent s.

Comput e qua nt ities such as th ird-order intercept points, total ha rmonicdistort ion, a nd inter modulat ion distort ion component s.

Perform power am plier load-pull cont our an alyses.

Perform n onlinear n oise analysis .

Ha rm onic Balan ce ena bles th e mu ltitone simu lation of circuits th at exhibitint erm odu lat ion frequ ency conver sion, including frequen cy conver sion bet weenha rm onics. It is a n iterative method th at assum es th at for a given sinusoidalexcitat ion t her e exists a st eady-sta te solut ion t ha t can be appr oxima ted t o asa tisfactory a ccur acy.

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58/906-6 Harmonic Balance Simulation Controller


Simulation OverviewHarmonic balance is a frequency-domain analys is technique for s imula t ing dis tor t ionin nonlinear circuits an d systems. It obtains t he frequency-doma in voltages a ndcur ren ts to calculat e th e spectr al cont ent of voltages or cur ren ts in t he circuit. The

ha rm onic balan ce meth od is iter at ive. It is based on th e assu mpt ion t ha t for a givens inusoida l excit a t ion the re exis t s a s teady-s ta t e solu t ion tha t can be approximated tosa tisfactory accur acy by mea ns of a n ite Four ier series.

The Harmonic Ba lance solu t ion is approximated by t runca ted Four ie r ser ie s and th ismet hod is inh erent ly incapa ble of repr esent ing tra nsient behavior. Thetim e-der iva tive can be comp ut ed exa ctly with boun da ry cond itions, v(0)=v(t),au tomat ically satised for all itera tes.

The tr un cat ed Four ier approximat ion + N circuit equa tions r esults in a r esidual

fun ction t ha t is m inimized.N x M nonlinea r a lgebra ic equa tions a re solved for t he Four ier coefcient s u singNewt ons met hod an d th e inner linear pr oblem is solved by:

Direct meth od (Gaussian elimina tion) for sm all problems

Krylov-subspa ce met hod (e.g. GMRES) for la rger pr oblems

Nonlinear devices (transistors, diodes, etc.) in Harmonic Balance are evaluated(sam pled) in t he time-doma in a nd convert ed t o frequen cy-doma in via t he FF T.

Advantages Ha rm onic balance capt ur es the steady-sta te spectr al response directly while

convent iona l tra nsient met hods need to int egrat e over ma ny periods of th elowest-frequen cy sinu soid to r each st eady st at e.

Ha rm onic balance is fast er a t solving typical h igh-frequency problems t ha ttr an sient an alysis cant s olve accur at ely or can only do so at p rohibitive cost s.

Ha rm onic balance is more accur at e at solving high frequencies where manylinea r m odels ar e best r epresent ed in t he frequen cy doma in.

ConvergenceNonconvergence is a nu mer ical pr oblem encoun ter ed by th e ha rm onic balancesimula tor when it cann ot rea ch a solution, within a given tolera nce, after a given

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nu mber of nu mer ical it era tions. Ther e is no one s pecic solut ion for solvingconvergen ce pr oblems. H owever, consider the following gu idelines :

I ncr ea s e t h e Or der (or ot h er h a r m on ic con t r ols ); t h is is t h e m os t ba s ic t ech n iqu efor solving convergence problems, if the time penalty for doing so is acceptable.

U se t h e S ta t u s s er ver win dow a s t h e m a in t ool in s olvin g con vergen ce p roblem s(set Sta tu sLevel=4). For each Newton iter at ion th e L-1 norm of the r esidualsth rough out th e circuit is pr int ed: a * indicates a full Newton st ep (vs. aSama nskii step).

Convergence criter ia ar e cont rolled by Voltage relat ive toleran ce, an d Curr entrelat ive t oleran ce (in t he Options component , un der th e Convergence t ab). Ingenera l, convergence speed is impr oved by increa sing th ese values, but a t th eexpense of a ccur acy. Similar ly, th e sma ller t hes e values a re, th e more accur at eth e resu lts but th e slower th e convergence.

Newton convergence issues with Kr ylov methods (becau se linea r pr oblemsolut ions can only appr oximat e) ca n be impr oved by us ing bett erpreconditioners.

Set the Oversample parameter t o a value greater t han 1.0, such a s 2.0 or 4.0.However, remember that a l though this can often solve convergence problems, itdoes so at th e cost of comp ut er m emory an d simu lat ion t ime. For m ult iple-toneha rm onic balance simulations, mak e sur e th at th e largest signa l in th e circuitis assigned t o Fr eq[1]. The simulat or s F FT a lgorith m is set up so tha t aliasingerr ors ar e mu ch less likely to affect Fr eq[1] th an an y oth er t one.

Wh en u sin g a d ir ect lin ea r s olver, t h e block s of t h e H a r m on ic Ba la n ce J a cobia nin h er it t h e J a cobia n m a t r ix or der in g fr om t h e DC s olu t ion p roces s. Th is m a t r ixord erin g ca n gr eat ly affect t he efciency of th e Ha rm onic Balan ce J acobianfa ctorizat ion, a nd in some circuit s sh ow noticea ble simu lat ion slowdown. Tocircum vent t his issu e, us e a DC conver gence mode th at ha sn t cha nged, e.g.DC_ConvMode=3.

For n on -con vergen ce d ue t o t igh t t oler a n ces, m on it or t h e r es id ua ls in t h e S ta t u sSer ver win dow.

I ncr ea s e I _Abs Tol if t h e cir cu it is con vergin g t o wit h in a few p A bu t n ot qu it et oI_AbsTol=1pA

Increase I_RelTol if th e problem is with nodes associated with large cur ren ts

Increase I_AbsTol if th e sma ll cur rent nodes ar e th e issue

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60/906-8 Harmonic Balance Simulation Controller


Relax voltage tolera nces for failur e in t he Newton upd at e criter ion

Th e in t er n a l cir cu it s im u la t or en gin e in ADS (Gem in i) r u n s fr om a n et lis t . ADSwrit es a net list le (net list.log) before in vokin g Gemini. The order of th ecomponent s an d model denitions in t he n etlist determ ine th e initia l Ja cobianma tr ix ord erin g. This ma tr ix ord erin g can affect t he efciency of th e J acobianfa ctorizat ion a nd cau se eith er a simu lat ion slow down or n on-conver gence.

For convergence problems due to err ors in th e component m odel equat ions(incorr ect d erivat ives, etc.) ma ke su re a ncient Ber keley MOSFE T Level 1, 2, 3ar e not th e culprit a nd t ha t t he lat est m odel version is us ed (especially BSIM3models). Model problems can cau se th e Newton residua l to hit a th resh old(great er t ha n th e convergence criter ia t oleran ces) an d st ale th e convergenceprocess or even exhibit r an dom jum ps (sudden increase in value). Set t hedevices Xqc pa ra met er t o a n onzer o value t o allow th e simu lat or t o us e a

cha rge-based m odel for t he ga te capa cita nce. This often ena bles conver gence,but at th e cost of extracting an extr a SPICE m odel param eter.

Sweeps as Convergence Tools

Cont inua t ion methods provide a sequence of in it ia l guesses tha t a re sufcien t ly closeto the solut ion to assure Newtons method convergence in Harmonic Balance. Sweepscan be used to form ulat e a specialized cont inua tion m eth od geared t owards th epar ticular circuit problem.

Sweep a circuit element th at , when set to some different value, ma kes t he circuitmore linea r. For inst an ce, in an am plier circuit t her e may be a resist or t ha t can beu sed t o lower t h e a m plier s ga in . Th e s im u la t or m a y be a ble t o n d a solu t ion t o t h ecircu it under a low-ga in cond it ion . Then , if the componen t s va lue is swept toward thedesired value, the simu lator ma y be able to nd a na l solution. Sta rt with a valueth at work s, an d stop with t he desired value. Also, select Resta rt , un der t he Par am sta b. Usu ally, a bett er initial guess a t ea ch st ep helps th e simulat or t o converge.

The t wo ma in ways to perform sweeps are:

HB sweep with in th e HB cont roller. This is preferr ed for m ost s weeps, exceptfrequency.

Param eter sweep using a separa te sweep contr ol ler.

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Convergence and Samanskii Steps

The Sa ma nsk ii steps can signican tly speed up th e solution process. However, usingan approximate Jacobian , pa r t icu la r ly for a la rge r number of it e ra t ions, may resu lt inpoor or even n o conver gence. The cons ta nt is us ed in t wo ways. First , it becomes a

more a bsolute measu re when it is sma ller. It th en a pproaches the requirement th ateach iter at ion r educes th e relevant norm by one-third.

Decr ea s in g t h e S am a n sk ii con s ta n t beyon d a cer t a in p oin t (wh ich in t u r n d ep en ds onthe qua lity of the mos t recen t Newton s tep) will make no d iffe rence. However, set t ingth e Sa ma nsk ii const an t to zero will effectively disable any Sa ma nsk ii stepsaltogether.

Increasing the Sa ma nskii const an t r elaxes this requirements in general, but th econdition becomes m ore dependen t on th e qua lity of th e sta nda rd most r ecentNewton it e ra t ion . In othe r words, a more rap id convergence of the Newton s tep wouldalso require bett er convergence of th e Sam an skii steps.

Convergence and Arc-Length Continuation

Arc-length cont inua tion is a n extremely robust algorith m. If it fails, try a ll oth erconvergence remedies rst before a djusting a rc-length p ar am eters

MaxStepRat io cont rols the ma ximu m n um ber of cont inuat ion st eps (defau lt100)

MaxShrinkage cont rols the m inimum size of th e ar c-length step (defau lt 1e-5)

Ar cMa xSt ep lim it s t h e m a xim u m s ize of t h e a r c-len gt h s tep (defa u lt is 0, i.e. n olimiting)

ArcMinValue & ArcMaxValue dene t he a llowed ran ge for t he var iation of th econt inuat ion para meter

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62/906-10 Circuit Envelope Simulation Controller


Circuit Envelope Simulation ControllerThe Circuit E nvelope cont roller is best s uit ed for a fa st a nd comp lete an alysis of comp lex signa ls such as digita lly modula ted RF s ignals. It combin es feat ur es of tim ean d frequen cy-doma in repr esent at ion by perm itting inpu t waveform s to be

repr esent ed in t he frequency doma in a s RF car riers, with modulation envelopesth at a re represented in th e time doma in.

Circuit E nvelope is highly efcient in a na lyzing circuits wit h digita lly modula tedsigna ls, becau se th e tr an sient simulation ta kes place only around t he carrier a nd itsha rm onics. In a ddition, its calculat ions ar e not ma de where t he spectru m is empt y.

It is fast er t ha n H ar monic Balance, for a given complex signal Spice, assum ing

most of th e frequen cy spectr um is empt y It does not compr omise in Signal complexity, unlike time-var ying H B or

Sh ootin g Meth od Componen t accur a cy, un like Spice, Shootin g Meth od, or DSP

It a dds physical an alog/RF performa nce to DSP/system simulation withrea l-tim e co-simu lat ion wit h ADS Pt olemy

I t is in t egr a t ed in s a me d es ign en vir on m en t a s RF, S pice, DS P, elect r om a gn et ic,instr um ent link s, and ph ysical design t ools

Advantages over Harmonic Balance

In H ar monic Balan ce, if you a dd nodes or m ore spectr al frequen cies, th e RAMan d CPU requ irem ent s increa se geomet rically. Krylov impr oved th is, but itsstill a limita tion of Ha rm onic Balan ce becau se th e signa ls ar e inher ent lyperiodic.

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63/90Circuit Envelope Simulation Controller 6-11

Conversely the penalty for more spectr al density in Circuit En velope is linear: just add more t ime points by increasing TSTOP. The longer you simulat e, thener your resolut ion ban dwidth.

Doing a large nu mber of simple 1-tone HB simu lations is effectively fast er a ndless RAM intens ive th an one h uge HB simula tion.

With a circuit envelope simulat ion th e amplitu de and phase at each spectr alfrequen cy can vary with t ime, so th e signa l represent ing the h ar monic is nolonger limited to a const an t, as it is with ha rm onic balan ce.

Limitations

1. More occupied spectr um th an un occupied spectr um .

Youre car rying more overh ead with frequ ency-doma in a ssu mp tions a nd

ha rm onics th an necessa ry. Use SPICE .

2. Everything baseband. Depends.

If everyth ing linea r, use AC/S-par am eter (for n oise or bu dget)

If everything nonlinear or digital, use SPICE.

If everyth ing logic/beha viora l, us e PTOLE MY.

3. Occupied spectr um is relatively spars e.

If you can do wha t you want using H ar monic Balan ce, you should.Post-processing, opt imizat ion, an d yield ar e simpler a nd fast er.

Simulation Process1. Tran sform input signal

Ea ch modulated signa l can be represent ed as a car rier modulat ed by an

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64/906-12 Circuit Envelope Simulation Controller


envelope - A(t)*ejf(t). The va lues of am plitu de a nd ph a se of th e sa mpledenvelope ar e used a s inpu t signa ls for H ar monic Balan ce an alyses.

2. Fr equency Doma in Ana lysis

Harmonic Ba lance ana lys is is per formed a t each t ime s tep. Th is p rocess crea tesa s uccession of spectr a t ha t char acterize the r esponse of th e circuit a t t he

different time s teps.3. Time Doma in Ana lysis

Circuit E nvelope pr ovides a comp lete n on s tea dy-st at e solut ion of th e circuitthrough a Fourier series with time-varying coefcients.

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4. Extra ct Dat a from Time Doma in

Select ing th e desired h a rm onic spectr al line (fc in t his case), it is possible toanalyze:

Amplitude vs. Time (Oscillator st ar t u p, Pu lsed RF r esponse, AGCtransients)

Ph as e (f) vs. Time (t) (VCO inst an ta neous frequ ency (df/dt ), PLL lock t ime)

Amplitude & Ph as e vs. Time (Const ellat ion plots, EVM, BER)

5. Extra ct Dat a from F requency Doma in

By applying FF T to th e selected t ime-var ying spectr al line it is possible toanalyze:

Adjacent Cha nn el Power Ratio (ACPR)

Noise Power Ratio (NPR)

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66/90

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Amplier ha rmonics in th e t ime domain.

Subsystems using modulation signa ls such as multilevel FSK, CDMA, orTDMA.

Third-order-intercept an d higher-order int ercept a na lyses of am pliers an d

mixers. Time-doma in optimizat ion of tr an sient responses.

Typical Applications

Time Domain Data Extraction

Selecting t he desired h ar monic spectr al line it is possible t o ana lyze:

Amplitude vs . Time

Oscillator sta rt u p

Pu lsed RF response

AGC tra nsients

P h a se vs. Tim e

VCO ins ta nt an eous frequ ency, PLL lock t ime

Amplitude & phase vs . t ime

Constellation plots

E VM, BER

Frequency Domain Data Extraction

By applying FF T to th e selected t ime-var ying spectr al line it is possible to an alyze:

Adjacent Cha nn el Power Rat io (ACPR)

Noise Power Ratio (NPR)

Power a dded efciency

Reference frequency feedth rough in PLL

Higher order intermods (3rd, 5th, 7th, 9th)

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68/906-16 LSSP Simulation Controller


LSSP Simulation ControllerThe lar ge-signa l S-par am eter simulat ion cont roller facilita tes th e compu ta tion of large-signa l S-par am eters in nonlinea r circuits.

Lar ge-signa l S-par am eters a re bas ed on a ha rm onic balan ce simulat ion of th e fullnonlinea r circuit. Unlike S-par am eters, lar ge signa l S-par am eters can chan ge aspower levels ar e varied becau se th e ha rm onic balan ce simula tion in cludes nonlineareffects su ch a s comp res sion.

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69/90XDB Simulation Controller 6-17

XDB Simulation ControllerThe XDB simu lat ion cont roller comp ut es th e gain comp res sion point of an am plieror m ixer. It sweeps th e input power u pward from a sma ll value, stopping when th erequired a mount of gain compr ession is seen a t t he outpu t.

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70/906-18 Transient/Conv. Simulation Controller


Transient/Conv. Simulation ControllerThe t ra nsient an d convolution simula tion cont rollers solve a set of integro-different ial equa tions t ha t express t he t ime dependence of th e cur ren ts a ndvolt a ges of t h e cir cu it . Th e r es ult of s u ch a n a n a lys is is n on lin ea r wit h r es pect t o t im e

an d, possibly, a swept var iable.

Use the Transient/Convolution controller to perform:

SPICE-type tra nsient t ime-domain an alysis .

Nonlinear tr an sient an alysis on circuits t ha t include the frequency-dependentloss a nd disper sion effects of linea r models, or Convolut ion a na lysis.

A t rans ien t ana lys is is per formed en t ir ely in the t ime-domain . I t does not accoun t forth e frequency-dependent behavior of distr ibuted element s.

A convolution a na lysis represen ts dist ribut ed elemen ts in th e frequen cy doma in toaccoun t for t heir frequ ency-depen den t beh avior.

Transient Simulation and ConvergenceIn Tra nsient a na lysis a nu mer ical integra tion a lgorith m is employed at each timepoint to appr oxima te t he different ial equat ions into algebra ic equat ions. Int egrat ionmet hods ar e used t o replace the t ime derivat ive with a discrete-time a pproximat ion

Time Step Control Characteristics

Local Tr un cat ion Er ror

Est imates th e LTE ma de on every capacitor a nd inductor

Determines the t ime step size to ensure th e largest LTE remains within th eaccepted tolerance

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71/90Transient/Conv. Simulation Controller 6-19

The estimat ed LTE is inversely proport iona l to Trun cTol

Th e a ccep ted t oler a n ce d ep en ds u p on t h e r ela t ive a n d t r u n ca t ion t oler a n ces s etfor t he cur ent an d volta ge. It is proport iona l to I_RelTol x Trun cTol an dV_RelTol x Tr uncTol

Iteration-Count Determines the time step size based on th e number of Newton iterat ions

requ ired for pr evious t ime point

No direct relationsh ip between itera tions an d LTE

Effectively cont rolled by Max time s tep (for linea r circuits)

Fixed

The t ime step is xed and equal to Max t ime step

Break Points

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