A 3D Finite Element Parallel Simulator forStudying Fluctuations in Advanced  MOSFETs

M. Aldegunde∗, A. J. Garcı́a-Loureiro∗, K. Kalna†, and A. Asenov†

∗Department of Electronics and Computer Science, University of Santiago de Compostela,15782 Santiago de Compostela, Spain. E-mail: maldegunde@dec.usc.es

†Device Modelling Group, Department of Electronics & Electrical Engineering,University of Glasgow, Glasgow G12 8LT, United Kingdom

Polysilicon gates and high-κ dielectrics used intoday’s MOSFETs are a serious source of intrinsicparameter fluctuations in addition to the randomdopants in the channel, source and drain, the lineedge, and interface roughness [1]. Limits in dopingactivation in the polysilicon gate and the dopingdepletion near the interface result in an unwantedpoly depletion effect [2]. The grain structure of thepolysilicon is one of the main contributors to thefluctuations, leading to a mismatch in the thresholdvoltage of sub-100 nm MOSFETs.

Most of the high-κ dielectrics exhibit a thermalinstability which leads to local crystallisation of theinitially amorphous layer. Regions with differentdielectric constant appear which contribute to theintrinsic parameter fluctuations in a device.

In this work, we investigate intrinsic parameterfluctuations introduced by the polysilicon gate andthe high-κ dielectric layer using a 3D parallel devicesimulator. The simulator employs the finite elementdiscretisation in a drift-diffusion (D-D) approxima-tion for the electron transport and runs in parallelemploying MPI standard library. We have developedan efficient tetrahedral unstructured mesh generatordesigned to deal with complicated geometry appear-ing in sub-100 nm advanced Si MOSFETs in thepresence of fluctuations. The mesh is refined closeto the boundaries between different regions of thetransistor and the zones with the highest variationsin the electrostatic potential resulting in a meshillustrated in Fig. 1. This meshing is also suitablefor an accurate description of the polysilicon grainboundaries illustrated in Fig. 2. The simulationdomain is partitioned into sub-domains shown inFig. 3 and assigned to individual processors.

The 3D parallel D-D MOSFET simulator has

been calibrated with respect to an n-type 67 nmeffective gate length Si MOSFET [3]. Fig. 4 com-pares ID-VG characteristics obtained from the 3D D-D parallel simulator with experimental data. It alsoshows results obtained when the SiO2 gate dielectricis replaced with a high-κ one with a dielectricconstant of 20 (HfO2), and results when consid-ering an interfacial layer of SiO2 together withrelatively large polycrystalline islands of differentdielectric constants in the gate dielectric. Finally, theresults obtained assuming a Gaussian distributionof different dielectric constants with a correlationlength of 3 nm mimicking fine grains of differentorientations in the high-κ gate dielectric layer arepresented as well. Fig. 5 shows a semilogarithmicplot of electron density in the 67 nm MOSFET.The effect of intrinsic parameter fluctuations in thepolysilicon gate and in the high-κ dielectric layerwill be also studied in a template 25 nm gate lengthbulk MOSFET. As an example, in Fig. 6, we showthe electron density right below the semiconductor-insulator interface in the case when the dielectriclayer consists of two regions with different dielectricconstant separated by a plane y = 0.

REFERENCES

[1] A. Asenov and S. Saini, Polysilicon gate enhancement ofthe random dopant induced threshold voltage fluctuationsin sub-100 nm MOSFETs with ultrathin gate oxide, IEEETrans. Electron Devices 47, 805 (2000).

[2] P. R. Suresh, P. Venugopal, S. T. Selvam and S.Potla, Combined Effect of Grain Boundary Depletion andPolySi/Oxide Interface Depletion on Drain Characteristicsof a p-MOSFET, Proc. IEEE Int. Conf. VLSI Design, 156(1996).

[3] K. Rim et al., Strained Si NMOSFETs for high performanceCMOS technology, Symp. VLSI Technol., Dig. Tech. Pap.,59 (2001).

Fig. 1. Finite element mesh for simulation of the 67 nmeffective gate length Si MOSFET with a polysilicon gate.

Y

X

Z

Fig. 2. Detail of a gate meshed for the simulation of threegrains in polysilicon.

Fig. 3. Partition of the finite element mesh in three subdo-mains.

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1.00E+01

1.00E+02

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40

Vgs(V)

I(A

/m)

Experimental Vd=0.05 V

SiO2 Oxide

Interfacial layer+islands

Gaussian fluctuations

Uniform high-k

Fig. 4. ID −VG characteristics obtained from the 3D D-D parallel simulator compared with experimental data for the67 nm effective gate length Si MOSFET.

0

0.02

0.04

0.06

0.08

0.1

0.12

Z(u

m)

-0.1

-0.05

0

0.05

0.1

X (um)

-0.0150

0.015Y (um)

N19.342518.05316.763515.47414.184512.89511.605510.3169.026487.736986.447485.157993.868492.578991.2895

Fig. 5. Electron density on log scale in the 67 nm effectivegate length Si MOSFET at VG = 0.5V and VD = 0.05V .

14

16

18

20

log(n)

-0.04

-0.02

0

0.02

0.04

X (um)-0.02

0

0.02

Y (um)

N19.483418.690317.897217.104116.31115.517914.7248

Fig. 6. Electron density at equilibrium beneath a dielectriclayer with two different dielectric constants of 7 (Si3N4) and5 in the template 25 nm gate length bulk MOSFET.