A Wholly Owned Subsidiary of Comtech Telecommunications Corp

LDPC Codes

What is an LDPC code?• PC � Parity Check• PC � Parity Check

- Parity Check: each step in the decoding process does a parity check operation.does a parity check operation.

• LD � Low Density- The parity check matrix for the code has a small - The parity check matrix for the code has a small

number of 1’s LDPC’s are typically specified by the parity check matrixparity check matrix

Low Density Parity Check Codes

• LDPC’s are linear block codes. • LDPC’s are linear block codes. • Described by a parity check matrix.

- Most codes are described by a generator function - Most codes are described by a generator function or matrix.

- Typically less than 0.1% of the elements in the H - Typically less than 0.1% of the elements in the H matrix are ones.

• Extremely configurable for block size and • Extremely configurable for block size and code rate

• Decoders are computationally intensive.• Decoders are computationally intensive.• Decoders “iterate”

Comtech AHA LDPC Cores• 4701• 4701

- Code Block sizes of 16K and 30K- Code rates from .5 to .75- Code rates from .5 to .75

• 4702- DVB-S2 Codes- DVB-S2 Codes- Code Block sizes of 16K and 64K- Rates from .25 to .9- Rates from .25 to .9

• Custom LDPC Cores- User defined data block size- User defined data block size- User defined code rates

Performance of LDPC CodesPerformance of LDPC Codes

Channel Capacity CurvesCode Rate vs PerformanceCode Rate vs Performance

Eb/No at BER=10-8

1.0

0.7

0.8

0.9

0.5

0.6

0.7

Cod

e R

ate

Shannon Limit (BPSK)

0.3

0.4TPC 4K blocks

TPC 16K blocks

Reed-Solomon/Viterbi

LDPC 30K

LDPC 16K

0.20.0 1.0 2.0 3.0 4.0 5.0

Eb/No (dB)

AHA4701 LDPC Core

• Up to 30 Mbps data rates• Up to 30 Mbps data rates• Block Sizes of 16K and 30K bits• Up to 256 Maximum Iterations per Block• Up to 256 Maximum Iterations per Block• Code rates of 1/2, 2/3, and 3/4 • Targeted at Altera Stratix FPGAs

AHA4702 DVB-S2 LDPC Core

• Channel rate up to 233 Mbps • Supports 21 Code rates• Fully compliant with DVB-S2 Satellite Standard• Block Sizes of 64K or 16K bits• Block Sizes of 64K or 16K bits• Up to 6-bits Soft Decision Input • Up to 256 iterations• LDPC Inner Code• LDPC Inner Code• BCH Outer Code• CCM, ACM and VCM compliance

DVB-S2 Performance (AHA 4702)

5

4

4,5

5

32APSKDotted lines = modulation constrained Shannon Limit

3

3,5

4

Ru

[Mbi

t/sec

] per

uni

t Sym

bol r

ate

Rs

DVB-S2

16APSK

2

2,5

3

Ru

[Mbi

t/sec

] per

uni

t Sym

bol r

ate

Rs

DVB-DSNG

8PSK

8PSK

16QAM

1

1,5

2

Ru

[Mbi

t/sec

] per

uni

t Sym

bol r

ate

Rs

DVB-DSNG

QPSK

DVB-S

8PSK

0

0,5

-4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17-4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

C/N [dB] in BW=Rs

AHA4702 DVB-S2 LDPC CoreCompare FPGA to ASICCompare FPGA to ASIC

FPGA ASIC

User Data Rate 86 Mbps 155 Mbps(2/3 CR, 25 iter)

Channel Rate 120 Mbps 233 Mbps

Power consumption 14 W 4 WPower consumption 14 W 4 W

LDPC Core, Compare

Core User Data Channel Target FPGARate (Mbps) Rate (Mbps)

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------AHA4701 25 (CR = 2/3) 40 Altera Stratix-30

AHA4702 86 (CR = 2/3) 130 Altera Stratix IIAHA4702 86 (CR = 2/3) 130 Altera Stratix IIEP2S130

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LDPC Core Deliverables

• Synthesized Netlist, VHDL or Verilog• Synthesized Netlist, VHDL or Verilog• Simulation Netlist• Test Bench with Test Vectors• Test Bench with Test Vectors• Limited Technical Support

LDPC Evaluation Software

• Allows system level simulation• Allows system level simulation• Operating systems supported: Windows, Linux• Code platform is both Matlab and “C/C++”• Code platform is both Matlab and “C/C++”• Software includes examples• User manual (PSLDPC_STK)

LDPC Evaluation SoftwareExample System SimulationExample System Simulation

DATAGENERATOR

LDPC ENCODER

BPSK,GAUSSIANCHANNEL

LDPCDECODER

COMPARE OUTPUTWITH ORIGINAL,COUNT ERRORS

LDPC Evaluation SoftwareRun SoftwareRun Software

1) Configure the Encoder and Decoder1) Configure the Encoder and Decoder

2) Run data through the system2) Run data through the system

3) Compare decoded output block againstoriginal data for uncorrected errors.