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The Pennsylvania State University
The Graduate School
Department of Computer Science and Engineering
A TIQ BASED CMOS FLASH A/D CONVERTER
FOR SYSTEM-ON-CHIP APPLICATIONS
A Thesis in
Computer Science and Engineering
by
Jincheol Yoo
c© 2003 Jincheol Yoo
Submitted in Partial Fulfillmentof the Requirements
for the Degree of
Doctor of Philosophy
May 2003
We approve the thesis of Jincheol Yoo.
Date of Signature
Kyusun ChoiAssistant Professor of Computer Science and EngineeringThesis AdviserChair of Committee
Mary Jane IrwinDistinguished Professor of Computer Science and Engineering
Vijaykrishnan NarayananAssistant Professor of Computer Science and Engineering
Charles L. CroskeyProfessor of Electrical Engineering
Raj AcharyaProfessor of Computer Science and EngineeringHead of the Department of Computer Science and Engineering
iii
Abstract
The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC)
products because it bridges the gap between the analog physical world and the digital
logical world. In the digital domain, low power and low voltage requirements are be-
coming more important issues as the channel length of MOSFET shrinks below 0.25
sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with
other digital circuits. These trends present new challenges in ADC circuit design. Thus,
this thesis is to investigate high speed, low power, and low voltage CMOS flash ADCs
for SoC applications.
The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique
that uses two cascaded CMOS inverters as a comparator. The TIQ technique has been
introduced in [53]. The TIQ technique proposed here has been developed for better
implementation in SoC applications. Four issues are addressed to achieve high speed,
low power consumption, and low voltage operation in the TIQ flash ADC. First, the high
speed and low power TIQ flash ADC architecture is presented along with an optimal
design method - called the systematic size variation (SSV) technique - for reducing the
impacts of the process variation. Second, a new digital encoder called the fat tree encoder
is introduced. The fat tree encoder replaces the ROM type encoder that is the speed
bottleneck. Next, for low power applications, a power and resolution adaptive flash ADC
(PRA-ADC) and a power management method in the TIQ flash ADC are presented
to reduce/manage power consumption. Finally, a new voltage comparator, called the
iv
Quantum Voltage (QV) comparator, for next generation deep sub-micron low voltage
CMOS flash ADC is proposed. In addition to the above four issues, simulation results
and fabrication results of the TIQ flash ADC are discussed. The preliminary results
show that the TIQ flash ADC achieves high speed, small size, low power consumption,
and low voltage operation compared to other ADCs.
v
Table of Contents
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
Chapter 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Challenges in Designing ADCs for SoC . . . . . . . . . . . . . . . . . 1
1.2 Solid-State Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2. A/D Converter Background . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 Static Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1.1 Offset and Gain Error . . . . . . . . . . . . . . . . . 8
2.1.1.2 Differential Non-Linearity Error (DNL) . . . . . . . 9
2.1.1.3 Integral Non-Linearity Error (INL) . . . . . . . . . . 11
2.1.2 Dynamic Parameters . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2.1 Signal-to-Noise Ratio (SNR) . . . . . . . . . . . . . 12
2.1.2.2 Signal-to-Noise and Distortion Ratio (SINAD) . . . 13
2.1.2.3 Total Harmonic Distortion (THD) . . . . . . . . . . 13
2.1.2.4 Effective Number of Bits (ENOB) . . . . . . . . . . 14
vi
2.1.2.5 Spurious-Free Dynamic Range (SFDR) . . . . . . . 14
2.2 ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.3 Successive Approximation ADC . . . . . . . . . . . . . . . . . 20
2.2.4 Σ∆ ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.5 Summary of ADC Architectures . . . . . . . . . . . . . . . . 23
Chapter 3. TIQ Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 TIQ Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.1 CMOS Inverter as a Comparator . . . . . . . . . . . . . . . . 27
3.1.1.1 Sensitivity to Process . . . . . . . . . . . . . . . . . 29
3.1.1.2 Sensitivity to Temperature . . . . . . . . . . . . . . 30
3.1.1.3 Sensitivity to Power Supply Voltage . . . . . . . . . 31
3.1.2 Comparator Generation and Selection Method . . . . . . . . 31
3.1.2.1 Random Size Variation (RSV) Technique . . . . . . 33
3.1.2.2 Systematic Size Variation (SSV) Technique . . . . . 33
3.2 Gain Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3 TC-to-BC Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.1 ROM Type Encoder . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.2 Fat Tree Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 4. Experimental Results and Evaluations . . . . . . . . . . . . . . . . . 43
4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
vii
4.1.1 TIQ Flash ADC Performance . . . . . . . . . . . . . . . . . . 45
4.1.1.1 Simulation Results of 0.25 µm technology . . . . . . 49
4.1.1.2 Simulation Results of 0.18 µm technology . . . . . . 56
4.1.1.3 Simulation Results of 0.50 µm technology . . . . . . 60
4.1.2 Variation Effects on the RSV and SSV Techniques . . . . . . 64
4.1.3 Fat Tree Encoder vs. ROM Type Encoders . . . . . . . . . . 68
4.2 Fabrication Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2.1 Test Results of 0.25 µm TIQ flash ADC Chips . . . . . . . . 71
4.2.2 Test Results of 0.18 µm TIQ flash ADC Chips . . . . . . . . 76
4.2.2.1 Noise effects on the ADCs . . . . . . . . . . . . . . . 78
4.2.2.2 Fast Fourier Transform (FFT) Test Results . . . . . 81
4.2.3 Test Results of 0.50 µm TIQ flash ADC Chips . . . . . . . . 83
Chapter 5. Low Power Applications with TIQ Comparator . . . . . . . . . . . . 84
5.1 The Power and Resolution Adaptive Flash ADC (PRA-ADC) . . . . 84
5.1.1 PRA-ADC Design and Layout . . . . . . . . . . . . . . . . . 85
5.1.2 PRA-ADC Simulation Results . . . . . . . . . . . . . . . . . 90
5.1.3 Summary of the PRA-ADC . . . . . . . . . . . . . . . . . . . 93
5.2 A Power Management Method in the TIQ Flash ADC . . . . . . . . 93
5.2.1 Power Management Method . . . . . . . . . . . . . . . . . . . 95
5.2.2 Power Simulation Results . . . . . . . . . . . . . . . . . . . . 97
5.2.3 Summary of the Power Management Method . . . . . . . . . 99
Chapter 6. Low Voltage Operation in ADCs . . . . . . . . . . . . . . . . . . . . 101
viii
6.1 Low Voltage Operation with the TIQ flash ADC . . . . . . . . . . . 102
6.1.1 Power Analysis of the TIQ flash ADC . . . . . . . . . . . . . 103
6.1.2 Voltage and Temperature Variations in 0.07 µm . . . . . . . . 106
6.2 Quantum Voltage Comparator . . . . . . . . . . . . . . . . . . . . . 108
6.2.1 Simple Transconductance Amplifier . . . . . . . . . . . . . . . 109
6.2.2 Flash ADC with QV comparator . . . . . . . . . . . . . . . . 110
6.2.2.1 The QV Comparator . . . . . . . . . . . . . . . . . 112
6.2.2.2 ADC Design with QV comparator . . . . . . . . . . 114
6.2.3 Simulation Results and Comparisons with TIQ Comparator . 116
6.2.3.1 Power Consumption Comparison with TIQ Compara-
tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2.3.2 Noise Comparisons with TIQ Comparator . . . . . . 119
6.2.4 Summary of the QV Comparator . . . . . . . . . . . . . . . . 119
Chapter 7. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Appendix A. DNL and INL Calculating Program . . . . . . . . . . . . . . . . . 137
Appendix B. MOSIS Parametric Test Results for TSMC 0.25 µm CMOS Run . 139
Appendix C. MOSIS Parametric Test Results for TSMC 0.18 µm CMOS Run . 143
Appendix D. MOSIS Parametric Test Results for AMI C5 (0.50 µm) Run . . . . 147
ix
List of Tables
2.1 Summary of ADC architectures . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Comparator transistor sizes used in 0.25 µm design . . . . . . . . . . . . 49
4.2 Simulation results of 0.25 µm TIQ flash ADCs . . . . . . . . . . . . . . 50
4.3 Process variation result in an 8-bit TIQ flash ADC . . . . . . . . . . . . 52
4.4 Temperature and power supply voltage variation results in the 8-bit TIQ
flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5 Simulation results of 0.18 µm TIQ flash ADCs . . . . . . . . . . . . . . 56
4.6 Variation results in a 0.18 µm 8-bit TIQ flash ADC . . . . . . . . . . . 58
4.7 Absolute currents used by each component . . . . . . . . . . . . . . . . 59
4.8 Simulation results of the 8-bit 0.50 µm TIQ flash ADC . . . . . . . . . . 62
4.9 Variation results in a 0.50 µm 8-bit TIQ flash ADC . . . . . . . . . . . 63
4.10 The effects of process variations and RSV and SSV design techniques . . 66
4.11 DNL and INL for temperature and power supply voltage variations using
the RSV and SSV design techniques . . . . . . . . . . . . . . . . . . . . 67
4.12 Summary of the simulation results with two encoders . . . . . . . . . . . 69
4.13 Summary of 0.25 µm chip test results . . . . . . . . . . . . . . . . . . . 72
4.14 ADC Signal delay test results . . . . . . . . . . . . . . . . . . . . . . . . 74
4.15 Summary of 0.18 µm chip test results . . . . . . . . . . . . . . . . . . . 78
5.1 Summary of the PRA-ADC simulation results . . . . . . . . . . . . . . . 90
x
5.2 Power simulation results of the 6-bit and 8-bit ADC . . . . . . . . . . . 99
6.1 Summary of the simulation results in 0.07 µm technology . . . . . . . . 102
6.2 Comparisons with other low-voltage ADCs . . . . . . . . . . . . . . . . . 103
6.3 Power analysis of the TIQ flash ADC by components . . . . . . . . . . . 106
6.4 Power supply voltage and temperature variation results from the 0.07
µm 8-bit TIQ flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.5 Summary of the QVC ADC simulation results . . . . . . . . . . . . . . . 116
6.6 Power Consumption Comparisons with TIQ Comparator . . . . . . . . . 118
6.7 Power supply voltage and temperature variations results . . . . . . . . . 120
7.1 Comparison the TIQ flash ADC with other ADCs . . . . . . . . . . . . 124
xi
List of Figures
2.1 Staircase transfer function of an ADC . . . . . . . . . . . . . . . . . . . 7
2.2 Offset and gain errors, after [32] . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Differential non-linearity error (DNL) . . . . . . . . . . . . . . . . . . . 10
2.4 Integral non-linearity error (INL) . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Tradeoff between resolutions and sampling rates . . . . . . . . . . . . . 16
2.6 Block diagram of a flash ADC . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 Block diagram of an 8-bit sub-ranging ADC . . . . . . . . . . . . . . . . 18
2.8 Block diagram of a pipelined ADC . . . . . . . . . . . . . . . . . . . . . 19
2.9 Block diagram of a successive approximation (SAR) ADC . . . . . . . . 20
2.10 Reference voltage tree in a 3-bit SAR ADC . . . . . . . . . . . . . . . . 21
2.11 Block diagram of a Σ∆ ADC . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Block diagram of the TIQ flash ADC . . . . . . . . . . . . . . . . . . . . 26
3.2 Inverter schematic and VTC . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 The 3-D plot of the inverter switching threshold voltages, Vm, as the
function of PMOS and NMOS transistor widths . . . . . . . . . . . . . . 32
3.4 Two 6-bit TIQ comparators produced by two design techniques . . . . . 34
3.5 An example of the SSV technique . . . . . . . . . . . . . . . . . . . . . . 36
3.6 Gain booster propagation delay result vs. gate length . . . . . . . . . . 37
3.7 Gain booster voltage gain result vs. gate length . . . . . . . . . . . . . . 38
3.8 The two steps for TC-to-BC encoder . . . . . . . . . . . . . . . . . . . . 39
xii
3.9 ROM type encoder of a 3-bit ADC . . . . . . . . . . . . . . . . . . . . . 40
3.10 Example of the 3-bit fat tree encoder . . . . . . . . . . . . . . . . . . . . 41
4.1 Layout of a 8-bit TIQ flash ADC with fat tree encoder . . . . . . . . . . 44
4.2 DC simulation results of a 6-bit TIQ flash ADC . . . . . . . . . . . . . . 46
4.3 Transient results of a 9-bit TIQ flash ADC (1) . . . . . . . . . . . . . . 47
4.4 Transient results of a 9-bit TIQ flash ADC (2) . . . . . . . . . . . . . . 48
4.5 Chip layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.6 Power consumption in the 6-bit ADCs . . . . . . . . . . . . . . . . . . . 54
4.7 FFT at fin=1 MHz in 6-bit ADC . . . . . . . . . . . . . . . . . . . . . . 55
4.8 Relative currents used by each component . . . . . . . . . . . . . . . . . 60
4.9 DNL and INL of the 8-bit TIQ flash ADC with 0.50 µm . . . . . . . . . 62
4.10 DNLs and INLs of the two 6-bit TIQ comparator . . . . . . . . . . . . . 65
4.11 Two encoders in the TIQ flash ADC . . . . . . . . . . . . . . . . . . . . 68
4.12 Equipments for testing prototype chips . . . . . . . . . . . . . . . . . . . 70
4.13 Die photo of a chip fabricated with 0.25 µm . . . . . . . . . . . . . . . . 71
4.14 Oscilloscope outputs of 0.25 µm ADCs . . . . . . . . . . . . . . . . . . . 75
4.15 DNL and INL of the 6-bit low power based ADC . . . . . . . . . . . . . 76
4.16 Die photo of a chip fabricated with 0.18 µm . . . . . . . . . . . . . . . . 77
4.17 Oscilloscope outputs of 0.18 µm ADCs . . . . . . . . . . . . . . . . . . . 79
4.18 Noise effects on the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.19 FFT spectra of measured and ideal data . . . . . . . . . . . . . . . . . . 82
4.20 Die photo of a chip fabricated with 0.50 µm . . . . . . . . . . . . . . . . 83
xiii
5.1 Active mode or standby mode selector circuit . . . . . . . . . . . . . . . 86
5.2 The power and resolution adaptive ADC . . . . . . . . . . . . . . . . . . 87
5.3 The precision control logic . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.4 VLSI layout of the PRA-ADC . . . . . . . . . . . . . . . . . . . . . . . . 89
5.5 Power reduction comparison . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.6 Resolution switching and switching overhead time . . . . . . . . . . . . 92
5.7 Power management method with TIQ flash ADC . . . . . . . . . . . . . 96
5.8 6-bit ADC simulation result with power management method . . . . . . 98
5.9 Power dissipation vs. frequency . . . . . . . . . . . . . . . . . . . . . . . 100
6.1 SPICE simulation result with 0.07 µm ADC . . . . . . . . . . . . . . . . 104
6.2 Linearity errors of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Schematic of the current mirror and the differential pair [34] . . . . . . . 109
6.4 ADC architecture using the QV comparator . . . . . . . . . . . . . . . . 111
6.5 Schematic of the QV comparator and its voltage transfer characteristic . 113
6.6 The 8-bit QVC flash ADC layout used two cascading QV comparators . 115
6.7 The SPICE simulation result of the 8-bit QVC flash ADC . . . . . . . . 117
6.8 Summary chart of comparing the QVC flash ADC with the TIQ flash ADC 121
xiv
Acknowledgments
First of all, I would like to express my sincere thankfulness to my thesis advisor,
Dr. Kyusun Choi, for his guidance, patience, encouragement, and support during my
stay at Penn State. I would also like to thank the committee members, Dr. Mary Jane
Irwin, Dr. Vijaykrishnan Narayanan, and Dr. Charles L. Croskey, for their time in
reviewing my thesis.
Next, I am thankful to the Korean Army and the Korea Military Academy for
their financial support and for giving me the chance to study abroad. Especially, I
am grateful to Dr. Jang Koon Shin, the former Head of the Department of Computer
Science at the Korea Military Academy, for his guidance when I prepared my PhD study.
Thanks also go to Professor Eun Jae Choi, Dr. Min Young Ra, and Dr. Myoung Ho Oh
for their valuable comments and encouragement.
I specially appreciate Daegyu Lee, Jahan Ghaznavi and Dr. Jongsoo Kim, pro-
fessor of the Department of Electrical Engineering at the University of Ulsan, for their
help in chip design and fabrication and also Steven M. Brown for his proofreading of
my thesis. My special thanks go to the other students in Microsystems Design Lab
(MDL) and in Mixed Signal Chip Design Group for their friendship and all of their help.
Also, I wish to thank the Device Group at UC Berkeley which provided the 0.07 µm the
Berkeley Predictive Technology Model (BPTM) SPICE model.
I am also grateful to the Department of Computer Science and Engineering at
Penn State for supporting me as a teaching assistant. I truly thank Vicki Keller for her
xv
help and support. Also, I would like to thank all Korean students in the Department
of Computer Science and Engineering at Penn State for their friendship and for sharing
their time playing tennis and racket ball.
During my stay at Penn State, I made my religious faith strengthen from the
Bible study with members of Korean Catholic Community. My special thanks go to Fr.
Youngchun Kim for leading that Bible study and for teaching me how to pray. I am
indebted to the Almighty God during my study. Thanks God!
Finally, my greatest thanks go to my family. I would like to thank my parents and
my sister in Korea for their patience, support, and love during this long graduate study.
As for my children, Hosoo Yoo and Jiwoo Yoo, I am very thankful to them for always
believing in me. I would like to express my deepest gratitude to my wife, Seonghye Yoon
who has generously and consistently provided me the endless support and love.
This work was supported in part by Pittsburgh Digital Greenhouse (EDTD00-2)
through a grant from the Commonwealth of Pennsylvania, Department of Community
and Economic Development.
1
Chapter 1
Introduction
The minimum channel length of the transistor will be scaled down to 0.065 µm
in 2007 according to the roadmap of semiconductors [44]. In addition to this down-
scaling, today’s system-on-chip (SoC) trend forces analog and mixed-signal integrated
circuits (ICs) to be integrated with complex digital processors and memory on a single
chip - called complete SoC or digital and mixed-signal (D/MS) SoC. At present, there
are many demands on the complete SoC in wireless and broadband communications -
wireless networking (WLAN, voice/data communication, and Bluetooth), wired com-
munication (WAN and LAN), and consumer electronics (DVD, MP3, digital cameras,
video games, and so on). Therefore, as one of the mixed-signal ICs, analog-to-digital
converters (ADCs) have to follow this complete SoC trend. This chapter introduces the
challenges in designing ADCs and possible solid-state technologies for the complete SoC
trend.
1.1 Challenges in Designing ADCs for SoC
There are many challenges for ADCs to be adaptable for SoC implementation
with current mixed-signal technology. The major considerations in designing ADCs for
the complete SoC are high speed, low power, and low voltage.
2
In terms of high speed, presently 0.13 µm CMOS technology allows processor
speeds in excess of 2.4 GHz. However, the sampling speed of ADCs fabricated with an
advanced BiCMOS process was around 200 mega samples per second (MSPS). Recently,
one of the major ADC foundries has produced high speed ADCs with a bipolar pro-
cess operating up to 1.5 giga samples per second (GSPS) [33] for digital oscilloscopes,
digital RF/IF signal processing, direct RF down-conversion, and radar/ECM systems.
This ADC produced by Maxim Integrated Products has enough speed for SoC imple-
mentation, but the price is too expensive because it uses bipolar solid-state technology.
Both cost and high speed operation are limitations of the complete SoC. Accordingly, to
remove the speed gap between a processor and an ADC in the complete SoC implemen-
tation, an ADC architecture must not only be fast but also cheap.
The next challenge is low power consumption. In the portable device market,
reducing the power consumption is one of the main issues. ADCs should be integrated
with digital circuits on a single chip for the portable devices. All battery powered
devices are now being designed to include low power techniques to prolong the battery
life. Similarly, ADCs need a low power architecture or a low power technique.
Low voltage operation is one of the difficult challenges in the mixed-signal ICs.
The down-scaling of the minimum channel length to 0.065 µm results in the reduction
of the power supply voltage to 0.7 V . However, the minimum supply voltage for the
analog circuits predicted in SIA Roadmap [44] does not follow the digital supply voltage
reduction. A mixed-signal circuit designer faces a great challenge when designing an
ADC that operates at low voltage because of the relatively high threshold voltage of the
transistors. As a result, an ADC should be operated in a small voltage range.
3
The main motivation of this thesis is to design an ADC that will allow on-chip
direct digitization of a wideband RF signal. One of the major challenges in developing
the complete SoC product for the wireless digital network market is the integration of
radio frequency (RF) analog circuit devices, which are mostly passive discrete devices.
Eventually, we want to replace the passive devices with active devices. We also want
to replace analog designs with full-digital implementations. To do this, a suitable ADC
architecture, concentrating on high speed, for the complete SoC should be devised.
1.2 Solid-State Technology
The type of solid-state technology used to implement the converter also affects the
speed of an ADC. Three different types of solid-state technologies are currently used for
high speed ADC implementations: CMOS technology, bipolar technology, and Gallium
Arsenide (GaAs) technology. GaAs technology [6, 45, 46, 55] is the fastest of the three,
and CMOS technology is the slowest. The fastest ADCs are implemented with flash
type architecture using the GaAs technology. The current GaAs technology is not com-
patible with the silicon based CMOS technology, however, which makes it very difficult
to realize the single-chip system solution targeted at by the current SoC trend. Bipolar
technology [33] allows faster operation and is compatible with the CMOS technology.
However, BiCMOS technology requires more processing steps and higher cost compared
to standard CMOS technology. Therefore, mixed-signal circuit implementation using
only the standard CMOS technology is the preferred choice for SoC products.
Hence, we propose a high speed CMOS flash architecture [8, 52, 57, 70] with
low power consumption, which is featuring the Threshold Inverter Quantization (TIQ)
4
technique. The TIQ technique allows greater ADC speed using the standard CMOS
logic circuitry preferred for SoC implementation. The main advantage of the TIQ based
CMOS flash ADC (TIQ flash ADC) design is a simpler comparator design. The idea
is to use digital inverters as analog voltage comparators. This eliminates the need for
high-gain differential input voltage comparators that are inherently more complex and
slower than the digital inverters. The TIQ flash ADC [67, 69, 64] also eliminates the
need of reference voltages, which require a resistor ladder circuit. This simplicity in the
comparator part provides both high speed and low power consumption at the same time.
Moreover, it allows a complete ADC to be implemented using the standard CMOS logic
technology, making the featured ADC ideal for a complete SoC implementation. On
the other hand, the ADC input range varies due to process parameter changes from one
fabrication to another, and the single ended inverter comparator is more susceptible to
noise. These two criteria must be carefully considered to obtain a successful TIQ flash
ADC implementation. The detailed architecture of the TIQ flash ADC will be described
in Chapter 3.
1.3 Thesis Overview
This thesis is organized as 7 chapters. The first chapter introduces the challenges
in designing ADCs for the complete SoC. Chapter 2 provides the necessary background
on ADCs including ADC specifications and several conventional ADC architectures.
Chapter 3 first investigates the CMOS inverter and then describes the proposed flash
ADC utilizing TIQ comparator. Each component in the TIQ flash ADC will be explained
in detail. Chapter 4 presents simulation results and measurements of the TIQ flash ADC.
5
Chapter 5 provides a new power and resolution adaptive flash ADC (PRA-ADC) and a
power management method for the TIQ flash ADC for low power applications with the
TIQ comparator. Chapter 6 introduces a new comparator, the Quantum Voltage (QV)
comparator, for the next generation deep sub-micron low voltage CMOS flash ADC.
Chapter 7 summarizes the work completed in this thesis and compares the TIQ flash
ADC with other ADCs. Future work for the ADC is also described.
6
Chapter 2
A/D Converter Background
This chapter first overviews commonly used ADC parameters to describe the
performance of ADCs. Next, the most popular ADC architectures at the present time
are introduced and compared to each other for design considerations of ADCs.
2.1 ADC Parameters
The parameters that show the performance of an ADC can be obtained from the
data sheets of the ADC [33, 54]. There are many parameters to understand the perfor-
mance of an ADC, and often these parameters are poorly defined. To comprehend the
meaning of them, we should check the standard for terminology and definitions of ADCs.
Some relevant standards have been published by organizations such as IEEE [17], Texas
Instruments [54], and Maxim Integrated Products [29]. These standards are very useful
for estimating and comparing ADCs. Also, most published materials including books
and papers concerned with ADCs use the parameters from the standards to describe
the ADCs’ performance. Therefore, in this section some of major parameters, which are
classified by two categories, static parameters and dynamic parameters, are defined for
easier understanding of this thesis.
7
2.1.1 Static Parameters
The static parameters describe the errors between the actual points and the
ideal/theoretical points in the staircase transfer function of an ADC when it is con-
verting DC signals. Figure 2.1 shows the staircase transfer function of an ADC. The
actual characteristic does not match with the ideal characteristic in both the reference
voltage and the width of horizontal steps, as shown in Figure 2.1. These differences
are essentially due to offset error, gain error, differential non-linearity error (DNL), and
integral non-linearity error (INL).
Output Code
Actual characteristic
000
001
010
011
100
101
110
111
Ideal characteristic
V1 V2 V3 V4 V5 V6 V7 Analog Reference Voltage
Fig. 2.1. Staircase transfer function of an ADC
8
2.1.1.1 Offset and Gain Error
The offset error, Eoffset, is defined [54] as the difference between the nominal and
actual offset points. The definitions of other materials [17, 29, 15, 9, 26, 36] are a little
bit different, but the meaning of the offset error is always the same. Generally speaking,
it means the difference between the first ideal reference voltage, Vmin in Figure 2.1, and
the first actual reference voltage. This offset error can be mathematically formalized.
Eoffset =(V ′min− Vmin)
VLSB(2.1)
where V ′min
is the first reference voltage of the actual characteristic, and VLSB is a
quantization step.
The gain error, Egain, is defined as the difference between the nominal and actual
gain point after the offset error has been eliminated. That is, it indicates the slope
difference between the lines - the dashed line shown in Figure 2.1 - after the offset error
has been adjusted to zero. The equation of the gain error is as follows:
Egain =
((V ′max
− V ′min
)
(Vmax − Vmin)− 1
)· 100 (2.2)
where V ′max
and Vmax stand for the last reference voltages of the transfer function in
the actual characteristic and the ideal characteristic, respectively. The gain error is
usually presented by the percentage of the full scale range of the analog input voltage,
VFSR = Vmax − Vmin. The definitions of the offset and gain error are summarized in
Figure 2.2, which is modified from the original figure [32].
9
Output Code
Ideal liney = ax
Actual liney = cx + b
boffset error
gain error
y = cxoffset error calibrated
Analog Reference Voltage
Fig. 2.2. Offset and gain errors, after [32]
With the calibration of the offset error, there will be no missing output codes, but
the transfer function will be shifted. However, the gain error calibration either reduces
the dynamic voltage range in a positive gain error - the slope of the actual line is higher
than the one of the ideal line - or loses some output codes in the case of a negative gain
error. The calibration of the offset and gain error can be done by a microcontroller or a
digital signal processor (DSP).
2.1.1.2 Differential Non-Linearity Error (DNL)
The differential non-linearity error (DNL) - sometimes this is simply called differ-
ential linearity (DLE) - describes how far the actual step size is from the ideal step in
the least significant bit (LSB) unit, after elimination of the gain error. To measure the
10
DNL, the following equation [30] is used.
DNL(k) =V ′k+1− V ′
k
VLSB− 1 LSB (2.3)
where VLSB = VFSR/2n − 2 for an n-bit flash ADC. Therefore, the ideal value of step
width is 1 LSB since its DNL is 0, according to Equation 2.3. Figure 2.3 shows the
DNL in an example ADC. We can see two different DNLs in Figure 2.3. DNL(2) shows
Output Code
000
001
010
011
100
101
110
111
V1 V2 V3 V4 V5 V6 V7 Analog Reference Voltage
Actual characteristic
DNL(3) = + 1.5 LSB
DNL(2) = - 0.5 LSB
Ideal characteristic
Fig. 2.3. Differential non-linearity error (DNL)
-0.5 LSB, which means the step width is half of the ideal LSB, but in this case we can
still get no missing code. On the other hand, DNL(3) illustrates that there is no output
code “100” because of its step width. Hence, there will be the possibility for an ADC to
become non-monotonic if the DNL is greater than ± 1 LSB.
11
2.1.1.3 Integral Non-Linearity Error (INL)
In the DNL calculation, the DNL only deals with two adjacent actual reference
voltages, no matter how far away from the ideal reference voltages. However, the integral
non-linearity error (INL) - sometimes this is simply called integral linearity (ILE) - checks
the difference between the actual reference voltages and the ideal reference voltages at
all transition points. Therefore, the INL shown in Figure 2.4 describes the overall shape
of an ADC transfer characteristic from the straight line drawn between end points after
Output Code
000
001
010
011
100
101
110
111
V1 V2 V3 V4 V5 V6 V7 Analog Reference Voltage
Actual characteristic
Ideal characteristic
INL(3) = - 1.0 LSB
INL(2) = - 0.5 LSB
Fig. 2.4. Integral non-linearity error (INL)
both the offset error and the gain error are nullified. Equation 2.4 formally defines the
12
INL [30].
INL(k) =V ′k− VminVLSB
− k LSB (2.4)
A program for calculating DNL and INL with Equation 2.3 and Equation 2.4 and for
drawing their plots with MATLAB are shown in Appendix A.
2.1.2 Dynamic Parameters
The static parameters are determined by DC Tests, but the dynamic parameters
are concerned with AC specifications such as resolution, sampling frequency, input signal
frequency, and so on. The main parameters to review are the signal-to-noise ratio (SNR),
the signal-to-noise and distortion ratio (SINAD), the effective number of bits (ENOB),
the total harmonic distortion (THD), and the spurious-free dynamic range (SFDR).
These dynamic parameters are usually extracted from the Fast Fourier Transform (FFT)
test - transforming time domain signals into the frequency domain to get the detailed
signal analysis.
2.1.2.1 Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio of signal power to noise power. With
the SNR, we can easily know how much noise is in an ADC. Generally, the SNR is
expressed in decibel (dB) as in the following equation [2]:
SNR = 20 · log10
(ARMS, signal
ARMS, noise
)= 6.02n + 1.76 dB (2.5)
13
where ARMS,signal and ARMS,noise are the root mean square (RMS) amplitude for
the signal and the noise, respectively. The signal means the fundamental amplitude
signal, and the noise does not include the significant harmonics, which are usually from
the second to the fifth highest amplitudes. The detailed derivation of Equation 2.5
is described in [9]. This equation shows the theoretical limits of the SNR for n-bit
resolution, for example, 50 dB is the maximum SNR for an ideal 8-bit ADC.
2.1.2.2 Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD, SNDR, or TDE for total dynamic
error [36]) is the ratio of signal power to noise power including the significant harmonics.
Since the SNR does not include the significant harmonics, the SNR is usually larger than
the SINAD. Mathematically, the SINAD is formalized as follows:
SINAD = 20 · log10
(ARMS, signal
ARMS, noise+harmonics
)dB (2.6)
2.1.2.3 Total Harmonic Distortion (THD)
The total harmonic distortion (THD) is the ratio of noise power - only the sig-
nificant harmonics - to the signal power. This parameter is caused by the INL, since a
sinusoid input signal will be distorted after passing through a non-linear transfer func-
tion. For this reason, harmonic tones will be created [36]. The THD can be expressed
as
THD = 20 · log10
(ARMS, harmonics
ARMS, signal
)dB (2.7)
14
2.1.2.4 Effective Number of Bits (ENOB)
The effective number of bits (ENOB) shows an ADC’s performance at a specific
input frequency. The ENOB is really related to the input frequency. If the input fre-
quency is increased, then the ENOB is degraded because all of the noises are increased
including the THD. The ENOB can be generally calculated with SINAD as shown in
Equation 2.8 [29].
ENOB =SINAD − 1.76
6.02(2.8)
2.1.2.5 Spurious-Free Dynamic Range (SFDR)
The parameter that shows the dynamic range of an ADC is the spurious-free dy-
namic range (SFDR). The SFDR is the ratio of the signal power to the largest harmonic,
the second significant harmonic. It can be expressed as
SFDR = 20 · log10
(ARMS, signal
ARMS, 2nd harmonic
)dB (2.9)
We can compute the SFDR as the difference between the amplitude of fundamental
and the amplitude of second significant harmonic in the FFT plot. This SFDR is the
important factor in distinguishing the input signal from undesirable spurs.
2.2 ADC Architectures
At present, there exists a variety of ADCs with different architectures, resolu-
tions, sampling rates, power consumptions, and temperature ranges. These ADCs are
15
used in different applications - from mobile communication devices to measure equip-
ment - according to the characteristics of ADCs. Since the performance - sampling rate,
resolution, and power consumption - of an ADC is basically determined by its architec-
ture, one single ADC type cannot cover all applications. For instance, flash (parallel)
ADCs can be used in high speed and low resolution applications. Because of its parallel
architecture, all conversions are done in one cycle with many comparators. On the other
hand, a successive approximation ADC can be used in low-speed and high-resolution
applications since the conversions are done in many cycles with only one comparator.
Therefore, it is important to properly choose an ADC for each particular application.
Among the variety of ADC architectures, there are four most popular ADC ar-
chitectures presently used. These are as follows:
• Flash: The flash ADC operates at very high speed with lower resolution. It is also
called a parallel ADC due to its parallel operation.
• Pipelined: The pipelined ADC can operate at a high speed, but it is slower than
the flash. It covers a wide range of applications because of its flexible resolution
and speed.
• Successive approximation register (SAR): The SAR ADC is suitable for low power
and medium-to-high resolution applications with medium speed.
• Sigma-delta (Σ∆): The Σ∆ ADCs are used for high resolution and low speed
applications.
16
Figure 2.5 shows the trade off between resolutions and sampling rates of the above
popular ADC architectures. The application ranges for each architecture are also shown.
In the following sections, the four popular ADC architectures are briefly addressed.
1M100 10M 100M1K 10K 100K 1G Sampling rate (Hz)
22
18
14
10
6
2
Resoultion (bits)
Sigma-Delta
Data / signal acquisitionPen digitizers & industrial controlsPortable / battery-powered devices
Pipelined
Flash
SAR
Direct RF Downconversion & RF / IF processingHigh speed data acquisitionDigital Oscilloscopes & Radar / ECM systemsWideband Satellite receivers
Video, HDTVMedical & CCD imagingxDSL, Cable modem, fast Ethernet
Portable instrumentationIndustrial process control
Smart transmittersRemote data acquisitionWeigh scales
Fig. 2.5. Tradeoff between resolutions and sampling rates
2.2.1 Flash ADC
The flash ADC is known for its fastest speed compared to other ADC architec-
tures. Therefore, it is used for high-speed and very large bandwidth applications such
as radar processing, digital oscilloscopes, high-density disk drives, and so on. The flash
ADC is also known as the parallel ADC because of its parallel architecture.
Figure 2.6 illustrates a typical flash ADC block diagram. As shown in Figure 2.6,
this architecture needs 2n − 1 comparators for an n-bit ADC; for example, a set of 63
17
1V
Encoder
1
1
1
0Analoginput
Binary output
2 nV
2 nV
2 nV
-1
-2
-3
Fig. 2.6. Block diagram of a flash ADC
comparators are used for 6-bit flash ADC. Each comparator has a reference voltage that is
provided by an external reference source. These reference voltages are equally spaced by
VLSB from the largest reference voltage (V2n−1 in Figure 2.6) to the smallest reference
voltage V1. An analog input is connected to all comparators so that each comparator
output is produced in one cycle. The digital output of the set of comparators - called
the thermometer code - is changed into a binary code through the encoder.
The flash ADC architecture has high speed conversion due to its parallel struc-
ture. However, the flash ADC needs a large number of comparators as the resolution
increases. For instance, a 6-bit flash ADC needs 63 comparators, but 1023 comparators
are needed for a 10-bit flash ADC. This exponentially increasing number of compara-
tors requires a large die size and a large amount of power consumption. To compensate
for the disadvantages of the flash architecture, a half-flash architecture (or sub-ranging
18
architecture) can be implemented with two half resolution flash ADCs and a digital-to-
analog converter (DAC). Figure 2.7 shows the block diagram of an 8-bit sub-ranging
ADC. The first most significant bits (MSBs) are obtained through the coarse 4-bit flash
Flash ADC
S/HAnaloginput Σ
Fist half MSBs (4 bits) Rest half LSBs (4 bits)
Coarse 4-bit
ADCFlash4-bitFineDAC
Fig. 2.7. Block diagram of an 8-bit sub-ranging ADC
ADC. Then a residue is created and converted to an analog signal in the DAC. After
subtracting the analog residual from the input signal, the last 4 LSBs can be obtained
through the fine 4-bit flash ADC. Finally, we have obtained a full 8-bit binary output
with two steps of conversion. Therefore, we can convert an analog signal with a total
of 30 comparators instead of 255 comparators. There are advantages in architecture
complexity and power consumption, but the speed is less than for the typical flash ADC.
Also, both a sample-and-hold (S/H) circuit and DAC are necessary, while the S/H is not
mandatory in the typical flash ADC.
19
2.2.2 Pipelined ADC
The pipelined ADC architecture is a type of sub-ranging ADC introduced in
the previous section. This architecture is implemented with at least two or more low-
resolution flash ADCs as shown in Figure 2.8. Each stage has a S/H circuit to hold the
amplified residue from the previous stage. Then, the input is fed to the low resolution
flash ADC to generate a segmented binary output. Like the sub-ranging ADC, the
segmented output is changed to an analog signal and is subtracted from the input. This
residue is amplified in an amplifier to send to the next stage. The segmented binary
outputs from each stage are time-aligned with a shift register. The final binary output
is obtained after passing through digital error correction logic. This conversion process
in the pipelined ADC is shown in Figure 2.8.
-bitn
-bitn
-bitk -bitk -bitk
-bitk-bitk
-bitk
S/H Σ
S/H Stage 1 m
DACFlashADC
inputAmplified
Analoginput
Digital error correction logic
Shift register
Stage 2 Stage
Fig. 2.8. Block diagram of a pipelined ADC
20
As shown in Figure 2.8, the internal flash ADCs have low resolution that depends
on the application. Hence, the pipelined ADC can be applied from high speed appli-
cations with low resolution to low speed applications with high resolution. Also it can
be modified for low power applications. This is why the pipelined ADC is very popular
today.
2.2.3 Successive Approximation ADC
The successive approximation register (SAR) - commonly called successive ap-
proximation converter - is widely used in industrial control applications and battery-
powered applications because of its good balance between speed and power consumption.
Figure 2.9 illustrates the architecture of the SAR ADC that consists of one comparator,
a DAC, and a successive approximation register. The conversion algorithm is similar to
-bit)n -bitn
-bitn
S/HAnaloginput Approximation
Successive
Register (
DAC
refV
Vin
Fig. 2.9. Block diagram of a successive approximation (SAR) ADC
the binary search algorithm. First, the reference voltage, Vref , provided by DAC is set
21
to theVFSR
2 to obtain the MSB. After getting the MSB, the SAR moves to the next
bit withVFSR
4 or 34VFSR depending on the result of the MSB. If the MSB is “1”, then
Vref = 34VFSR, otherwise Vref =
VFSR4 . This sequence will continue until the LSB
is obtained. Figure 2.10 shows how the reference voltages are implemented in a 3-bit
Vin V4
V7 V6 V5 V4 V3 V2 V1
V6
V7
V5
V3
V1
V2
111
110
101
100
011
010
001
000
binary output
Fig. 2.10. Reference voltage tree in a 3-bit SAR ADC
SAR ADC. Note that V7 is the largest reference voltage, and V1 is the smallest reference
voltage. To get a binary output, 3 comparisons are needed, while 7 comparisons are
needed in the flash architecture. For a 10-bit resolution, the SAR only needs 10 compar-
isons with a single comparator, but the flash ADC needs 1023 comparisons with 1023
comparators. There are large savings in power consumption, but the SAR ADC needs
n cycles for n-bit resolution, while the flash ADC and the pipeline ADC need 1 cycle
22
and m (number of stages) cycles, respectively. Therefore, this SAR architecture is very
attractive for low power applications with a medium sampling rate.
2.2.4 Σ∆ ADC
The Σ∆ ADC is also called an oversampling ADC. It consists of two main blocks.
One is the Σ∆ modulator that includes an integrator, a comparator, and a single-bit
DAC. The other is a digital filter that changes the Σ∆ output to binary code with
filtering. Its block diagram is shown in Figure 2.11. The output of the 1-bit DAC
-bitn
Analoginput
DigitalfilterΣ f
Integrator
Σ∆ Modulator
DAC1-bit
Fig. 2.11. Block diagram of a Σ∆ ADC
is subtracted from the input signal, integrated, and then converted to a 1-bit binary
output. This single bit again goes to the DAC to be processed. This closed-loop process
is performed at a very high oversampled rate [4]. The Σ∆ ADC is very popular for low
bandwidth with high resolution applications because of the capability of noise shaping
23
[4]. But, the latency is much greater than for the other ADC architectures, and this
restricts the application of the Σ∆ ADC.
2.2.5 Summary of ADC Architectures
The most popular ADC architectures have been reviewed in the previous sections.
The flash ADC architecture is the fastest, the SAR ADC architecture has been developed
for low power applications, the Σ∆ ADC is very useful for high resolution applications,
and the pipelined ADC can be applied for various applications depending on how the sub
flash ADCs are organized. Each ADC architecture has tradeoffs among speed, resolution,
and power consumption. In summary, Table 2.1 provides the characteristics of four
popular ADC architectures [4, 31]. In the third column, “sps” stands for samples per
second. The m shown in the forth column is the number of stages in the pipeline
architecture, and n indicates the resolution of the ADC.
24
Table 2.1.Summary of ADC architectures
Architecture Resolution Speed Latency Comments
(bits) (sps) (cycle)
Flash < 10 250M - 1G 1 - extremely fast
- high input bandwidth
- highest power consumption
- expensive
- large die size
Pipelined 8 - 16 1M - 100M m - high throughput rate
- low power consumption
- on-chip self calibration
- require 50 % duty cycles
- needs minimum clock frequency
SAR 10 - 18 76K - 5M n - high resolution & accuracy
- low power consumption
- few external components
- limited sampling rates
- low input bandwidth
Σ∆ > 14 > 200K large - high resolution
- high input bandwidth
- digital on-chip filtering
- external S/H
- limited sampling rates
25
Chapter 3
TIQ Flash ADC
This chapter provides detailed information about the proposed TIQ flash ADC
including its major components. Also important characteristics of the CMOS inverter
are introduced for simulation and analysis of the TIQ flash ADC, which will be described
in Chapter 4.
The proposed flash ADC features the threshold inverter quantization (TIQ) tech-
nique for high speed and low power using standard CMOS technology that is compatible
with microprocessor fabrication. Figure 3.1 shows the block diagram of the TIQ flash
ADC. The use of two cascading inverters as a voltage comparator is the reason for the
technique’s name. The voltage comparators compare the input voltage with internal
reference voltages, which are determined by the transistor sizes of the inverters. Hence,
we do not need the resistor ladder circuit used in a conventional flash ADC shown in Fig-
ure 2.6. The gain boosters make sharper thresholds for comparator outputs and provide
full a digital output voltage swing. The comparator outputs - the thermometer code -
are converted to a binary code in two steps through the ‘01’ generator and the encoder
as shown in Figure 3.1.
26
Vin Comparator
Vmmin
Vmmax
Binary1-out-of-nThermometerCodeCodeCode
Analog InputVoltage
LSB
MSB
Encoder‘01’Generator
GainTIQBooster
Fig. 3.1. Block diagram of the TIQ flash ADC
27
3.1 TIQ Comparator
The comparator is the most important component in the ADC architecture. Its
role is to convert an input voltage (Vin) into a logic ‘1’ or ‘0’ by comparing a reference
voltage (Vref ) with the Vin. If Vin is greater than Vref , the output of the comparator
is ‘1’, otherwise ‘0’.
Commonly used comparator structures in CMOS ADC design are the fully differ-
ential latch comparator [3] and dynamic comparator [70, 56]. The former is sometimes
called a “clocked comparator,” and the latter is called a “auto-zero comparator” or “chop-
per comparator.” To achieve high speed, such comparators are usually implemented with
bipolar transistor technology. For SoC implementation in this case, BiCMOS technology
would be necessary to integrate both a high speed ADC and a digital signal process on
the same substrate.
The TIQ comparator uses two cascading CMOS inverters as a comparator for
high speed and low power consumption. Tangel [53] used this TIQ comparator for
implementing a high speed flash ADC. The proposed TIQ comparator that is described
in this thesis has been developed not only for higher speed but also for higher resolution.
3.1.1 CMOS Inverter as a Comparator
The inverter threshold (Vm) is defined as the Vin = Vout in the VTC of an
inverter [41, 43]. Mathematically,
Vm =r(VDD −
∣∣∣VTp∣∣∣)+ VTn
1 + rwith r =
√kp
kn(3.1)
28
where VTp and VTn represent the threshold voltages of the PMOS and NMOS devices,
respectively. Figure 3.2 shows the schematic of an inverter and its VTC from the sim-
ulation. At the first inverter, the analog input signal quantization level is set by Vm
Wn / Ln Wn / Ln
Wp / Lp
Volta
ges
(lin)
0
200m
400m
600m
800m
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Voltage X (lin) (VOLTS)600m 800m 1 1.2 1.4 1.6 1.8
* hspice file created from inv.ext - technology: mmi25
(a) Inverter schematic diagram
VoutVin Vout1
Wp / LpVout1
Vout
Vb
Va Vin
Vin = Vout
(b) Inverter VTC
Fig. 3.2. Inverter schematic and VTC
depending on the W/L ratios of PMOS and NMOS. The second inverter is used to in-
crease voltage gain and to prevent an unbalanced propagation delay. In Figure 3.2, the
slope of Vout is shown larger than the one of Vout1. The inverter threshold depends on
the transistor sizes. The inverter VTC Va and Vb show the difference from the VTC of
Vout. With a fixed length of the PMOS and NMOS devices, we can get desired values of
Va and Vb by increasing only the width of the PMOS and NMOS transistors, respectively.
29
This result can be confirmed by the following equation of the inverter threshold [43].
Vm =
√µpWpµnWn
(VDD −
∣∣∣VTp∣∣∣)+ VTn
1 +
√µpWpµnWn
(3.2)
where µp and µn are the electron and hole mobility, respectively. To derive Equation 3.2,
we assume that both transistors are in the active region, the gate oxide thickness (Cox)for
both transistors is the same, and the lengths of both transistors (Lp and Ln) are also the
same. From Equation 3.2, we know that Vm is shifted depending the transistor width
ratio (Wp/Wn). That is, increasing Wp makes Vm larger, and increasing Wn results in
Vm being smaller on the VTC.
This changing of the widths of the PMOS and NMOS devices with a fixed transis-
tor length is the idea of the TIQ comparator. We can use the inverter threshold voltage
as an internal reference voltage to compare the input voltage. However, to use the CMOS
inverter as a voltage comparator, we should check the sensitivity of Vm to other param-
eters, which are ignored in Equation 3.2, for correct operation of the TIQ flash ADC. In
a mixed-signal design, the ignored parameters - threshold voltages of both transistors,
electron and hole mobility, and power supply voltage - are not fixed at a constant value.
The following sections will discuss the sensitivity to process, temperature, and power
supply voltage.
3.1.1.1 Sensitivity to Process
For implementing the TIQ comparator, the BSIM3 (HSPICE Level 49) MOS
transistor model that includes about 93 parameters to define a transistor behavior is
30
used. However in reality, there are many parameters. We cannot be sure that the
simulation results with the BSIM3 MOS transistor model will be exactly matched with
the measurement results. Therefore, we need a more complete transistor model for the
inverter threshold sensitivity to reduce the gap between the simulation results and the
measurement results.
Moreover, if we apply another transistor model that was not used in our ADC de-
sign, the inverter threshold sensitivity will be critical in the TIQ comparator. Since
process parameters change from one fabrication to another fabrication, the inverter
threshold voltage will change. This situation is especially one of major problems for
linearity errors of the TIQ comparator that uses Vm as a reference voltage.
3.1.1.2 Sensitivity to Temperature
The inverter threshold voltage also depends on temperature according to the
following partial differential equation [1].
∂Vm∂T
=1
1 +
√µpWpµnWn
dVTndT−
√µpWpµnWn
d∣∣∣VTp∣∣∣
dT
(3.3)
If the temperature is changed, then the effective mobility, channel length, and threshold
voltage of the PMOS (VTp) and NMOS (VTn) devices will be affected. Therefore, the in-
verter threshold will be also changed. The inverter threshold variation with Equation 3.3
has been simulated in [49]. The simulation results show that large ratio of Wp/Wn is
more sensitive to temperature variation. For temperature variation simulation, the range
of temperature - from −40oC to 85oC will be applied in this thesis.
31
3.1.1.3 Sensitivity to Power Supply Voltage
Since the CMOS inverter has a single-ended input, it is more susceptible to power
supply voltage noise than the differential comparator. The partial differential equation
for power supply voltage [53] can be expressed by
∂Vm∂VDD
=1
1 +
√µnWnµpWp
(3.4)
Like Equation 3.2, the lengths of PMOS and NMOS devices are assumed to be equal.
This equation also shows that the larger ratio of the Wp/Wn the more sensitive Vm is to
power supply voltage variation. This fact has been proved by simulation [49]. Generally,
a ±5% power supply range is used in a commercial chip. This rejection ratio will be
used in the power supply voltage variation simulation.
3.1.2 Comparator Generation and Selection Method
The TIQ flash ADC requires 2n − 1 different size comparators and we need to
effectively find their sizes to correctly implement the TIQ comparators. However, choos-
ing the needed Vm from many candidates for comparators and generating the selected
comparators with a custom layout are difficult jobs. For example, a 10-bit flash ADC
would need 1023 TIQ comparators, too many for manual layout designs, while other
ADCs use a single comparator design and simply duplicate it for 2n− 1 times. We have
developed a customized program that automatically generates the TIQ comparators with
an optimal selection approach.
32
A CMOS inverter consists of one PMOS and one NMOS transistor, with the
inverter switching threshold voltage depending upon the transistor sizes. If one fixes
the length of both the PMOS and NMOS transistors at a constant size, one can obtain
different inverter threshold voltages by simply varying the transistors’ widths. Figure 3.3
shows the 3-D plot of Vm as the function of PMOS and NMOS transistor widths.
05
10 0 5 10 15 20
0.6
0.8
1
1.2
1.4
1.6
1.8
2
PMOS (um)
Vm
(V
)
NMOS (um)
Fig. 3.3. The 3-D plot of the inverter switching threshold voltages, Vm, as the functionof PMOS and NMOS transistor widths
To design an n-bit ADC, one needs 2n − 1 equal quantization voltages, and one
must decide on the maximum Vm and the minimum Vm. After deciding the maximum
Vm and minimum Vm, one computes the LSB voltage step (VLSB) by (max. Vm - min.
Vm)/(2n − 2). There are two different design methods [22, 66] for the TIQ comparator
for the Vm values shown in Figure 3.3. One method, called the random size variation
(RSV) technique, can obtain the 2n − 1 reference voltages by selecting the inverter
33
width from the full range of the 3-D surface without considering the relation of adjacent
comparators. This method is named zero DNL design method in [22, 66]. The other
method, called the systematic size variation (SSV) technique, considers the relation of
comparators in selection of the inverter size. This method is named non-zero DNL design
method in [22, 66]. Detailed descriptions are given in the following sections.
3.1.2.1 Random Size Variation (RSV) Technique
The random size variation (RSV) technique simply chooses the Vm from the full-
range of the 3-D plot (around 2 million points). This algorithm selects the actual Vm
that is the closest the ideal Vm, theoretical points that are exactly spaced by VLSB ,
regardless of the transistor size relationship with other comparators. This method needs
much time to find a Vm, because it checks all points of the 3-D plot. As a result, all
of the internal reference voltages of the 2n − 1 comparators are almost equally divided
by VLSB. Hence, the DNL (defined by ((V ′i+1− Vi)/VLSB) − 1) of this approach is
almost zero. A 6-bit TIQ comparator layout produced by the RSV technique is shown
in Figure 3.4(a). The increase or decrease of the transistor size is not systematic.
3.1.2.2 Systematic Size Variation (SSV) Technique
In the case of the systematic size variation (SSV) technique, the Vm is selected
from a reduced-range of the 3-D plot. The diagonal line shown in Figure 3.3 is the ideal
line for this approach. This approach keeps the systematic increasing/decreasing order
of transistor sizes. But, the values along the diagonal line are in too small range to find
proper 2n − 1 reference voltages. Therefore, the range is expanded around the diagonal
34
Vm1
NMOS
PMOS
Vm63
Vm1
NMOS
PMOS
Vm63
(a) A 6-bit TIQ comparator layoutproduced by the RSV technique
(b) A 6-bit TIQ comparator layoutproduced by the SSV technique
Fig. 3.4. Two 6-bit TIQ comparators produced by two design techniques
35
line. We obtain the systematic increasing/decreasing comparator transistor sizes shown
in Figure 3.4(b) by considering the relation of adjacent comparators.
The SSV algorithm determines the best fit Vm values around the diagonal line in
Figure 3.3, keeping an increasing/decreasing order of transistor sizes. The algorithm also
enforces the incremental transistor size step to a certain minimum width (∆W), which
is initially given, for the maximum resolution of the given CMOS technology. The SSV
technique uses the following four steps to generate the 2n − 1 TIQ comparators:
• Step 1: Generating a set of inverter sizes roughly following the diagonal line. The
maximum Vm, minimum Vm, and ∆W are needed for this step.
• Step 2: Finding Vm of each inverter produced in Step 1 through HSPICE simula-
tion. This step takes much more time. When we used 5 Sun-Blade 2000 machines
at the same time, this step took around 4 hours for finding 28000 points.
• Step 3: Selecting a set of 2n − 1 inverters among the inverters generated in Step
1, whose Vm voltages are the nearest to the ideal one, satisfying the following
conditions simultaneously:
– Does each comparator keep the order of increasing/decreasing transistor sizes?
– Does the differences between two adjacent comparators keep at least the ∆W?
• Step 4: Generating a cell design of the TIQ comparators based on the selected
set of inverters in Step 3. With this automatic generation, we can obtain the TIQ
comparator layout in a few seconds A 6-bit TIQ comparator manual design takes
around 4 hours.
36
Figure 3.5 shows an example of how the SSV technique generates a set of transistor
sizes and chooses the best fit (optimal) ones among them. From every possible combi-
W
WNMOS
PMOS
: Selected combination: Arranged combination
Fig. 3.5. An example of the SSV technique
nation of PMOS and NMOS transistor sizes, the program first arranges them along the
diagonal line. Next, the program selects the optimal combinations by looking up the Vm
values of each combination resulted from the HSPICE simulation. The filled black dots
are the selected combination of PMOS and NMOS transistor sizes for the TIQ inverters.
The simulation results of both RSV technique and SSV technique will be represented in
Section 4.1.2.
37
3.2 Gain Booster
Each gain booster consists of two cascading inverters with the same circuit as
the comparator, but the transistor sizes of each gain booster are small and identical.
The gain booster is used to increase voltage gain of the output of a comparator so that
it provides a full digital output voltage swing. Figure 3.6 and Figure 3.7 respectively
show the propagation delay and voltage gain of the gain booster over transistor length
variation.
0 0.5 1 1.5 2 2.5 3 3.50
1
2
3
4
5
6x 10
−9
Transistor length (um)
Pro
paga
tion
dela
y (s
ec)
Fig. 3.6. Gain booster propagation delay result vs. gate length
The propagation delay’s trend is almost exponentially proportional to the transis-
tor length, but the voltage gain follows a logarithm function. Therefore both propagation
38
0 1 2 3 4 50
50
100
150
200
250
Transistor length (um)
Vol
tage
gai
n
Fig. 3.7. Gain booster voltage gain result vs. gate length
delay and voltage gain should be considered together when we choose the size of the gain
booster.
3.3 TC-to-BC Encoder
After the comparators produce a thermometer code (TC), the thermometer code
to binary code (TC-to-BC) encoder generally converts it to a binary code (BC) in two
steps. The TC is converted to the 1-out-of-n code, using XOR logic. This code is then
converted to BC. The two steps for TC-to-BC encoder are shown in Figure 3.8
The most common implementation of the TC-to-BC encoder has been the ROM/PLA
circuits [39, 18], however, the TC-to-BC encoder is often the bottle neck of high sampling
rate flash ADCs. Alternate encoder designs such as a Wallace tree encoder [19] for 1
GHz sampling rate flash ADC implemented with gallium arsenide (GaAs) technology, a
39
CodeGenerator
ROM/PLA00000100
1100
111
01
1
ThermometerCode
CodeBinary
TC-to-BC Encoder1-out-of-n Code
1-out-of-n
Encoder
Fig. 3.8. The two steps for TC-to-BC encoder
XOR encoder [61] for a 8 GHz rate ADC implementation with silicon-germanium (SiGe)
bipolar technology, and a pipeline encoder [27] for a 5 GHz rate ADC implemented with
the Josephson-junction super-conduction technology have been used.
The following sections describe two encoders: a ROM type encoder and a fat tree
encoder. The ROM type encoder is generally used in a flash ADC architecture. To
increase the speed of the flash ADC, we propose a new TC-to-BC encoder, the fat tree
encoder, that is highly suitable for a high speed and low power CMOS flash ADC.
3.3.1 ROM Type Encoder
To convert a 1-out-of-n code to a BC, a ROM can be used. An optimized, with
respect to transistor sizes, NOR ROM circuit was developed to achieve high speed con-
version as shown in Figure 3.9. In the TIQ flash ADC, the ROM speed is the predominant
factor of the overall ADC speed because the signal delay of the ROM is algorithmically
40
TIQComp.
7
TIQComp.
4
TIQComp. 3
TIQComp.
2
TIQComp. 1
Vr7
Vr4
Vr3
Vr2
Vr1
Vin
out2 out1 out0
ROM type encoder
Buffer
Fig. 3.9. ROM type encoder of a 3-bit ADC
41
O(N), where N is the number of ROM inputs. Therefore, we need to improve the speed
of the encoder with an alternative design, non-ROM type such as [19, 61, 27].
3.3.2 Fat Tree Encoder
We propose the fat tree encoder to improve the encoder speed that is the bottle
neck of a flash ADC speed [23, 21]. The main advantage of the fat tree encoder over
the other encoders is its high encoding speed and low power consumption. Figure 3.10
shows an example of the 3-bit fat tree encoder. The 1-out-of-8 code, which is the output
of the ‘01’ generator, is presented at the leaf nodes (from a7 to a0) of the tree. The 3-bit
a5
a4
a3
a2
a1
a0
a6
a7
d2
d0
d1 = (a2 + a3) + (a6 + a7)
d2 = (a4 + a5) + (a6 + a7)
d0 = (a1 + a3) + (a5 + a7)
d1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 a7
a6a5a4a3a2a1a0
d(2:0) 000 001 010 011 100 101 110 111
du
Fig. 3.10. Example of the 3-bit fat tree encoder
binary output (d2, d1, and d0) is located at the root of the tree. The output is obtained
by a logical ORing of the leaf nodes depending on the truth table shown on the right
42
in Figure 3.10. When using only 2-input OR gates, 6 OR gate results go to the parent
nodes, then finally 4 OR gate results (du, d2, d1, d0) are obtained. One of those 4 results,
du, will be used for the next level of the tree. As shown in the tree, the number of edges
increases from leaf to root. So, this new encoder type is named the fat tree encoder.
The fat tree encoder’s signal delay is O(log2N) because of its tree architecture.
Therefore, it is much faster than the ROM type encoder; for example, there are only 2
OR gate delays in case of 3-bit encoding. Also, all multiple OR gates can be changed to
NOR and NAND gates for more efficient implementation. Moreover, the fat tree encoder
can be easily pipelined at each height in the tree. Even though it has an advantage in
terms of speed of the ADC, it is much more difficult to design and automatically generate
than the ROM type encoder. Because the fat tree is 3-dimensional, design automation
of the fat tree encoder is one of the challenges for an improved implementation of the
TIQ flash ADC.
43
Chapter 4
Experimental Results and Evaluations
In this chapter, we present the experimental results and fabrication results of the
TIQ flash ADCs. The TIQ flash ADCs have been designed with three different standard
CMOS technologies - 0.25 µm, 0.18µm, and 0.50µm - with both MAX and Magic CAD
tools. The HSPICE models (BSIM3 level 49) have been used for the experimental simu-
lations. Also, the TIQ flash ADCs have been fabricated three times through the MOSIS
service. This chapter will first show the simulation results then present the fabrication
measurements.
4.1 Simulation Results
With three different CMOS technologies and three different resolutions: 6-bit,
8-bit, and 9-bit, a total of 20 TIQ flash ADCs have been designed, simulated, and
fabricated. Also four more TIQ flash ADCs have been designed and simulated with the
0.07 µm predictive model from the BPTM in the University of California at Berkeley [5].
Therefore, there are too many layouts and simulation results to show all of them in this
thesis. Hence, only the necessary layouts and simulation results will be presented.
The ADC layout is shown in Figure 4.1. This layout shows an 8-bit TIQ flash
ADC with a fat tree encoder. The layouts of the other ADCs are similar to Figure 4.1
except that layout area differs. Some ADCs use a ROM type encoder instead of the fat
44
‘01’ Generator EncoderFat Tree
Gain BoosterTIQ Comparator
Fig. 4.1. Layout of a 8-bit TIQ flash ADC with fat tree encoder
45
tree encoder. In these cases, more regular layouts are shown in the encoder part. The
layout of a TIQ flash ADC with ROM type encoder is discussed in Section 4.1.3.
4.1.1 TIQ Flash ADC Performance
As shown in Figure 3.2, the inverter threshold voltages (Vm) vary with transistor
size. Figure 4.2 shows DC simulation results of a 6-bit TIQ flash ADC and shows the
uniformity of 63 equally spaced inverter threshold voltage. For a transient operation, the
simulation results of a 9-bit TIQ flash ADC with 0.25 µm technology are shown in both
Figure 4.3 and Figure 4.4. Since the LSB of the 9-bit ADC can not be distinguished
in a page, its simulation results is divided into two figures. Figure 4.3 shows the first
half of the simulation results and Figure 4.4 shows the last half of the simulation results.
This 0.25 µm 9-bit ADC was recently designed with a fat tree encoder for a fabrication.
These figures demonstrate a sampling speed up to 1 GSPS without a missing binary
code.
The simulation results - sampling rate, power consumption, and layout - of TIQ
flash ADCs with 3 different technologies are described in following sections.
46
Vol
tage
s (li
n)
0
200m
400m
600m
800m
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Voltage X (lin) (VOLTS)800m 1 1.2 1.4 1.6
max.Vm
min.Vm
Fig. 4.2. DC simulation results of a 6-bit TIQ flash ADC
47
Vin
1
1.5
d8 012
d7 012
d6 012
d5 012
d4 012
d3 012
d2 012
d1 012
d0 012
Time (lin) (TIME)0
50n 100n 150n 200n 250n300n
Fig. 4.3. Transient results of a 9-bit TIQ flash ADC (1)
48
Vin
1
1.5
d8 012
d7 012
d6 012
d5 012
d4 012
d3 012
d2 012
d1 012
d0 012
Time (lin) (TIME)300n 350n 400n 450n 500n 550n
Fig. 4.4. Transient results of a 9-bit TIQ flash ADC (2)
49
4.1.1.1 Simulation Results of 0.25 µm technology
A total of six TIQ flash ADCs with 0.25 µm CMOS technology have been designed
with ROM type encoders for fabrication in the same run as shown in Figure 4.5. The
transistor sizes used in designing the comparator and its inverter threshold voltage are
shown Table 4.1. The “min. comp” and the “max. comp” entries shown in the second
Table 4.1.Comparator transistor sizes used in 0.25 µm design
Length Comparator Wp Wn Vm
(µm) (µm) (µm) (V )
0.24 min. comp 2.0 10.0 0.74774305
max. comp 20.0 1.0 1.64793472
0.50 min.comp 2.0 20.0 0.67623762
max. comp 40.0 1.0 1.62422083
1.00 min.Comp 2.0 40.0 0.60015062
max. comp 80.0 1.0 1.66380054
column mean that the comparator has the smallest inverter threshold voltage and the
largest inverter threshold voltage, respectively. All 6-bit, 8-bit, and 9-bit ADCs have
same sizes of “min. comp” and “max. comp” if they have the same size of length.
Table 4.2 summarizes the simulation results of TIQ flash ADCs with a 2.5 V power
supply voltage. There are two versions of the ADCs for each resolution. The smaller
comparator length is for high speed and the larger length is for low power. As the length
50
Fig. 4.5. Chip layout
Table 4.2.Simulation results of 0.25 µm TIQ flash ADCs
Resolution Comp. Length Area Max. Speed Avg. Power Total Energy
(bits) (µm) (mm2) (MSPS) (mW ) (nJ)
6 0.24 0.051 1000 68.98 4.41
6 1.00 0.102 400 37.57 6.01
8 0.24 0.254 667 254.76 97.83
8 0.50 0.322 500 165.29 84.63
9 0.50 0.635 250 317.40 650.00
9 1.00 0.826 200 260.11 665.88
51
of the comparators increase, the ADC consumes less power, but the speed degrades
even if we increased the maximum width of the low power based ADC’s comparator.
For the 9-bit ADC, the minimum gate length was not used because of too much power
consumption. In terms of ADC speed, low power based ADCs have 60%, 25%, and
20% degradation for the 6-bit, 8-bit, and 9-bit, respectively compared to the high speed
versions. But, the ADCs reduced power consumption by 46% for the 6-bit, 35% for the
8-bit, and 19% for the 9-bit. Since the total energy during the conversion depends on
both speed and power consumption of each ADC, the low power based ADCs does not
always consume small energy compared to the high speed based ADCs. The linearity
errors are 0.26 LSB of DNL and 0.23 LSB of INL for the 9-bit high speed based ADC.
This is the worst case among the six TIQ flash ADCs.
Linearity Errors in 0.25 µm Technology
The most critical issue for the TIQ flash ADC might be process variation. The
process variation simulation results demonstrate changes in the offset, gain, and linearity
of the ADC input voltage range. Table 4.3 shows the process variation effects of an 8-
bit TIQ flash ADC designed with N94S process parameter. The maximum offset and
gain variations from the N94S process are 7.8% and 3.3%, respectively. The full scale
range of reference voltage shows a 9.4% maximum deviation, and the step among the
reference voltages are 11.3% different from the designed process. However, the DNL
is very consistent, within 0.1 LSB, compared with the INL because we used the SSV
technique mentioned in Section 3.1.2.2 for designing the TIQ comparator.
52
Table 4.3.Process variation result in an 8-bit TIQ flash ADC
Process min. Vm max. Vm VFSR VLSB DNL INL
(V ) (V ) (V ) (V ) (LSB) (LSB)
N94S 0.74774 1.64793 0.90019 0.00354 0.0396 0.0295
T02D 0.76576 1.66084 0.89508 0.00352 0.0623 1.6888
T04R 0.70882 1.63864 0.92982 0.00366 0.0747 1.3783
T08P-epi 0.73098 1.60244 0.87146 0.00343 0.1040 2.6049
T08P-ne 0.73114 1.64028 0.90914 0.00358 0.1013 2.4323
T09A-epi 0.75399 1.62559 0.87160 0.00343 0.0728 1.2026
T09A-ne 0.73727 1.59411 0.85684 0.00337 0.1066 2.8842
T0BL-epi 0.76846 1.63072 0.86225 0.00339 0.0570 0.9483
T0BL-ne 0.73436 1.62822 0.89386 0.00352 0.0703 1.4102
T0BM 0.74635 1.63290 0.88656 0.00394 0.0556 1.4195
T11Y-epi 0.73449 1.64926 0.91477 0.00360 0.0529 1.4407
T11Y-ne 0.71114 1.63563 0.92449 0.00364 0.0500 0.5552
TSMC-ff 0.70803 1.69926 0.99124 0.00390 0.0785 2.3330
TSMC-fs 0.69004 1.59432 0.90428 0.00356 0.0393 0.4805
TSMC-ss 0.78762 1.60307 0.81545 0.00321 0.0835 1.9656
TSMC-sf 0.80580 1.70152 0.89573 0.00353 0.0433 0.5012
max. dev. 7.76% 3.27% 9.41% 11.30%
53
Other issues for the TIQ flash ADC linearity errors are temperature and power
supply voltage variations. These variation results in the 8-bit ADC are shown in Ta-
ble 4.4. The comparator was designed with inverter threshold voltages from operating
Table 4.4.Temperature and power supply voltage variation results in the 8-bit TIQ flash ADC
Variations min. Vm max. Vm VFSR VLSB DNL INL
(V ) (V ) (V ) (V ) (LSB) (LSB)
-40o C 0.76707 1.60842 0.84135 0.00331 0.0647 1.8118
27o C 0.74719 1.64923 0.90205 0.00355 0.0396 0.0837
85o C 0.73210 1.68785 0.95575 0.00376 0.0593 1.7988
2.375V (-5%) 0.72906 1.54588 0.81682 0.00322 0.0455 0.5880
2.625V (+5%) 0.76598 1.75084 0.98486 0.00388 0.0461 0.6106
max. dev. 2.59% 6.25% 9.41% 9.61%
at a 25oC temperature and a 2.5 V power supply voltage. Again, the net effects of the
variation are offset, gain, and linearity changes, but the maximum deviation is not as
large as the process variation except the INL. With the SSV technique, we can obtain
reasonable values of DNL, but the INL is still a matter to consider for increasing the
accuracy of the TIQ flash ADCs.
The linearity errors due to process, temperature, and power supply voltage vari-
ations in 0.25 µm CMOS technology are not a large problem for ADC performance
according to the above simulation results. The designed TIQ flash ADCs keep their
54
sampling rate regardless of these variations. But, in 0.18 µm CMOS technology, these
variations degrade the ADC performance. The detailed description of these results will
be presented in Section 4.1.1.2.
Power Consumption in 6-bit ADCs
Figure 4.6 displays the power consumption in the 6-bit TIQ flash ADCs. Both
TP
OW
RD
(lin
)
0
20m
40m
60m
80m
Voltage X (lin) (VOLTS)
600m 800m 1 1.2 1.4 1.6 1.8
6-bit low power ADC
6-bit high speed ADC
Fig. 4.6. Power consumption in the 6-bit ADCs
plots show that a large amount of power is consumed in the middle of the conversion
process. Since most of the comparators are turned on at the middle voltage, VFSR/2,
during conversion, the power consumption lines look parabolic. Also, we can notice that
more power is consumed at the beginning of converting - low input voltage - than at the
55
end of converting. The power consumption in the 8-bit and 9-bit ADC looks similar to
Figure 4.6.
FFT test with 0.25 µm 6-bit ADC
The Fast Fourier Transform (FFT) test is a commonly used measure for the
dynamic parameters of the ADCs. During the FFT test, the signal in the time domain
is converted to a signal in the frequency domain. Figure 4.7 depicts the FFT simulation
results for a 6-bit ADC. The 6-bit ADC FFT test with a 1 MHz sine wave signal exhibits
0 20 40 60 80 100 120 140−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
Frequency(MHz)
Am
plitu
de(d
B)
fsample
SNR = 43.85 dBSINAD = 33.17 dBTHD = -36.17 dBSFDR = 37.93 dB
= 250 MHz, fin = 1 MHz
Fig. 4.7. FFT at fin=1 MHz in 6-bit ADC
harmonics 37.93 dB (SFDR) below the fundamental frequency 1 MHz. The SINAD of
33.17 dB implies the ENOB is equal to 5.2 bits.
56
4.1.1.2 Simulation Results of 0.18 µm technology
For the second fabrication, 0.18 µm CMOS technology and a 1.8 V power supply
voltage were used. A fat tree encoder was also designed for a 6-bit ADC to compare with
ROM type encoder. The simulation results summarized in Table 4.5 show higher speed,
Table 4.5.Simulation results of 0.18 µm TIQ flash ADCs
Resolution Comp. Length Area Speed(1) Speed(2) Power Energy
(bits) (µm) (mm2) (MSPS) (MSPS) (mW ) (nJ)
6 0.18 0.037 2000 1250 101.98 3.26
6 0.50 0.045 1666 1000 39.37 1.51
6 w/ROM 1.00 0.074 1111 667 35.85 2.06
6 w/FAT 1.00 FAT 0.069 1111 714 23.46 1.35
8 0.50 0.165 2000 1000 137.08 17.55
8 1.00 0.272 1666 714 108.47 16.66
9 1.00 0.537 667 476 194.23 149.17
9 1.50 0.595 500 400 110.38 113.03
smaller area, and lower power consumption than the results for 0.25 µm technology.
There are two ADC speeds shown in this table. The fourth column in Table 4.5
shows the maximum speed with the process parameters used in the design. However, the
speed in the fifth column indicates the speed after considering all process, temperature,
and power supply voltage variations. Because of these variations, the speed is degraded
by up to 57 % for the 8-bit low power based ADC. In the 0.18 µm technology, these
variations affect the speed of the TIQ flash ADC.
57
Linearity Errors in 0.18 µm Technology
As shown in Table 4.5, the process, temperature, and power supply voltage vari-
ations are problems for the performance of the 0.18 µm ADCs, while these variations
do not degrade the performance of the 0.25 µm ADCs. Therefore, we need to check the
variation effects in 0.18 µm technology.
The parameter variation results are shown in Table 4.6. The DNLs of the variation
results with 0.18 µm technology are all within 0.3 LSB which shows that the ADCs are
monotonic. However, the maximum deviations from the results of process, TSMC-tt,
which was used for the design, are very large compared to the 0.25 µm technology
variation results. These large values result in a large value of INL. The large INL means
that the ADC has a possibility to be non-monotonic. As a result, the ADCs cannot be
operated at the maximum sampling rates under these variations. From these variation
results, we noticed that the process, temperature, and power supply voltage variations
are a critical factor of the ADC performance as the gate length is made smaller. Again,
we recognize that the SSV technique is very effective for reducing the DNL, but with
small gate lengths the SSV technique cannot overcome the large value of INL. A design
method for improving the INL is necessary for the TIQ flash ADC to correctly operate
using the small length of CMOS technology.
Power Consumption in Each Component of the ADC
The power consumption in a short-gate technology should be less than the one
in a long-gate technology because of the reduction of power supply voltage, which is
quadratically proportional to power consumption. The sixth column in Table 4.5 shows
58
Table 4.6.Variation results in a 0.18 µm 8-bit TIQ flash ADC
Variations min. Vm max. Vm VFSR VLSB DNL INL
(V ) (V ) (V ) (V ) (LSB) (LSB)
TSMC-tt 0.61069 1.01191 0.40122 0.00158 0.0899 0.0758
TSMC-ff 0.53818 1.02046 0.48588 0.00191 0.1850 1.3156
TSMC-fs 0.51266 0.92721 0.41455 0.00163 0.2086 1.1193
TSMC-ss 0.68121 1.00577 0.32456 0.00128 0.1941 2.1702
TSMC-sf 0.70925 1.09709 0.38784 0.00153 0.2774 1.2637
T12K 0.63725 1.03781 0.40056 0.00158 0.2591 4.3487
T14B 0.64719 1.03766 0.39047 0.00154 0.2761 4.9441
T15J 0.64070 1.03931 0.39861 0.00157 0.2585 5.0830
T16X 0.65218 1.04176 0.38958 0.00153 0.2912 6.9232
T18H 0.65618 1.04019 0.38401 0.00151 0.2931 6.7843
T1CH 0.65272 1.05780 0.40508 0.00159 0.2757 6.6918
T22T 0.63870 1.03128 0.39258 0.00155 0.2853 6.7023
T24I 0.64072 1.05136 0.41064 0.00162 0.2706 6.9110
T26X 0.65168 1.04931 0.39763 0.00157 0.2568 7.0116
T28M 0.64914 1.05872 0.40958 0.00161 0.2569 7.3446
-40o C 0.63122 0.97874 0.34752 0.00137 0.3056 4.5929
85o C 0.59515 1.04430 0.44915 0.00177 0.2768 3.2568
1.71V (-5%) 0.59516 0.95409 0.35893 0.00141 0.2666 0.8621
1.89V (+5%) 0.62579 1.07056 0.44477 0.00175 0.1414 0.6882
max. dev. 16.1% 8.4% 21.1% 20.9%
avg. dev. 7.1% 3.8% 6.3% 6.2%
59
the average power consumption of the ADCs. The power consumption for the 0.18 µm
technology does not produce a large savings because the maximum transistor size in the
comparator is at least 2.5 times for the PMOS and 1.5 times for the NMOS devices larger
than the sizes in 0.25 µm technology. The absolute currents and relative currents used by
each component are shown in Table 4.7 and in Figure 4.8, respectively. The simulated
Table 4.7.Absolute currents used by each component
ADCs Comparator Gain booster 01 generator Encoder
(mA) (mA) (mA) (mA)
6b 0.18 75.07 1.37 0.68 10.99
6b 0.50 27.94 1.36 0.68 10.86
6b 1.00r 23.53 1.45 0.68 10.86
6b 1.00f 17.46 1.50 1.05 3.96
8b 0.50 85.00 1.53 0.73 15.22
8b 1.00 72.57 1.49 0.74 14.73
9b 1.00 138.81 1.43 0.74 16.52
maximum currents show the portion of power consumption in each ADC. As expected,
the comparator consumes more than 60 % of the power. Figure 4.8 also illustrates that
the comparator power portion is decreased as the gate length is made longer. Also,
the resolution of the ADC effects the portion of the power consumption. For the same
gate length, the higher resolution ADC consumes more power than the lower resolution
60
Fig. 4.8. Relative currents used by each component
ADC. The encoder section is the next major uses of power. Specifically, the ROM type
encoder (the 3rd one) consumes more power than the fat tree encoder (the 4th one).
The power consumption of the gain booster, which is a minimum size of inverter, and
the ‘01’ generator are very small compared to the power of the comparator. Therefore,
we should focus on the comparator for designing a low power ADC.
4.1.1.3 Simulation Results of 0.50 µm technology
An 8-bit TIQ flash ADC has been designed with 0.50 µm CMOS standard tech-
nology for the third fabrication. For this chip, the fat tree encoder was used to increase
the speed of the TIQ flash ADC. In Section 4.1.1.2 the fat tree encoder was confirmed
to be faster than the ROM type encoder. The fat tree encoder also has an advantage in
power consumption.
61
Unlike the first and second fabrication, no parameter values were supplied by
the chip fabrication vendor. Therefore we needed to choose one parameter that could
be less sensitive to the process variation. To choose the parameter set that was used
in this design, we picked 10 SPICE parameters provided by MOSIS and calculated the
average values of each inverter threshold voltage. After that, we chose the parameter
model T22A because 255 inverter threshold voltages of the T22A were the closest to the
average values.
The simulation results of the 8-bit 0.50 µm TIQ flash ADC are described in
Table 4.8. As can be seen, the ADC size is larger than for the ADCs with 0.25 µm
and 0.18 µm, but the ADC speed is faster than the speed of the 8-bit ADC with 0.25
µm. Next, we optimized the size of both fat tree encoder and gain booster. The power
consumption in this case is very large since the maximum width of PMOS and NMOS
devices in the comparator has been increased at least four times compared to the ADCs
with 0.25 µm. In addition to this increasing the width, the influence on the power
consumption is the power supply voltage increasing from 2.5 V to 5.0 V .
Figure 4.9 displays the DNL and INL of the 8-bit TIQ flash ADC designed with the
T22A SPICE parameter set. Table 4.9 shows the variation of results with other SPICE
models. The results are exactly as expected. In the 0.50 µm CMOS technology, the
inverter threshold voltages are less sensitive to process variations than for the previous
smaller technologies. The simulations with other process models shows small deviations
(within 1% in all parameters) including DNL and INL from the model used for the design.
Especially, the DNL and INL of the other processes are less than 0.5 LSB, except for one
- the T17Z INL. The DNLs are almost the same as the T22A model. There is only 3.2%
62
Table 4.8.Simulation results of the 8-bit 0.50 µm TIQ flash ADC
Resolution 8 bit
CMOS tech. 0.50 µm
comparator length 1.50 µm
power supply 5.0 V
max. speed 500 MSPS
avg. power 2.399 W
total energy 2.457 µJ
VFSR 1.346 V - 2.613 V
VLSB 0.005 V
DNL 0.2647 LSB
INL 0.1726 LSB
ADC area 1.722 mm2
0 50 100 150 200 250−0.5
−0.25
0
0.25
0.5
output code
DN
L (
LS
B)
0 50 100 150 200 250−0.5
−0.25
0
0.25
0.5
output code
INL
(L
SB
)
(a) DNL (b) INL
Fig. 4.9. DNL and INL of the 8-bit TIQ flash ADC with 0.50 µm
63
Table 4.9.Variation results in a 0.50 µm 8-bit TIQ flash ADC
Process min. Vm max. Vm VFSR VLSB DNL INL
(V ) (V ) (V ) (V ) (LSB) (LSB)
T22A 1.34574 2.61347 1.26773 0.00499 0.2647 0.1726
T17G 1.33873 2.61190 1.27317 0.00501 0.2654 0.3186
T17Z 1.34216 2.61802 1.27586 0.00502 0.2687 0.5883
T1AW 1.33868 2.61317 1.27449 0.00502 0.2700 0.1779
T1BD 1.35666 2.63113 1.27447 0.00502 0.2723 0.3649
T1CK 1.35208 2.60971 1.25763 0.00495 0.2713 0.2866
T21S 1.33346 2.59478 1.26132 0.00497 0.2720 0.3867
T22Y 1.34862 2.62063 1.27201 0.00501 0.2689 0.3078
T24H 1.35072 2.60794 1.25722 0.00495 0.2731 0.3328
T24O 1.35827 2.62137 1.26310 0.00497 0.2658 0.2093
max. dev. 0.93% 0.72% 0.83% 0.80%
avg. dev. 0.56% 0.29% 0.55% 0.56%
64
maximum deviation. However, the deviations of the INLs are large, but they are still in
a reasonable range when compared to the 0.25 µm and 0.18 µm results. By choosing
the process that has an average inverter threshold voltage, we can get reasonable DNLs
and INLs in spite of process variations. But, this method is not practical because there
are too many processes to reasonably choose between them.
4.1.2 Variation Effects on the RSV and SSV Techniques
This section deals with the simulation results from the two design methods intro-
duced in Section 3.1.2: the RSV and SSV techniques. Two 6-bit TIQ comparators have
been designed with the 0.25 µm TSMC-TT SPICE parameter set. One comparator was
designed with the RSV technique and the other one with the SSV technique.
Initially, the 6-bit comparator with the SSV technique had a larger value of DNL
and INL. However, choosing inverter transistor sizes from the diagonal line shown in
Figure 3.3 ensures the monotonic size increase and decrease of the PMOS and NMOS
transistors (shown in Figure 3.4(b)), respectively. This makes the DNL and INL of the
ADC to be less sensitive to the CMOS process variations. The 22 HSPICE parameters
provided by MOSIS and five TSMC parameters are used to check the effects of process
variation. The simulation results of the Figure 4.10 and Table 4.10 show that the DNL
and INL of the RSV technique are much more sensitive to process variation than those
of the SSV technique. Considering process variations, the SSV technique can reduce
DNL and INL to 82.6% and 32.5% on average compared to those of RSV technique,
respectively.
65
0 10 20 30 40 50 60−1.5
−1
−0.5
0
0.5
1
1.5
OUTPUT CODE
INL
(L
SB
)
tsmc−tttsmc−ffn94s
0 10 20 30 40 50 60−1
−0.5
0
0.5
1
OUTPUT CODE
DN
L (
LS
B)
tsmc−tttsmc−ffn94s
0 10 20 30 40 50 60−1.5
−1
−0.5
0
0.5
1
1.5
OUTPUT CODE
INL
(L
SB
)
tsmc−tttsmc−ffn94s
0 10 20 30 40 50 60−1
−0.5
0
0.5
1
OUTPUT CODE
DN
L (
LS
B)
tsmc−tttsmc−ffn94s
(a) DNLs of RSV technique (b) DNLs of SSV technique
(d) INLs of SSV technique(c) INLs of RSV technique
Fig. 4.10. DNLs and INLs of the two 6-bit TIQ comparator
66
Table 4.10.The effects of process variations and RSV and SSV design techniques
Process DNL of RSV DNL of SSV INL of RSV INL of SSV
(LSB) (LSB) (LSB) (LSB)
TSMC-TT 0.0023 0.0114 0.0013 0.0083
TSMC-ff 0.1384 0.0414 0.5839 0.5265
TSMC-fS 0.0134 0.0142 0.1140 0.1155
TSMC-Sf 0.0140 0.0158 0.1190 0.1164
TSMC-SS 0.1399 0.0424 0.4954 0.4293
T08P-epi 0.9277 0.1028 1.1109 0.6823
T08P-ne 0.7054 0.0825 1.0058 0.6420
T09A-epi 0.9695 0.0790 0.7746 0.4836
T09A-ne 0.8278 0.0958 1.2349 0.7610
T0BL-epi 1.0548 0.0872 1.0539 0.6096
T0BL-ne 0.8946 0.0885 1.0335 0.6172
T11Y-epi 0.9425 0.0431 0.5388 0.2581
T11Y-ne 1.0289 0.0598 0.8105 0.3986
T13M-epi 1.1652 0.0832 0.6712 0.4954
T13O-epi 0.6815 0.0482 0.4142 0.3088
T14Y-epi 0.9827 0.1055 1.1881 0.7065
T15H-epi 1.1302 0.0694 0.6809 0.4310
T16R-epi 0.8226 0.0687 0.5629 0.4220
T17A-epi 0.9733 0.0732 0.6464 0.4558
T18I-epi 1.0313 0.0840 0.8050 0.5284
T19o-epi 0.9317 0.0864 0.8417 0.5522
T1AB-epi 0.9246 0.0458 0.5458 0.2530
T1CJ-epi 0.9578 0.0553 0.5122 0.3327
T21Q-epi 0.5672 0.0436 0.3692 0.2762
T23C-epi 0.9806 0.0655 0.5564 0.3992
T25T-epi 0.8805 0.0533 0.7442 0.3982
T27H-epi 0.6261 0.0397 0.6181 0.3441
67
Table 4.11 compares the RSV and SSV techniques for temperature and power
supply voltage variations. For the temperature and power supply voltage variation,
43.5% reduction for DNL and 6.0% reduction for INL are achieved. Again, the key
feature in the SSV technique is to maintain the monotonicity of transistor size changes so
that the resulting ADC will have consistent DNL limits in spite of process, temperature,
and power supply voltage variations.
Table 4.11.DNL and INL for temperature and power supply voltage variations using the RSV andSSV design techniques
Variations DNL of RSV DNL of SSV INL of RSV INL of SSV
(LSB) (LSB) (LSB) (LSB)
-40oC 0.0634 LSB 0.0459 LSB 0.4449 LSB 0.4330 LSB
85oC 0.0617 LSB 0.0353 LSB 0.4392 LSB 0.4324 LSB
2.375 V 0.0365 LSB 0.0169 LSB 0.1450 LSB 0.1306 LSB
2.625 V 0.0309 LSB 0.0155 LSB 0.1483 LSB 0.1337 LSB
The TIQ comparator design is based on the internal voltage reference determined
by the transistor sizes. However, the internal voltage reference varies due to the CMOS
process parameter variation during manufacturing. Such variations create limits on the
linearity variation of the ADC. The SSV design technique of the TIQ comparator sig-
nificantly improves the linearity of the ADC in spite of the CMOS process variation. In
particular, the DNL dependence on the CMOS process variation can be almost elimi-
nated.
68
4.1.3 Fat Tree Encoder vs. ROM Type Encoders
The concepts of the fat tree encoder and ROM type encoder were introduced in
Section 3.3. In this section, we compare the two encoders in terms of their sampling rate
and power consumption.
For a more efficient implementation in CMOS, the OR gates shown in Figure 3.10
are replaced with NOR and NAND gates using DeMorgan’s theorems. To compare the
two encoders, 0.18 µm TIQ flash ADCs were designed with the fat tree encoder and the
ROM type encoder, respectively. Two encoders are shown in the Figure 4.11. The only
difference between two ADCs in Figure 4.11 is the encoder. The simulation results with
these two encoders are summarized in Table 4.12.
fat tree encoder
(a) Fat tree encoder layout (b) ROM type encoder layout
ROM type encoder
Fig. 4.11. Two encoders in the TIQ flash ADC
69
Table 4.12.Summary of the simulation results with two encoders
Fat Tree Encoder ROM Type Encoder
sampling rate 2.00 GSPS 1.11 GSPS
avg. power 22.70 mW 32.64 mW
max. power 38.65 mW 54.41 mW
total energy 0.73 nJ 1.88 nJ
encoder transistor number 485 222
encoder area 0.0074 mm2 0.0094 mm2
The speed of the ADC with the fat tree encoder is about 1.8 times faster than
the speed of the ADC with the ROM type encoder. Concerning power consumption
and area, the fat tree encoder can save 30.5% of the power, 61.2% of the energy, and
21.3% of the area. For the TIQ flash ADC, the ROM type encoder does not have a
sense amplifier and minimum size of the NMOS device. Instead, the sizes of NMOS and
PMOS transistors in the ROM have been optimized for high speed operation. Therefore,
the ROM type encoder consumes more power even if it has small number of transistors.
Table 4.12 clearly demonstrates that the fat tree encoder is a better choice over the ROM
type encoder in a SoC implementation.
The disadvantage of the fat tree encoder is the difficulty in its layout. As shown
in Figure 4.11, the fat tree encoder is not as regular as the ROM type encoder. Hence,
it takes much more time to design the fat tree encoder. For an effective design and
implementation of the fat tree encoder, a systematic layout tool should be developed.
70
4.2 Fabrication Results
TIQ flash ADCs have been fabricated three times. The first fabrication was done
with TSMC 0.25 µm CMOS technology and packaged in a 40-pin dual inline package
(DIP). The TSMC 0.18 µm CMOS technology was used in the second fabrication and
it was packaged in a 84-pin pin grid array (PGA). For the third fabrication, 0.50 µm
CMOS technology was used and packaged in a 40-pin DIP. The fabricated prototype chips
have been tested with a 15MHz function generator (HP33120A), 100 MHz 2*16 channel
oscilloscope (HP54645D), and a DC power supply (HP3631A), as shown in Figure 4.12.
15MHz Function Generator DC Power Supply
100MHz Oscilloscope Bread Board 0.25um Chips
Fig. 4.12. Equipments for testing prototype chips
71
4.2.1 Test Results of 0.25 µm TIQ flash ADC Chips
The first fabricated chip contained six TIQ flash ADCs: two for 6-bits, two for
8-bits, and two for 9-bits. As mentioned in Section 4.1.1.1, we tried two different gate
lengths for the comparator transistors in each resolution to compare the speed and the
power consumption. Figure 4.13 shows the fabricated chip die photo (2.58 mm × 2.58
mm). Since the 5 layers of metal covers most of the active area, the details of each ADC
9-bit 0.50um
8-bit 0.24um 8-bit 0.50um
9-bit 1.00um
1.00um6-bit6-bit
0.24um
Fig. 4.13. Die photo of a chip fabricated with 0.25 µm
layout cannot be seen. The layout of the chip shown in Figure 4.5 is displayed after
removal of the topmost metal layer that covers the active area.
72
A total of 25 prototype chips were received. The test results show that only the
6-bit low-power based ADC (comparator length equals to 1.00 µm) operates with full
precision without a missing code. However, the other ADCs work with reduced precision.
Table 4.13 summarizes the test results of the first fabricated ADCs. The second column
Table 4.13.Summary of 0.25 µm chip test results
ADCs ] of TRs Comp. length Precision Avg. Power Signal delay
(µm) (bits) (mW ) (ns)
6-bit 1000 0.24 4 109.38 3.799
1.00 6 35.25 21.404
8-bit 5174 0.24 5 170.50 7.249
0.50 7 121.25 18.612
9-bit 10555 0.50 6 200.38 27.762
1.00 8 179.63 83.595
shows the number of transistors used in each ADC. The precision of the ADCs are shown
in the third column. These precisions are reduced due to the following reasons:
• Process limitation: Although layout dimension can be specified in 0.01 µm steps,
mask production and physical dimension control in 0.01 µm is not possible. Con-
sidering this minimum feature size of 0.24 µm, ∆W in Section 3.1.2.2 was too small
in the first fabrication.
73
• On chip power distribution: The pad frame design does not separate the analog
power lines from the digital power lines. Digital circuits generate noise on the
power supply line causing the sensitive analog comparators to chatter.
• Noise coupling to ADC input: The large capacity output pad drivers causes more
noise on the power supply when the oscilloscope probe is connected. Also, the
switching transitions at the output couple to the ADC input.
The actual measured power for each ADC shows good matching with simulation
results described in Table 4.2. Overall 10% - 20% less power consumption was mea-
sured than produced by the simulation results. This might be mainly due to an under
estimation of the parasitics in simulation parameters.
We cannot actually measure the conversion speed of the ADCs except for the 6-
bit low power based TIQ flash ADC because of the unanticipated noise. However, all of
the ADCs correctly operate with 1 MHz square wave input. Therefore, the performance
of the ADCs can be illustrated by the measured signal delays shown in Table 4.13 with
this square wave input. The “signal delay” means the transition time from “000000” to
“111111” in the case of the 6-bit ADC. The original ADC design and simulation has been
done with TSMC-tt (simply called TSMC) process parameter set. The wafer test result
was produced T14Y-lo-epi parameter set (simply called T14Y) shown in Appendix B.
The signal delays of the ADCs are summarized in Table 4.14. Re-simulation with T14Y
parameter shows the signal delay is 10% - 30% longer than for the designed parameter
TSMC. However, the actual measurements on a prototype chip show at least a 50%
longer signal delay. Several possible reasons are as follows:
74
Table 4.14.ADC Signal delay test results
ADCs Chip ]15 Chip ]15 TSMC TSMC T14Y T14Y
input swing 0.0V -2.5V 0.6V -1.7V 0.0V -2.5V 0.6V -1.7V 0.0V -2.5V 0.6V -1.7V
(ns) (ns) (ns) (ns) (ns) (ns)
6b024 3.924 5.562 1.850 2.011 2.216 2.383
6b100 21.562 37.861 4.506 6.481 5.250 8.186
8b024 7.787 7.487 1.430 1.520 1.914 2.012
8b050 18.662 17.574 1.931 2.244 2.502 2.914
9b050 27.712 31.211 2.330 2.629 3.075 3.483
9b100 82.062 106.862 3.740 4.437 4.544 5.775
• A significant under estimation of the load conditions
• The layout to circuit extraction being not too accurate
• The bandwidth of the signal source and measuring tools being limited
• The bread board configuration and power supply limits
Table 4.14 describes the signal delays with a rail-to-rail swing input voltage (0.0V - 2.5V )
and ADC the full swing range (0.6V - 1.7V ). The signal delays with the ADC full swing
input range are longer than for the rail-to-rail swing.
The maximum observed conversion speed in the 6-bit low-power based TIQ flash
ADC is 250 MSPS, as measured with a recently acquired 250 MHz mixed signal oscil-
loscope, but we anticipate being able to document higher-speed operation with better
measuring equipment. Figure 4.14 shows a 20 KHz sine wave test result for the 6-bit
75
(b) 100 KHz saw wave test with 9-bit ADC
(a) 20 KHz sine wave test with power supply noise in 6-bit ADC
Fig. 4.14. Oscilloscope outputs of 0.25 µm ADCs
76
ADC and a 100 KHz saw-tooth wave form test result for the 9-bit ADC.
The process parameter variation produces less than 3% variation of min. Vm and
is consistent among chips. The INL (1.20 LSB) and DNL (0.27 LSB) are significantly
larger for the test result than the simulation results. The measured INL and DNL for
the 6-bit ADC are shown in Figure 4.15.
0 10 20 30 40 50 60−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
OUTPUT CODE
DN
L (L
SB
)
0 10 20 30 40 50 60−1.5
−1
−0.5
0
0.5
1
1.5
OUTPUT CODE
INL
(LS
B)
(a) Differential non-linearity (b) Integral non-linearity
Fig. 4.15. DNL and INL of the 6-bit low power based ADC
4.2.2 Test Results of 0.18 µm TIQ flash ADC Chips
The second chip fabrication used the same die size as the first fabrication. Since
0.18 µm CMOS technology was used at this time, we could put more TIQ flash ADCs
on the chip than the previous fabricated chip for the TIQ comparator experiment. From
the second fabrication, the parametric test result, T1AX-lo-epi shown in Appendix C,
was produced. Figure 4.16 shows the die photo of a prototype chip fabricated with 0.18
77
µm CMOS technology. Six layers of metal were used for chip design. Like the first
9-bit 1.50um
9-bit 1.00um
4 6-bit ADCs
6-bit1.0um
8-bit 0.50um 8-bit 1.00um
Fig. 4.16. Die photo of a chip fabricated with 0.18 µm
fabrication, the details of the chip layout cannot be seen. But, a part of TIQ comparator
among the higher metal layers can be identified.
All 40 chips work, but the test results are worse than for the chips fabricated
with 0.25 µm technology. As shown in Table 4.15, only two of the 6-bit ADCs with a
gate length of 1.00 µm operate with full precision. The precision of the other ADCs is
even worse than for the previous ones. The second fabrication with 0.18 µm ADCs are
smaller in area, lower in power consumption (at least 40%), and shorter in ADC signal
delays (at least 100%) than the first fabrication. The transient signal outputs and signal
delay of the 6-bit 1.00 µm ADC with a fat tree encoder and the 8-bit 1.00 µm ADC
78Table 4.15.
Summary of 0.18 µm chip test results
ADCs Comp. length Precision Avg. Power Signal delay
(µm) (bits) (mW ) (ns)
6-bit 0.18 3 77.40 3.35
0.50 3 36.01 2.97
1.00 w/ROM 6 21.64 4.50
1.00 w/FAT 6 26.97 2.65
8-bit 0.50 5 75.64 6.65
1.00 6 64.78 15.45
9-bit 1.00 5 111.61 29.20
1.50 5 64.81 35.50
are shown in Figure 4.17. There are no missing codes in the 6-bit 1.00 µm ADC with
fat tree encoder, and its signal delay is 3.85 ns including the pad delay (1.2 ns). On
the other hand, the 8-bit 1.00 µm ADC shows that there are missing codes in first two
MSBs. We could be able to obtain a full precision 8-bit TIQ flash ADC if we eliminate
the noise problem. The signal delay of this ADC is 16.65 ns, which also includes the
pad delay. The measured DNL and INL of the 6-bit fat tree encoder ADC is 0.36 LSB
and 1.36 LSB, respectively.
4.2.2.1 Noise effects on the ADCs
The noise problem is more serious in the 0.18 µm design. Figure 4.18 shows effects
on power supply and input of the ADC. The noise from the probe on the power supply
is one of the major factors that makes the input chatter. Figure 4.18(a) shows a large
(more than 100 mV ) noise on the power supply when the probe is connected to the chip.
However, without the probe connection, we get a small noise (around 10 mV ) on the
79
(a) 6-bit 1.00um with fat tree encoder (b) Signal delay of (a)
(c) 8-bit 1.00um ADC (d) Signal delay of (c)
Pad delay: 1.2 ns
Pad delay: 1.2 ns
Fig. 4.17. Oscilloscope outputs of 0.18 µm ADCs
80
(c) Vdd and GND noise in a 6-bit ADC
(d) Vdd and input noise in a 6-bit ADC
(a) Noise from the probe (b) Noise without the probe
(e) Noise reduction with 47K resistor
Fig. 4.18. Noise effects on the ADC
81
power supply as depicted in Figure 4.18(b). The 6-bit ADC is less sensitive to this noise
effect, while the higher resolution ADC is very susceptible to this noise. Figure 4.18(c)
shows the 6-bit ADC result along with power supply noise. Also this power supply noise
makes the input chatter shown in Figure 4.18(d). The noise on the input follows the
noise on the power supply. This noise can be reduced by adding a resistor at the end
of the outputs. Figure 4.18(e) shows noise reduction on both the input and the power
supply after a 47K resistor was added to the chip. Due to these noises, the precision
of the ADCs is reduced, especially in higher resolution ADCs. Also, the added resistor
degrades the ADCs’ performance.
4.2.2.2 Fast Fourier Transform (FFT) Test Results
The dynamic performance of the TIQ flash ADC is measured with a FFT test.
The measured data FFT result shown in Figure 4.19(a) does not match the FFT test
result for the simulated operation (Figure 4.7). The 6-bit data (512 points) was measured
for a 80 KHz input frequency at a 10 MHz sampling rate for the 6-bit fat tree encoder
ADC. The measured data from the 6-bit ADC shows reduced dynamic parameters due
to the noise problems. The small SINAD results in an ENOB of 3.3 bits, while the
simulated ENOB is 5.2 bits. On the other hand, the 6-bit data (1024 points) from a
pure 1 MHz sine wave input shows ideal dynamic parameters in a 6-bit ADC at 200
MHz sampling rate. Its ENOB is 5.8 bits. From the comparison with the ideal FFT test
results, we notice that the TIQ flash ADC should be less sensitive or insensitive to noise
for a SoC implementation.
82
0 1 2 3 4 5−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency(MHz)
Am
plitu
de(d
B)
0 20 40 60 80 100−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency(MHz)
Am
plitu
de(d
B)
fsample
SNR = 37.78 dBSINAD = 36.56 dBTHD = -54.24 dBSFDR = 37.86 dB
= 200 MHz, fin = 1 MHz
fsample
SNR = 23.40 dBSINAD = 21.83 dBTHD = -37.42 dBSFDR = 9.13 dB
= 10 MHz, fin = 80 KHz
(a) FFT test with measured data in 6-bit fat tree encoder
(b) FFT test with a pure sine wave
Fig. 4.19. FFT spectra of measured and ideal data
83
4.2.3 Test Results of 0.50 µm TIQ flash ADC Chips
The third fabrication used 0.50 µm CMOS technology and produced the SPICE
model T26B-lo-epi parametric test result shown in Appendix D. Since only 2 layers of
metal have been used in the ADC design, we can see more detail of the prototype chip
(Figure 4.20). The systematic increasing/decreasing sizes of the comparator transistors
Comparator
Gain boosterFat tree encoder 01 generator
Fig. 4.20. Die photo of a chip fabricated with 0.50 µm
are shown at the bottom of the photo. Also, the fat tree encoder is shown at the top
below the complicated connection lines.
For the third fabrication results, we only have the die photo of one of the four
received prototype chips. The test results for this chip will be described later.
84
Chapter 5
Low Power Applications with TIQ Comparator
Usually, low power ADC architectures are implemented with pipelined [60, 40,
59, 16, 50], successive approximation [35, 12], and Σ∆ modulator [38]. These are all
useful for the medium speed conversion and high resolution applications. On the other
hand, the flash architecture is suitable for high speed conversion and low resolution
applications due to its parallel architecture. Because many comparators compare the
reference voltage with input voltage at the same time, power consumption in the flash
architecture is much larger than for the others. Controlling the power consumption in
the comparator is the key to reducing the overall power consumption in a flash ADC.
This chapter describes two low power modifications to the TIQ flash ADC. One is
called the power and resolution adaptive flash ADC (PRA-ADC) whose resolution and
power can be changed on demand. The other is a power management method in the
TIQ flash ADC with a frequency scaling method.
5.1 The Power and Resolution Adaptive Flash ADC (PRA-ADC)
Resolution, speed, and power consumption are the three key parameters for an
ADC. These parameters cannot be changed once an ADC chip has been fabricated. Of
course, one can use only 6-bits from an 8-bit ADC chip, while the full 8-bit operation
takes place internally. Such an application is non-optimal, resulting in lower speed and
85
extra power consumption due to the full 8-bit internal operation. This proposition applies
to the flash ADCs, which are parallel, high-speed, high-power ADCs.
A new flash ADC design is proposed in this section: a true variable power and
variable resolution ADC. It is named the power and resolution adaptive ADC (PRA-
ADC) [68]. The PRA-ADC can operate at high speeds and will consume less power
when it operates at a lower resolution. This feature is highly desirable in many wireless
mobile applications. For example, the strength of a radio frequency (RF) signal varies
greatly depending on geographic location. Optimally, the ADC resolution can be reduced
upon the reception of strong signal, or the resolution can be increased upon the reception
of weak signal. The substantial reduction of power consumption at lower resolution will
prolong the battery-powered operation.
5.1.1 PRA-ADC Design and Layout
The key feature of the TIQ comparator is the fact that the comparator can easily
and quickly switch from active mode to standby mode. Figure 5.1 shows a simple addition
to the TIQ comparator input to select either the analog input voltage or the Vstby
voltage, selecting the active mode or standby mode, respectively. In the active mode,
switch S1 is on and switch S2 is off, connecting the analog input signal to the TIQ
comparator input. In the standby mode, S1 is off and S2 is on, connecting Vstby voltage
to the TIQ comparator. The analog input signal voltage varies between GND and VDD,
but the Vstby voltage is fixed either to GND or to VDD. In standby mode, the power
consumption of the TIQ comparator is due to only the leakage current of a PMOS or
86
2
1
VinVcin
S
S
φ
analog
MOD-SEL Circuit
TIQComparator
Vstby
Fig. 5.1. Active mode or standby mode selector circuit
an NMOS transistor. A great deal of power saving is thereby achieved for each TIQ
comparator when it enters the standby mode.
In the PRA-ADC, the unused TIQ comparators are switched to the standby
mode to reduce power consumption. An 8-bit flash ADC requires 28 − 1 = 255 voltage
comparators, and a 7-bit flash ADC requires 27 − 1 = 127 voltage comparators. The
8-bit PRA-ADC has 255 TIQ comparators. When it is operating at 7-bit precision, every
other TIQ comparator is switched to the standby mode, achieving almost an 50% ADC
power consumption reduction. When it is operating at 6-bit precision, every three out
of four TIQ comparators are switched to the standby mode, achieving almost an 75%
ADC power consumption reduction. Similarly a 5-bit precision results in almost 87.5%
power reduction. The comparators’ power consumption is the dominant component of
the TIQ flash ADC power consumption, and the overall power consumption is directly
proportional to the number of active comparators at any given time.
Figure 5.2 shows the block diagram of the PRA-ADC. The input signals R1 and
R2 control the ADC precision. The precision control logic unit on the lower left of
87
2R
1
12
-SELMOD
R R
ControlLogic
Precision
analogVin
Gain Booster
8
Gain Booster
Gain Booster
Gain Booster
6
Gain Booster
Gain Booster
Gain Booster
Gain Booster
C4
C1
57
Gain Booster
8bit
7bit
6bit
5bit
4 to 1 MUX (8)
8
R
Encoder
C255
C8
C7
C6
C5
φ7
C3
C2
MOD
MOD
φ6 φ5
MOD-SEL
MOD
MOD
MOD
MOD
MOD
-SEL
-SEL
-SEL
-SEL
-SEL
-SEL
-SEL
Fig. 5.2. The power and resolution adaptive ADC
88
Figure 5.2 generates the mode selection signals to selectively activate the appropriate
inverter comparators. Figure 5.3 shows the truth table of the precision control logic.
RA-ADCPrecision φ7 φ6 φ5
8-bit7-bit6-bit5-bit
00011
101
1 1 111
100 00 0 0
φ7φ6φ5
R
R
R R
ControlPrecision
Logic1
2
12
Fig. 5.3. The precision control logic
The gain booster unit consists of a number of cascaded inverters. If the inverter
comparator is in standby mode, the inverters in the gain booster unit are also in standby
mode. We use ROM to convert the thermometer code to binary code. Four encoders
are connected in parallel, shown on the right side of Figure 5.2. The 8-bit encoder is a
256×8 ROM, the 7-bit encoder is a 128×7 ROM, the 6-bit encoder is a 64×6 ROM, and
the 5-bit encoder is a 32 × 5 ROM. The appropriate ROM is selected by the precision
control signals R1 and R2. Unselected ROMs are switched into the standby mode.
Figure 5.4 shows the PRA-ADC layout using 0.18 µm CMOS technology. The
total area is 2.180mm2 (345.72µm × 630.48µm). The layout area overhead required for
adding the power and resolution adaptation feature to the fixed 8-bit TIQ flash ADC
is almost 100%. The fixed 8-bit TIQ flash ADC consists of only the TIQ comparator
89
Encoder8bitBooster
Gain7bit 6bit 5bitSelector
Mode
MUXPrecision Control Logic
Comp.TIQ
Fig. 5.4. VLSI layout of the PRA-ADC
90
column, the gain booster column, and the 8-bit encoder ROM column. One can see
the extra overhead layout area due to the mode selector column, 7-bit, 6-bit, and 5-bit
encoder ROM columns in Figure 5.4.
5.1.2 PRA-ADC Simulation Results
Table 5.1 shows a summary of the simulation results. The power dissipation is
reduced by almost 50% for each resolution bit reduction. Figure 5.5 shows the comparison
of the theoretical 50% power reduction graph and the simulation results.
Table 5.1.Summary of the PRA-ADC simulation results
Resolution Power Speed Switching O/H INL DNL VLSB
(bits) (mW ) (GSPS) (ps) (LSB) (LSB) (mV )
8 434.63 1.25 484.43 0.0347 0.0654 1.68
(5bit-to-8bit)
7 223.15 1.61 417.76 0.0162 0.0199 3.36
(8bit-to-7bit)
6 120.29 2.22 404.56 0.0025 0.0037 6.71
(7bit-to-6bit)
5 68.63 3.03 237.36 0.0015 0.0012 13.41
(6bit-to-5bit)
The third column of Table 5.1 shows the ADC speed increase as the number of
resolution bits is decreased. This is mainly due to the fact that the 128 × 7 ROM is
91
5 6 7 80
50
100
150
200
250
300
350
400
450
Resolution (bit)
Pow
er (
mW
)
Measured PowerIdeal Power Measured PowerIdeal Power
Measured PowerIdeal PowerMeasured PowerIdeal Power
Measured PowerIdeal PowerMeasured PowerIdeal PowerMeasured PowerIdeal Power
Measured PowerIdeal Power
Fig. 5.5. Power reduction comparison
faster than the 256 × 8 ROM and the 64 × 6 ROM is faster than the 128 × 7 ROM. A
smaller ROM is faster than a larger ROM. Also by comparing the 8-bit ADC speed and
the 5-bit ADC speed, we can see the fact that the predominant signal delay is due to the
encoder ROM circuit. The encoder ROM is the bottleneck of the speed in the TIQ flash
ADCs, whereas the voltage comparators are the bottleneck in the non-TIQ flash ADCs.
The fourth column of Table 5.1 shows the mode switching overhead time. The
power and resolution changes take place in less than 0.5ns, comparable to the PRA-
ADC’s high operating speed above 1 giga samples per second (GSPS). The PRA-ADC
will suffer minimal analog signal loss during the resolution change. Figure 5.6 shows
the simulation result of the ADC resolution switching and the switching overhead times.
The remaining columns in Table 5.1 show the linearity errors and VLSB change as the
ADC resolution changes.
92
Vin 800m
1
d8 0
1.5
d7 0
1.5
d6 0
1.5
d5 0
1.5
d4 0
1.5
d3 0
1.5
d2 0
1.5
d1 01.5
Time (lin) (TIME)0 20n 40n 60n 80n 100n 120n 140n 160n 180n 200n
4.1776e-108bit-to-7bit O/H
4.0456e-107bit-to-6bit O/H
2.3736e-106bit-to-5bit O/H
4.8443e-105bit-to-8bit O/H
Fig. 5.6. Resolution switching and switching overhead time
93
5.1.3 Summary of the PRA-ADC
The flash ADCs are parallel, high-speed, high-power ADCs, applicable in RF
portable communication devices. In an effort to conserve energy, we proposed a new
power and resolution adaptive flash ADC, called PRA-ADC. The PRA-ADC design
produces an exponential power reduction with a linear resolution reduction. Unused
parallel voltage comparators are switched to standby mode. These voltage comparators
dissipate only leakage power during the standby mode.
The PRA-ADC layout using a 0.18 µm CMOS design rule shows an 100% area
overhead. There is no noticeable performance overhead for the PRA-ADC. The volt-
age comparator switches between the active mode and the standby mode in less than
0.5 ns while the ADC operates at over 1 GSPS speed. The PRA-ADC allows tighter
management of power and efficiency.
5.2 A Power Management Method in the TIQ Flash ADC
Recently many techniques for building low power ADC circuits have been re-
searched [20, 35, 59, 16]. Among those techniques, voltage scaling is known as the most
effective power reduction technique. The power dissipation reduces quadratically as the
power supply voltage decreases. However the supply voltage scales down, the signal
swings will be decreased, which will degrade the ADC precision and speed. High preci-
sion and high gain voltage comparators are difficult to design for operation from a low
power supply voltage.
94
Most power reduction techniques utilize the circuit and algorithm approaches.
Instead of using large numbers of voltage comparators operating in parallel, one can use
only one voltage comparator to sequentially compare the incoming analog voltage and
produce the digital output. Such a technique is very effective in power reduction but
inevitably slow.
Another power reduction technique commonly used in digital circuits is power
switching or clock gating. Simply switch off the power supply to the circuit when it is
not used, forcing the circuit to be in stand-by mode. With the CMOS digital circuits,
this power switching can be easily achieved by stopping the clock transitions to the target
circuit.
In [10] a new power efficient scheme, called the pruning calibration technique,
for a flash ADC was introduced. This technique reduces the power consumption by
turning off some comparators during the calibration. Another approach for power control
of the comparators is to turn off all the comparators during the idle period, that is,
the comparators consume power only during the sampling period, which is small time
compared to the idle period. This idea can only be applied to the frequency scaling
method. If the sampling interval of a flash ADC can be controlled without changing
main clock speed, the power dissipation will be clearly reduced, but the speed of the
ADC, not the complete circuit, will be degraded; this is a tradeoff between power and
speed. Even though there will be speed degradation, the flash ADCs will still be relatively
faster than the other ADCs.
We apply the last technique to reduce the flash ADC power. More accurately, we
designed a flash ADC that is power manageable. The flash ADC can be operated at full
95
speed with the maximum sampling clock speed if desired and it can be operated at slower
speed with the sampling clock gated. The power consumption is directly proportional
to the sampling clock frequency. This section presents the TIQ flash ADC design with
a power management method and detailed simulation results [63].
5.2.1 Power Management Method
One of the features of the TIQ based flash ADC is that it can operate without a
clock signal; however, to control the sampling interval, we need to add some additional
circuits: a sample-and-hold (S/H) circuit for periodically sampling the input voltage and
then holding a constant value and flip-flops for extracting the digital outputs at a fixed
sampling interval. The function of the S/H circuit is to sample the input voltage when a
clock signal is high; otherwise, it holds the input voltage which will be forwarded to the
flash ADC core. The other circuits for implementing the proposed power management
method are flip-flops. The negative-edge triggered master slave D flip-flops with minimal
size transistors are used. These are connected at the end of the TIQ based flash ADC
core to clearly get the digital outputs.
The power management method with frequency scaling in the TIQ flash ADC
uses to advantage one of the major characteristics of the TIQ comparator. The power
consumption of an inverter can be shut off by using VDD or GND as an input. With this
feature, all comparators in the ADC can be powered off when they are not used, which
is called the idle period. Power dissipation in the ADC happens only at the time when
the comparators are working, which is called the sampling period. Hence, the idea of
96
this method is to control these sampling intervals by adding an AND gate and a PMOS
transistor.
Figure 5.7 shows the block diagram for the proposed power management method.
CLK represents the system clock signal, while “Sample” determines the sampling inter-
vals. According to the logic of the AND gate, the input voltage is only sampled when
both CLK and Sample are high. In the example shown in Figure 5.7, the input voltage
S/H
Read
VDD
Vin Dout
SampleCLK
TIQ flashADC
DFFs
Fig. 5.7. Power management method with TIQ flash ADC
is sampled once every two CLK signals (the “Read” signal is the output of the AND
gate). On the other hand, if the output of the AND gate is ‘0’, the S/H circuit will
be disconnected, and the PMOS transistor that is connected to VDD will be activated.
Then, the input of the TIQ flash ADC will be at the signal maximum. Therefore, there
is no power consumption in the ADC during this idle period. The CLK signal is fixed
97
at the highest conversion rate, but the rate of the Sample signal is flexible depending
on how it is controlled. The highest sampling rate can be achieved when the Sample
signal is fixed to VDD in this method. Also, the maximum power consumption will occur
at this time. By controlling the Sample signal, the ADC consumes less power on the
average, but there will be some loss in ADC speed.
This power management method is only possible in the TIQ flash ADC. By ap-
plying the proposed method to the TIQ flash ADC, there is degradation in ADC speed
because of the addition of the clock signal and S/H circuits, but there is a much larger
reduction in the ADC power dissipation. In the next section, the simulation results will
be explained.
5.2.2 Power Simulation Results
A 6-bit and an 8-bit TIQ flash ADC were used for the power management method
simulation. Their conversion rates measured by previous simulation with 1.8V supply
voltage were up to 2 GSPS for the 6-bit and 1.25 GSPS for the 8-bit ADC. Figure 5.8
shows the functionality of the 6-bit TIQ based flash ADC when the power management
method was applied. This maximum sampling speed can be obtained when the Sample
signal is equal to VDD and the CLK speed is 6.2 ns, which is shown in the 2nd row in
the Table 5.2.
The simulation summary for 6-bit and 8-bit ADCs are shown in Table 5.2. The
first simulation was performed using only the clock signal and the flip-flop to measure the
highest sampling rates when the clock signal was applied. For this condition, the speed
was degraded to 1.7 GSPS for the 6-bit ADC and 278 MSPS for the 8-bit ADC. The
98
Inpu
t
600m
800m
1
1.2
1.4
1.6
1.8
Time (lin) (TIME)0 100n 200n 300n 400n 500n 600n
d5 0
1.5
d4 0
1.5
d3 0
1.5
d2 0
1.5
d1 0
1.5
d0 01.5
Time (lin) (TIME)0 100n 200n 300n 400n 500n 600n
Fig. 5.8. 6-bit ADC simulation result with power management method
99
Table 5.2.Power simulation results of the 6-bit and 8-bit ADC
Sampling Rate Power Sampling Rate Power
6-bit ADC 6-bit ADC 8-bit ADC 8-bit ADC
(sps) (mW ) (sps) (mW )
1.7 G 203.7131 277.8 M 307.6429
161.3 M 69.3894 45.5 M 102.8967
32.3 M 14.1583 9.1 M 15.9862
6.5 M 3.3724 1.8 M 3.4259
1.3 M 0.7833 363.6 K 0.6954
258.1 K 0.1582 72.7 K 0.1398
51.6 K 0.0319
second simulation was implemented with all the additional circuits. When the sampling
interval was increased by five times, the power dissipation was proportionally reduced
for both the 6-bit and 8-bit ADCs. Figure 5.9 represents that the power dissipation is
linearly proportional to the frequency scaling.
5.2.3 Summary of the Power Management Method
The frequency scaling technique was applied to the TIQ flash ADC. Because of
its comparator architecture, this frequency scaling reduces the power consumption by
turning off whole comparators during the idle period. Also, by controlling the sampling
intervals, the power consumption of the ADC can be managed. This power management
method enables the TIQ flash ADC to be used at different sampling rates, depending on
the application. The simulation results show that the 6-bit ADC consumes 204 mW at
100
0 50 100 1500
20
40
60
80
100
Frequency (MHz)
Pow
er (
mW
)
6−bit8−bit
Fig. 5.9. Power dissipation vs. frequency
1.7 GSPS and 0.0319 mW at 51.6 KSPS; the 8-bit ADC consumes 307.6 mW at 277.8
MSPS and 0.1398 mW at 72.7 KSPS. These results show a ten times smaller power
consumption than any low power ADCs [] found in the current literature.
101
Chapter 6
Low Voltage Operation in ADCs
Currently, the minimum channel length of the transistors is 0.13 µm. This will
be scaled down to 0.065 µm in 2007 according to the roadmap of semiconductors [44].
This shortening of the minimum channel length of the transistors results in reduction
of the power supply voltage to 0.7 V . Also, the SoC trend forces analog circuits to
be integrated with digital circuits. To follow both the scaling down of the minimum
channel length of the transistors and the SoC trend, ADCs should be operated at low
voltages, especially below 1.0 V for portable devices. However, the minimum supply
voltage for the analog circuits predicted in the roadmap [44] does not follow the digital
supply voltage reduction. Analog supply voltages between 2.5 V and 1.8 V will still be
used by 2007. Therefore, it is a great challenge to design an ADC that operates at a low
supply voltage because of the relatively high threshold voltage of short channel length
transistors. As a result, an ADC should operate with a small VFSR.
Many techniques have been devised to overcome this design challenge of low volt-
age operation, such as low threshold devices [28], the bootstrap technique [12], switched-
opamps [59], and special biasing schemes [35]. In addition to these techniques, several
design strategies for low voltage ADCs have been introduced [24, 38, 48, 14]. All of these
low voltage techniques have been implemented with additional or modified circuits to
102
all known ADC architectures like the successive approximation, pipeline, flash, and Σ∆
modulator.
This chapter describes the simulation results and analysis of the TIQ flash ADCs
designed with 0.07 µm CMOS technology [64]. A new differential comparator is proposed
for low voltage operation. The new differential comparator is called the quantum voltage
(QV) comparator and uses the TIQ comparator concept for voltage comparison and the
SSV technique for choosing the internal reference voltages [65].
6.1 Low Voltage Operation with the TIQ flash ADC
The TIQ flash ADC has been simulated with the HSPICE BSIM level 49 and
0.07 µm predictive model from the University of California at Berkeley. Table 6.1 shows
the summary of the simulation results. The 6-bit and the 8-bit ADC can respectively
Table 6.1.Summary of the simulation results in 0.07 µm technology
resolution 6-bit 8-bit
CMOS tech. 0.07 µm 0.07 µm
power supply 0.7 V 0.7 V
max. speed 4.76 GSPS 3.57 GSPS
power consumption 11.32 mW 48.88 mW
VFSR 0.24 V - 0.46 V 0.24 V - 0.46 V
VLSB 3.43 mV 0.81 mV
leakage current 78.5µA 185.1µA
DNL 0.0075 LSB 0.1684 LSB
INL 0.0062 LSB 0.1234 LSB
ADC Area 0.0170 mm2 0.0625 mm2
103
operate at the speed of 4.76 GSPS and 3.57 GSPS without any missing codes at a 0.7
V power supply voltage [64]. The SPICE simulation result of the 8-bit ADC is shown in
Figure 6.1. Both the DNL and the INL shown in Figure 6.2 are less than 0.01 LSB for
the 6-bit and 0.20 LSB for the 8-bit ADC. Table 6.2 compares these results with other
ADCs. According to the comparison, the TIQ flash ADC has the highest speed, but a
large power dissipation compared to other low voltage ADCs.
Table 6.2.Comparisons with other low-voltage ADCs
ADCs Architecture Resolution VDD CMOS Speed Power
(bit) (V ) (µm) (sps) (mW )
TIQ flash 6 0.7 0.07 4.76 G 11.32
TIQ flash 8 0.7 0.07 3.57 G 48.88
[28] Σ∆ 10 1.0 0.5 384 K 1.56
[12] SAR 10 1.0 0.18 200 K
[59] pipelined 9 1.0 0.5 5 M 1.6
[35] SAR 8 1.0 1.2 50 K 0.34
[24] flash-interpolation 6 0.8 0.13 25 M 480 µW
[38] Σ∆ 14 1.1 0.35 16 K
6.1.1 Power Analysis of the TIQ flash ADC
Low power consumption is now one of the main issues in ADC design. The ADCs
in Table 6.2 consume very small amounts of power. The TIQ flash ADC architecture is
a pure flash type because all 2n − 1 comparators turn on at the same time. Therefore,
the TIQ flash ADC dissipates more power than the others. The comparator circuits are
104
Vin 300m
400m
bit7
0
600m
bit6
0
600m
bit5 0
600m
bit4 0
600m
bit3 0
600m
bit2 0
600m
bit1 0
600m
bit0 0
600m
Time (lin) (TIME)0 20n 40n 60n
* hspice file created from 8b007adc_flat.ext - technology: mmi07
Fig. 6.1. SPICE simulation result with 0.07 µm ADC
105
0 20 40 60−0.1
−0.05
0
0.05
0.1
output code
DN
L(LS
B)
(a) DNL of the 6-bit
0 20 40 60−0.1
−0.05
0
0.05
0.1
output code
INL(
LSB
)
(b) INL of the 6-bit
0 50 100 150 200 250−0.2
−0.1
0
0.1
0.2
output code
DN
L(LS
B)
(c) DNL of the 8-bit
0 50 100 150 200 250−0.2
−0.1
0
0.1
0.2
output code
INL(
LSB
)
(d) INL of the 8-bit
Fig. 6.2. Linearity errors of the ADC
106
an important consideration in power consumption. The power consumption in the TIQ
flash ADC is analyzed for each component. Table 6.3 shows the power analysis of the
TIQ flash ADC at the maximum sampling rate.
Table 6.3.Power analysis of the TIQ flash ADC by components
TIQ flash ADC 6-bit 8-bit
components (mW ) (mW )
comparator 10.618 (93.8 %) 47.983 (98.1 %)
gain booster 0.043 (0.4 %) 0.083 (0.2 %)
‘01’ generator 0.088 (0.8 %) 0.085 (0.2 %)
fat tree encoder 0.565 (5.0 %) 0.731 (1.5 %)
total 11.314 (100 %) 48.882 (100 %)
Most of the power consumption of the ADC occurs in the comparator as expected.
The comparator’s power dissipation is especially large as its resolution increases. There-
fore, the comparator section is the critical component for low power consumption. It is
hard to reduce power consumption in the flash architecture when the comparators are
operating. But, as we mentioned in Chapter 5, the power management is easy in the
TIQ comparator since the TIQ comparator can be easily turned off.
6.1.2 Voltage and Temperature Variations in 0.07 µm
In the TIQ flash ADC implementation, there are two problems that affect changes
in the offset, gain, and linearity: static variation and dynamic variation. The static
variation is the process variation. The dynamic variations are power supply voltage and
107
temperature variation. The internal reference voltages, which are fixed by the size of
the transistors, are the cause of these variations. To correct them, One can use digital
signal processing (DSP) on the ADC output. Unfortunately, there are no representation
process parameters available for 0.07 µm technology. So, only dynamic variations have
been simulated.
Table 6.4 shows the variation parameters from the 8-bit ADC simulation results
as a result of the power supply voltage and temperature variations. The default condi-
tion is a 0.7 V power supply voltage at 25oC. There are changes in both the offset and
Table 6.4.Power supply voltage and temperature variation results from the 0.07 µm 8-bit TIQ flashADC
Variations min. Vm max. Vm DNL INL
(V ) (V ) (LSB) (LSB)
0.665 V (-5 %) 0.239831 0.431048 0.1874 0.7083
0.735 V (+5 %) 0.264819 0.491096 0.1446 1.3165
−40oC 0.276854 0.423492 0.2345 2.1280
85oC 0.226461 0.490242 0.1745 2.9707
default 0.251036 0.456555 0.1684 0.1234
gain with these variations. The temperature variations show an especially large amounts
of expansion (at 85oC) or contraction (at −40oC) of the full scale range of the reference
voltages. As a result of these changes, all characteristics of the ADC including the sam-
pling rates are degraded, while there was no degradation to performance of the ADC in
the 0.25 µm technology [67, 69]. However, by using the optimal design method [22], The
DNL of the ADC shows less sensitivity over the variations than the INL. A new design
108
method for INL optimization is needed to prevent the degradation of the performance
of the ADC as temperature or power supply changes.
The TIQ flash ADC has been simulated with 0.07 µm CMOS technology to verify
functionality at low power supply voltage. Both the 6-bit and the 8-bit ADC worked
correctly at a 0.7 V with high speed sampling rates and small values of DNL and INL.
On the other hand, the static and dynamic variations are just one of the considerations
in the design of the TIQ technique. This simulation shows the TIQ technique can be
adapted to the future CMOS technologies.
6.2 Quantum Voltage Comparator
One of the major problems in the TIQ flash ADCs [67, 69], is the noise suscep-
tibility of the TIQ comparator. Because the TIQ comparator, which consists of two
cascaded inverters, has a single-ended input, the comparator is very sensitive to power
supply noise. Each TIQ comparator has an internal reference voltage set by the sizes
of the inverter’s transistors. The reference voltage is changed when there is noise in the
power supply. The changing of the reference voltage causes gain and offset errors. In
addition to the power supply voltage variation, temperature variation makes the DNL
and the INL larger in the TIQ flash ADC.
To overcome these problems, a new comparator has been used. It is a type of
differential voltage comparator. Since this comparator has two inputs for analog signals,
the common mode noise rejection is much better. This is the reason why most conven-
tional flash ADCs use a differential comparators. However, these differential comparators
require a resistor ladder circuit to provide the reference voltages (An additional external
109
circuit is needed). However, the quantum voltage (QV) comparator proposed here does
not need a resistor ladder circuit. The new QV comparator has been devised from the
simple transconductance amplifier [34] with the application of the TIQ comparator con-
cept to generate the internal reference voltages. A 0.7 V 6-bit flash ADC and an 8-bit
flash ADC have been designed with 0.07 µm CMOS technology to implement this new
QV comparator [65].
6.2.1 Simple Transconductance Amplifier
A simple transconductance amplifier (STA) circuit consists of two circuits, a cur-
rent mirror and a differential pair. Figure 6.3 shows the schematic diagram of the current
mirror and the differential pair. The current mirror is devised to provide a constant cur-
V3 V4Q3
Qb
I3
Ib
Q4
I4
Vb
(a) current mirror (b) differential pair
I2I1
Q2Q1
Fig. 6.3. Schematic of the current mirror and the differential pair [34]
rent at both drains of transistor Q1 and Q2 in Figure 6.3(a). As the gate of Q1 is
connected to its drain, the transistor Q1 is always in saturation mode. Therefore, the
110
current I2 is fixed at a constant current that is equal to the current I1. In the differential
pair shown in Figure 6.3(b), the difference between voltage V3 and V4 determines the
current I3 and I4, where I3 + I4 = Ib. Transistor Qb is a current source, which produces
a fixed current that depends on the voltage Vb.
By combining the current mirror (at the top) and the differential pair (at the
bottom), we can devise the STA circuit. This is commonly used as a transconductance
amplifier that generates a current output depending on the difference between two input
voltages. This circuit can also be used as a voltage amplifier by taking a voltage at the
output instead of a current. Many ADCs use this voltage amplifier as a comparator to
compare a reference voltage with an input voltage. The simple voltage amplifier has
been used in the proposed QV comparator.
6.2.2 Flash ADC with QV comparator
The ADC using the proposed QV comparator is a full flash type. As shown in
Figure 6.4, the ADC consists of four blocks: comparator, gain booster, ‘01’ generator,
and a fat tree encoder. An analog input voltage, Vin, is connected to each QV comparator
at the same time. The Vin is compared with an internal reference voltage Vref in each
comparator. To obtain a larger gain, a gain booster is connected to each comparator
output. Since the output of the gain booster stage is a thermometer code, an encoder
is needed to change the thermometer code to a binary code. This encoding process has
two steps. The first step is converting the thermometer code to the 1-out-of-n code
with simple XOR logic, which is implemented with NAND gates. Next, the fat tree
111
maxVm
Vmmin
Vin
Binary1-out-of-nThermometerCodeCodeCode
Analog InputVoltage
LSB
MSB
EncoderFat Tree‘01’
GeneratorGainDIVBoosterComparator
Fig. 6.4. ADC architecture using the QV comparator
112
encoder [23] is used to change the 1-out-of-n code into a binary code. A ROM type
encoder [67, 69] could also be used.
6.2.2.1 The QV Comparator
From the previous experience in fabrication of TIQ flash ADCs, we noticed that
the single-ended inverter is very sensitive to noise in both the power supply and in-
put signal. These noises resulted in a reduced precision of the fabricated ADC chips.
Consequently, a new comparator that is less sensitive to noises is needed.
The advantage of the TIQ comparator is that it is fast and simple. There is no
alternative comparator available to replace the TIQ comparator in terms of speed and
simplicity. Particularly, it is the main idea of the TIQ comparator that the reference
voltage is internally fixed by the transistor size of the inverter. Hence, no additional
circuits are needed.
The underlying idea of the TIQ comparator has been applied to the simple
transconductance amplifier (STA). To do so, we need to modify the STA implemen-
tation of the QV comparator. The schematic diagram of the proposed QV comparator
is shown in Figure 6.5(a). One can see there is no difference from the STA schematic
diagram except for changes in the W/L ratios. The VTC of the STA is similar to the
VTC of the inverter. Figure 6.5(b) shows the VTC of the QV comparator. The C0 and
C2 curves show the voltage output of one QV comparator and the voltage output of two
cascading QV comparators, respectively. Both the logic zero values of the C0 and C2
curves are not close to ground because of the lower limitation of the voltage out called
the “Vmin problem” in [34]. One can see different low voltage limits in each curve of
113
Q4Q3 (W / L)
(Wp / Lp) Q1
Qb (Wn / Ln)
(a) QV comparator
Va
Vb
Vin
V
ou
t
100m
200m
300m
400m
500m
600m
700m
Vin200m 300m 400m 500m
Vout
Q2 (Wp / Lp)
Vm3
(b) VTC of the comparator
in
C0
C1 C2 C3
Vm1
Fig. 6.5. Schematic of the QV comparator and its voltage transfer characteristic
Figure 6.5(b). This low voltage limit problem can be solved by adding a gain booster.
The gain booster in the ADC architecture makes the comparator output transition sharp
and also produces a full rail-to-rail swing.
In Figure 6.5(b), there are three different curves, C1, C2, and C3, simulated by
cascading two QV comparators. These curves illustrate that how different reference
voltages are internally obtained. In conventional differential comparators, the transistor
sizes are standardized and the input Va is taken from a Vref generated by a resistor ladder
circuit. Therefore, all 2n − 1 comparators for an n-bit flash ADC are identical, but the
externally supplied reference voltages are different. On the other hand, the proposed QV
comparator has different transistor sizes for transistors Q3 and Q4, while transistor Q1
and Q2 are identical. In addition, the input voltage Va and the bias voltage Vb are fixed
114
at a constant voltage between GND and VDD. With this intentional mismatch in the
differential pair, the reference voltages can be internally supplied to the comparators.
On account of this mismatch, 2n−1 different sizes of QV comparators are needed
for the flash ADC implementation. The curve C2 in Figure 6.5(a) has been obtained
for the case of equal sizes of the differential pair. If transistor Q3 is larger than Q4,
the C1 and Vm1 will be obtained as the VTC and the Vref , respectively. Conversely,
if transistor Q4 size is larger than Q3, the C3 and Vm3 will be obtained as the VTC
and the Vref , respectively. By systematically increasing the size of transistor Q3 and
decreasing the size of transistor Q4, each of the 2n − 1 QV comparators has a different
reference voltage in descending order as shown in Figure 6.4.
6.2.2.2 ADC Design with QV comparator
The ADC has been designed and simulated with the 0.07 µm SPICE model pa-
rameter provided by the Berkeley Predictive Technology Model (BPTM) [5]. For the
first design attempt with only one QV comparator, the performance of the ADC was
worse than expected since the rising and falling time of the comparator was different.
Using two cascaded QV comparators can stop this degradation by the unbalanced rise
and fall time. There is almost 50% penalty in area of the ADC, but a greater than 50%
performance improvement has been achieved.
Figure 6.6 shows the 8-bit flash ADC layout using two cascaded QV comparators.
This layout has been done with full custom design. One may notice that the differential
pair is systematically increased/decreased in Figure 6.6.
115
fat treeencoder
gainbooster generator
‘01’
two cascaded QV comparators
Fig. 6.6. The 8-bit QVC flash ADC layout used two cascading QV comparators
116
6.2.3 Simulation Results and Comparisons with TIQ Comparator
For a 0.7 V power supply voltage, the 6-bit and the 8-bit ADC simulation results
are shown in Table 6.5. Also, Figure 6.7 shows the SPICE simulation result of the 8-
Table 6.5.Summary of the QVC ADC simulation results
ADC resolution 6-bit 8-bit
CMOS technology 0.07 µm 0.07 µm
VDD 0.7 V 0.7 V
sampling rate 2.7 GSPS 2.0 GSPS
power consumption 4.952 mW 19.094 mW
area 0.029 mm2 0.109 mm2
VLSB 3.802 mV 0.946 mV
DNL 0.0502 LSB 0.2996 LSB
INL 0.0287 LSB 0.1581 LSB
bit ADC. The ADCs with the QV comparators (QVC flash ADC) show lower sampling
rates, lower power consumption, and lower noise sensitivity than the ADCs with the TIQ
comparators. The TIQ flash ADC with 0.07 µm CMOS technology and 0.7 V power
supply operates up to 4.76 GSPS and 3.57 GSPS with 6-bit and 8-bit resolution. The
performance of QV comparator degrades by 50.4% for 6-bit and to 56.0% for 8-bit ADC
in terms of sampling rate. The design area of the ADC, however, has been increased by
70.6% for the 6-bit and by 73.0% for the 8-bit ADC compared to the TIQ flash ADCs.
117
V
in
300m400m
d7 0
600m
d6 0
600m
d5 0
600m
d4 0
600m
d3 0
600m
d2 0
600m
d1 0
600m
d0 0600m
Time
0 20n 40n 60n 80n 100n 120n
Fig. 6.7. The SPICE simulation result of the 8-bit QVC flash ADC
118
6.2.3.1 Power Consumption Comparison with TIQ Comparator
The power dissipation in the flash ADC can be significantly reduced by using the
proposed QV comparator. Table 6.6 shows the power consumption in each circuit of
both TIQ flash ADC and the QVC flash ADC. As expected, the comparator is the most
power consuming circuit among the ADC components. In the 6-bit ADC, 93.8% and
89.8% of total power is dissipated in the comparator for TIQ flash ADC and QVC flash
ADC, respectively. In case of the 8-bit ADC, the power consumption in the comparator
is increased by 98.8% for TIQ flash ADC and 95.2% for QVC flash ADC. The comparator
in the QVC flash ADC consumes much less power than the one in the TIQ flash ADC.
The QVC flash ADC can save power dissipation by 58.1% in the 6-bit and 62.1% in the
Table 6.6.Power Consumption Comparisons with TIQ Comparator
Components TIQ 6-bit QVC 6-bit TIQ 8-bit QVC 8-bit
(mW ) (mW ) (mW ) (mW )
comparator 10.618 4.446 47.983 18.175
gain booster 0.043 0.125 0.083 0.417
‘01’ generator 0.088 0.053 0.085 0.064
encoder 0.565 0.328 0.731 0.438
total 11.314 4.952 48.589 19.094
8-bit compared to the TIQ flash ADC. The power consumption of the gain booster in
the QVC flash ADC is slightly increased.
119
6.2.3.2 Noise Comparisons with TIQ Comparator
The noise problems were the critical degradation of both performance and preci-
sion in the TIQ flash ADC. The proposed QV comparator has been designed to reduce
these noise problems. To check the noise susceptibility, power supply voltage variation
and temperature variation are used. The simulation results of these variations are shown
in Table 6.7.
In the Table 6.7, “default” means a 0.7 V power supply and a 25oC temperature.
Both the TIQ comparator and the QV comparator were designed with these default
parameters. Each percentage shows the difference from the default value. The power
supply voltage variation shows that all internal reference voltages are within 2.3% of
the default values in the proposed QV comparator. But, the rejection of power supply
voltage variation in the TIQ comparator is not as good as for the QV comparator.
The temperature variation also shows almost the same trend as power supply variation
results. The linearity errors, DNL and INL, show that the QV comparator’s linearity
is less than 0.5 LSB, however, the linearity of the TIQ comparator is much larger than
0.5 LSB even though its default DNL and INL are much smaller than those of the QV
comparator. Therefore, the QV comparator is more useful in low noise application than
the TIQ flash comparator.
6.2.4 Summary of the QV Comparator
The new QV comparator has been designed and simulated to verify the low voltage
operation. Both the 6-bit QVC flash ADC and the 8-bit QVC flash ADC are correctly
operating with high speed and low power consumption. The simulation results with
120
Table 6.7.Power supply voltage and temperature variations results
ADC Variations min. Vm max Vm VLSB DNL INL
(V ) (V ) (V ) (LSB) (LSB)
TIQ 6-bit default 0.24392951 0.45681821 0.00343369 0.0075 0.0062
0.665 V (-5%) 0.23125632 (-5.2%) 0.42730764 (-6.5%) 0.00316212 (-7.9%) 0.0246 0.1852
0.735 V (+5%) 0.25558329 (+4.8%) 0.48730602 (+6.7%) 0.00373746 (+8.8%) 0.0298 0.2587
−40oC 0.27159260 (+11.3%) 0.42369262 (-7.2%) 0.00245323 (-28.6%) 0.0632 0.4886
85oC 0.21768998 (-10.8%) 0.49055548 (+7.4%) 0.00440106 (+28.2%) 0.0681 0.6799
QVC 6-bit default 0.23800303 0.47371028 0.00380173 0.0502 0.0287
0.665 V (-5%) 0.23249937 (-2.3%) 0.46734040 (-1.3%) 0.00378776 (-0.4%) 0.0436 0.0841
0.735 V (+5%) 0.24348051 (+2.3%) 0.47970900 (+1.3%) 0.00381014 (+0.2%) 0.0561 0.0884
−40oC 0.25267587 (+6.2%) 0.44516141 (-6.0%) 0.00310461 (-18.3%) 0.0390 0.1701
85oC 0.21517652 (-9.6%) 0.48549266 (+2.5%) 0.00435994 (+14.7%) 0.0510 0.1145
TIQ 8-bit default 0.25103569 0.45655458 0.00080913 0.1684 0.1234
0.665 V (-5%) 0.23787332 (-5.2%) 0.42706004 (-6.5%) 0.00074483 (-7.9%) 0.1901 0.7986
0.735 V (+5%) 0.26318532 (+4.8%) 0.48702675 (+6.7%) 0.00088127 (+8.9%) 0.1416 1.1406
−40oC 0.27685383 (+10.3%) 0.42349234 (-7.2%) 0.00057732 (-28.6%) 0.2345 2.1280
85oC 0.22646139 (-9.8%) 0.49024182 (+7.4%) 0.00103851 (+28.3%) 0.1745 2.9707
QVC 8-bit default 0.23858866 0.47875197 0.00094552 0.2996 0.1581
0.665 V (-5%) 0.23308409 (-2.3%) 0.47232453 (-1.3%) 0.00094189 (-0.4%) 0.2859 0.3807
0.735 V (+5%) 0.24406446 (+2.3%) 0.48479614 (+1.3%) 0.00094776 (+0.2%) 0.3066 0.3502
−40oC 0.25889330 (+8.5%) 0.45531032 (-4.9%) 0.00077330 (-18.2%) 0.2740 0.4501
85oC 0.22132918 (-7.2%) 0.49972095 (+4.4%) 0.00109603 (+15.9%) 0.3230 0.4180
121
a 0.7 V power supply shows that the QV comparator has a great advantage in power
consumption and noise rejection. Figure 6.8 shows the summary chart of comparing the
QVC flash ADC with the TIQ flash ADC. All 5 factors are normalized to 1, for example,
in the case of performance, the sampling speed of the 6-bit TIQ flash ADC and the 8-bit
TIQ flash ADC is normalized to 1, respectively.
Fig. 6.8. Summary chart of comparing the QVC flash ADC with the TIQ flash ADC
The proposed QV comparator uses the differential voltage comparator architec-
ture to minimize the input-offset voltage error. Also, the QV comparator utilizes the
TIQ comparator concept to eliminate the resistor ladder circuit. As a result, a dra-
matic improvement of linearity and a large amount of power saving in an ADC can be
achieved. Therefore, the QV comparator is preferable for use in the next generation deep
sub-micron low voltage CMOS flash ADC.
122
Chapter 7
Conclusions
A simple and fast flash ADC architecture that uses two cascaded CMOS inverters
as a comparator, called Threshold Inverter Quantization (TIQ) technique, has been pro-
posed by Ali Tangel [53]. In this thesis, a new design method (systematic size variation
(SSV) technique) and a new type of encoder (fat tree encoder) have been developed for
advanced TIQ flash ADCs. Their applications can be wideband RF, wireless local loop,
radar/communications, universal computer network adaptor, and so on. The TIQ flash
ADC offers higher data conversion rates while maintaining a comparable power con-
sumption level so that it is also highly suitable for the complete SoC integration using
the standard digital CMOS process. The SSV design technique [22, 66] improved the
linearity of the ADC over the CMOS process, temperature, and power supply voltage
variations. In particular, the DNL dependence on the variations was almost eliminated in
the simulation and fabrication test results. The fat tree encoder [23] overcame the speed
limitation of the ROM type encoder, which is the bottleneck of high speed ADCs. The
simulation and fabrication test results showed that the fat tree encoder outperformed
the commonly used ROM type encoder in terms of speed, power consumption, and area
for the 6-bit TIQ flash ADC. However, an automatic layout generation tool should be
developed to ease the difficulty of the layout design.
123
In addition to the techniques for improving the performance of the TIQ flash
ADCs, two applications of the TIQ technique have been proposed in this thesis: low
power consumption and low voltage operation. Because parallel voltage comparison is
used in the flash ADC, the power consumption gets much larger as we increase the
resolution of the ADC. With the TIQ comparator feature, we have implemented both
the power and resolution adaptive flash ADC (PRA-ADC) and the power management
method in the TIQ flash ADC. The PRA-ADC can operate at different resolutions
depending on the amplitude of a reception signal in a wireless application. Substantial
reduction of power consumption at lower resolution will prolong the battery-powered
operation. The power management method can manage the power consumption by
controlling its sampling interval on demand. For the low voltage operation, the TIQ flash
ADC has been implemented with 0.07 µm CMOS technology to verify the functionality at
a low power supply voltage. Without any additional circuits, the TIQ flash ADC worked
correctly at high speeds and with small linearity errors. To reduce noise problems in
the TIQ flash ADCs, a new differential comparator, called the quantum voltage (QV)
comparator, was proposed and designed with SSV technique. The simulation results
shows that the QV comparator is preferable for the next generation deep sub-micron low
voltage CMOS flash ADC.
Table 7.1 shows a comparison of the TIQ flash ADC with other ADCs. This
comparison with other ADCs shows the TIQ flash ADCs to have smaller size, higher
speed, and lower power consumption. Therefore, we can conclude the TIQ flash ADC
is preferable for SoC implementation. The main advantage of the TIQ flash ADC is its
high speed and low power dissipation using the standard CMOS technology because an
124
Table 7.1.Comparison the TIQ flash ADC with other ADCs
ADCs Architecture Res. Tech. Speed Power Area
(bits) (µm) (MSPS) (mW ) (mm2)
TIQ w/ROM flash 6 0.18 2000 101.98 0.037
TIQ w/ROM flash 6 0.25 1000 68.98 0.051
TIQ w/FAT flash 9 0.25 (1.50) 1000 200.73 1.846
TIQ w/FAT flash 8 0.50 500 2399 1.722
TIQ[53] flash 6 0.80 200 46 0.48
[24] flash 6 0.13 22 0.48 0.3
[42] flash 6 0.18 1600 328 0.12
[37] flash 6 0.25 700 187 0.45
[37] flash 7 0.25 200 143 0.45
[11] flash 6 0.25 400 150 1.2
[58] semi-flash 12 0.25 54 295 1.0
[62] flash 4 0.25 8000 1100 0.06
[25] folding & interpolating 8 0.35 10 76 5.01
[51] subranging 8 0.35 100 108.9 0.9
[57] flash 6 0.35 1000 1155 0.8
[13] flash interpolating 6 0.35 1100 300 0.3
[47] current-interpolating 6 0.35 50 10 4.8
[52] flash 6 0.4 500 400 2.4
[7] pipeline 8 0.5 100 165 1.68
[6] flash 6 0.5 2000 970 3.99
[8] flash 6 0.6 200 380 2.7
[70] flash 6 0.6 500 330 5.25
[60] pipeline 8 0.6 150 395 1.2
125
inverter not only is typically fast but also consumes less power at the front-end of the
ADC. The other advantages of the TIQ flash ADC are
• Highly adaptable to future CMOS technology development, going to smaller feature
size and lower supply voltage.
• No need for a resistor ladder circuit as the reference voltage source.
• No need for switches, clock signals, or coupling capacitors for the voltage compar-
ison.
• Suitable for the standard CMOS technology - ideal for the complete SoC imple-
mentation.
In contrast, the following two criteria must be carefully considered to obtain a successful
TIQ flash ADC implementation:
• The ADC input range varies due to process parameter changes from one fabrication
to another fabrication.
• The inverter input is single ended, not differential, causing the ADC to become
more susceptible to noise.
The following studies are projected for future works.
• Reducing the noise effects: The noise problems were the major factor of ADC
performance degradation in the chip test results. These noise effects will be espe-
cially critical as the CMOS technology goes down to sub-micron dimensions. A
combination of a well-designed layout strategy, the deep trench isolation, and a
separate analog power supply may significantly minimize the noise effects.
126
• Reducing the linearity errors: The linearity errors are also a concern when the
CMOS technology scales down. To improve the DNL, the SSV design technique
was used in the TIQ flash ADC. But, we still see the large variations in the INL.
As a dynamic solution, we may add a programmable pre-amplifier to the signal
input of the TIQ flash ADC to adjust the offset and gain.
• Automatic generation of fat tree encoder: With the fat tree encoder, we
could increase the TIQ flash ADC speed, however, it is difficult to design the fat
tree encoder because of the connections in the sub-trees. An automatic generation
of the fat tree encoder will make the design process faster.
127
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Appendix A
DNL and INL Calculating Program
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
WarnNExit1()
{
printf( "Memory allocation failed !!\n" );
exit( -1 );
}
main( int argc, char* argv[] )
{
double *inl, *dnl, *selVm;
double prevVm, idealLSBVm, temp1, temp2, temp3;
int i, numOfBit, numOfVm;
char outFileName1[40], outFileName2[40];
FILE *fp_in, *fp_out_dnl, *fp_out_inl;
if( argc != 2 )
{
printf( "Usage: iderr xBit_VmFile\n" );
exit( -1 );
}
printf( "Which bit ADC is it ? " ); scanf( "%d", &numOfBit );
numOfVm = (int)pow(2.0, (double)numOfBit)-1;
inl = (double *)malloc( numOfVm*sizeof(double) );
if( inl == NULL ) WarnNExit1();
dnl = (double *)malloc( numOfVm*sizeof(double) );
if( dnl == NULL ) WarnNExit1();
selVm = (double *)malloc( numOfVm*sizeof(double) );
if( selVm == NULL ) WarnNExit1();
fp_in = fopen( argv[1], "r" );
for( i=0; i<numOfVm; i++ )
{
fscanf( fp_in, "%lf", &selVm[i] );
}
fclose( fp_in );
138
idealLSBVm = (selVm[numOfVm-1]-selVm[0]) / (numOfVm-1);
prevVm = selVm[0]-idealLSBVm;
for( i=0; i<numOfVm; i++ )
{
dnl[i] = ((selVm[i]-prevVm)/idealLSBVm) - 1.0;
inl[i] = ((selVm[i]-selVm[0])/idealLSBVm) - (double)i;
prevVm = selVm[i];
}
strcpy( outFileName1, argv[1] );
strcat( outFileName1, "_dnl.m" );
strcpy( outFileName2, argv[1] );
strcat( outFileName2, "_inl.m" );
fp_out_dnl = fopen( outFileName1, "w" );
fp_out_inl = fopen( outFileName2, "w" );
fprintf( fp_out_dnl, "x = [\n" );
fprintf( fp_out_inl, "x = [\n" );
for( i=0; i<numOfVm; i++)
{
fprintf( fp_out_dnl, "%d; \n", i );
fprintf( fp_out_inl, "%d; \n", i );
}
fprintf( fp_out_dnl, "]\n\n" );
fprintf( fp_out_inl, "]\n\n" );
fprintf( fp_out_dnl, "y = [\n" );
fprintf( fp_out_inl, "y = [\n" );
for( i=0; i<numOfVm; i++ )
{
fprintf( fp_out_dnl, "%13.10f; \n", dnl[i] );
fprintf( fp_out_inl, "%13.10f; \n", inl[i] );
}
fprintf( fp_out_dnl, "]\n" );
fprintf( fp_out_inl, "]\n" );
fclose( fp_out_dnl );
fclose( fp_out_inl );
free( inl );
free( dnl );
free( selVm );
}
139
Appendix B
MOSIS Parametric Test Results
for TSMC 0.25 µm CMOS Run
MOSIS PARAMETRIC TEST RESULTS
RUN: T14Y (LO_EPI) VENDOR: TSMC
TECHNOLOGY: SCN025 FEATURE SIZE: 0.25 microns
INTRODUCTION: This report contains the lot average results obtained by MOSIS
from measurements of MOSIS test structures on each wafer of
this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
COMMENTS: TSMC 0251P5M
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 0.36/0.24
Vth 0.51 -0.50 volts
SHORT 20.0/0.24
Idss 548 -249 uA/um
Vth 0.53 -0.54 volts
Vpt 7.6 -7.2 volts
WIDE 20.0/0.24
Ids0 6.9 < 2.5 pA/um
LARGE 50/50
Vth 0.44 -0.58 volts
Vjbkd 5.9 -7.0 volts
Ijlk <50.0 <50.0 pA
Gamma 0.44 0.63 V^0.5
K’ (Uo*Cox/2) 120.1 -23.9 uA/V^2
Low-field Mobility 403.46 80.29 cm^2/V*s
COMMENTS: Poly bias varies with design technology. To account for mask and
etch bias use the appropriate value for the parameters XL and XW
in your SPICE model card.
Design Technology XL XW
----------------- ------- ------
140
SCN5M_DEEP (lambda=0.12) 0.03 -0.04
thick oxide, NMOS 0.02 -0.04
thick oxide, PMOS -0.03 -0.04
TSMC25 0.03 0.00
thick oxide, NMOS 0.03 0.00
thick oxide, PMOS 0.03 0.00
SCN5M_SUBM (lambda=0.15) -0.03 0.00
thick oxide, NMOS 0.02 0.00
thick oxide, PMOS -0.03 0.00
FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS
Vth Poly >6.6 <-6.6 volts
PROCESS PARAMETERS N+ACTV P+ACTV POLY N+BLK MTL1 MTL2 MTL3 UNITS
Sheet Resistance 4.4 3.4 4.0 58.9 0.07 0.07 0.07 ohms/sq
Contact Resistance 5.8 5.0 5.0 3.26 6.08 ohms
Gate Oxide Thickness 58 angstrom
PROCESS PARAMETERS PLY+BLK MTL4 MTL5 N_WELL UNITS
Sheet Resistance 184.5 0.07 0.03 1076 ohms/sq
Contact Resistance 9.40 12.14 ohms
COMMENTS: BLK is silicide block.
CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY M1 M2 M3 M4 M5 N_WELL UNITS
Area (substrate) 1770 1921 101 39 19 13 9 8 65 aF/um^2
Area (N+active) 5968 52 21 14 12 10 aF/um^2
Area (P+active) 5726 aF/um^2
Area (poly) 63 18 11 8 6 aF/um^2
Area (metal1) 39 16 10 7 aF/um^2
Area (metal2) 41 16 10 aF/um^2
Area (metal3) 44 16 aF/um^2
Area (metal4) 45 aF/um^2
Fringe (substrate) 425 357 21 61 56 43 25 aF/um
Fringe (poly) 71 42 31 25 22 aF/um
Fringe (metal1) 56 37 30 25 aF/um
Fringe (metal2) 58 37 31 aF/um
Fringe (metal3) 54 42 aF/um
Fringe (metal4) 63 aF/um
Overlap (N+active) 614 aF/um
Overlap (P+active) 674 aF/um
CIRCUIT PARAMETERS UNITS
Inverters K
Vinv 1.0 1.02 volts
141
Vinv 1.5 1.07 volts
Vinv 2.0 1.12 volts
Gain 2.0 -16.65
Ring Oscillator Freq.
DIV1024_T (31-stg,3.3V) 199.80 MHz
DIV1024 (31-stg,2.5V) 260.20 MHz
Ring Oscillator Power
DIV1024_T (31-stg,3.3V) 0.13 uW/MHz/gate
DIV1024 (31-stg,2.5V) 0.06 uW/MHz/gate
COMMENTS: DEEP_SUBMICRON
T14Y SPICE BSIM3 VERSION 3.1 PARAMETERS
SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8
* DATE: May 21/01
* LOT: T14Y WAF: 101
* Temperature_parameters=Default
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3877332
+K1 = 0.4503218 K2 = 7.498548E-3 K3 = 1E-3
+K3B = 2.7511903 W0 = 1E-7 NLX = 2.684962E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4948826 DVT1 = 0.5924031 DVT2 = -0.5
+U0 = 300.237024 UA = -1.207596E-9 UB = 2.358208E-18
+UC = 2.411595E-11 VSAT = 1.423302E5 A0 = 1.4820567
+AGS = 0.2493074 B0 = -2.000837E-7 B1 = 3.568634E-6
+KETA = 9.120027E-4 A1 = 3.802033E-5 A2 = 0.4500971
+RDSW = 117.272191 PRWG = 0.5 PRWB = -0.2
+WR = 1 WINT = 0 LINT = 4.377598E-9
+XL = 3E-8 XW = -4E-8 DWG = -2.290208E-8
+DWB = 5.476111E-9 VOFF = -0.0948739 NFACTOR = 1.9975727
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 4.108112E-3 ETAB = 8.333134E-4
+DSUB = 0.0311455 PCLM = 1.8275359 PDIBLC1 = 0.9990847
+PDIBLC2 = 4.688174E-3 PDIBLCB = -0.0999829 DROUT = 0.8506408
+PSCBE1 = 7.991332E10 PSCBE2 = 5.16406E-10 PVAG = 0.0099971
+DELTA = 0.01 RSH = 4.4 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.14E-10 CGSO = 6.14E-10 CGBO = 1E-12
+CJ = 1.753617E-3 PB = 0.99 MJ = 0.4591946
+CJSW = 4.328986E-10 PBSW = 0.99 MJSW = 0.3552107
142
+CJSWG = 3.29E-10 PBSWG = 0.99 MJSWG = 0.3552107
+CF = 0 PVTH0 = -0.01 PRDSW = -10
+PK2 = 2.428891E-3 WKETA = 0.0103867 LKETA = -7.732829E-3 )
*
.MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.8E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.5887506
+K1 = 0.6126803 K2 = 7.885899E-3 K3 = 0
+K3B = 14.442188 W0 = 1E-6 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.3705962 DVT1 = 0.7414674 DVT2 = -0.1278685
+U0 = 121.9538647 UA = 1.62789E-9 UB = 1E-21
+UC = -1E-10 VSAT = 2E5 A0 = 0.9432943
+AGS = 0.1657709 B0 = 1.621073E-6 B1 = 5E-6
+KETA = 0.01749 A1 = 6.582776E-4 A2 = 0.3
+RDSW = 1.050595E3 PRWG = 0.1217968 PRWB = -0.3344162
+WR = 1 WINT = 0 LINT = 3.148114E-8
+XL = 3E-8 XW = -4E-8 DWG = -4.599354E-8
+DWB = 3.248109E-8 VOFF = -0.1241961 NFACTOR = 1.2000247
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.4473028 ETAB = -0.1020914
+DSUB = 0.9345426 PCLM = 0.7700996 PDIBLC1 = 8.653573E-4
+PDIBLC2 = 0.0213771 PDIBLCB = -1E-3 DROUT = 0.4304851
+PSCBE1 = 2.607383E10 PSCBE2 = 6.650832E-9 PVAG = 6.011881E-3
+DELTA = 0.01 RSH = 3.4 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.74E-10 CGSO = 6.74E-10 CGBO = 1E-12
+CJ = 1.913294E-3 PB = 0.9893175 MJ = 0.4712889
+CJSW = 3.825105E-10 PBSW = 0.6116479 MJSW = 0.296387
+CJSWG = 2.5E-10 PBSWG = 0.6116479 MJSWG = 0.296387
+CF = 0 PVTH0 = 6.429985E-3 PRDSW = -12.3017562
+PK2 = 3.434527E-3 WKETA = 0.0244275 LKETA = -0.0136271 )
*
143
Appendix C
MOSIS Parametric Test Results
for TSMC 0.18 µm CMOS Run
MOSIS PARAMETRIC TEST RESULTS
RUN: T1AX (LO_EPI) VENDOR: TSMC
TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns
INTRODUCTION: This report contains the lot average results obtained by MOSIS
from measurements of MOSIS test structures on each wafer of
this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
COMMENTS: DSCN6M018_TSMC
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 0.27/0.18
Vth 0.54 -0.56 volts
SHORT 20.0/0.18
Idss 537 -255 uA/um
Vth 0.54 -0.55 volts
Vpt 4.8 -5.4 volts
WIDE 20.0/0.18
Ids0 10.5 -4.3 pA/um
LARGE 50/50
Vth 0.45 -0.44 volts
Vjbkd 3.8 -5.1 volts
Ijlk <50.0 <50.0 pA
Gamma 0.55 0.64 V^0.5
K’ (Uo*Cox/2) 163.1 -35.3 uA/V^2
Low-field Mobility 396.76 85.87 cm^2/V*s
COMMENTS: Poly bias varies with design technology. To account for mask and
etch bias use the appropriate value for the parameters XL and XW
in your SPICE model card.
Design Technology XL XW
----------------- ------- ------
144
SCN6M_DEEP (lambda=0.09) -0.02 -0.01
thick oxide -0.03 -0.01
TSMC18 -0.02 0.00
thick oxide -0.02 0.00
SCN6M_SUBM (lambda=0.10) -0.04 0.00
thick oxide -0.07 0.00
FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS
Vth Poly >6.6 <-6.6 volts
COMMENTS:
PROCESS PARAMETERS N+ACTV P+ACTV POLY N+BLK PLY+BLK MTL1 MTL2 UNITS
Sheet Resistance 6.8 7.6 7.9 59.8 332.0 0.08 0.08 ohms/sq
Contact Resistance 11.2 11.5 10.1 5.17 ohms
Gate Oxide Thickness 42 angstrom
PROCESS PARAMETERS MTL3 MTL4 MTL5 MTL6 N_WELL UNITS
Sheet Resistance 0.08 0.07 0.07 0.03 971 ohms/sq
Contact Resistance 9.99 15.10 19.91 23.55 ohms
COMMENTS: BLK is silicide block.
CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY M1 M2 M3 M4 M5 M6 N_WELL UNITS
Area (substrate) 972 1127 99 37 18 13 8 8 3 70 aF/um^2
Area (N+active) 8160 49 19 13 10 9 8 aF/um^2
Area (P+active) 7944 aF/um^2
Area (poly) 60 16 10 7 5 4 aF/um^2
Area (metal1) 36 14 9 6 5 aF/um^2
Area (metal2) 37 14 9 6 aF/um^2
Area (metal3) 36 15 9 aF/um^2
Area (metal4) 41 14 aF/um^2
Area (metal5) 33 aF/um^2
Area (no well) 145 aF/um^2
Fringe (substrate) 263 222 15 58 53 41 23 -- aF/um
Fringe (poly) 63 38 29 23 20 17 aF/um
Fringe (metal1) 54 34 22 19 aF/um
Fringe (metal2) 51 35 27 22 aF/um
Fringe (metal3) 55 35 27 aF/um
Fringe (metal4) 57 35 aF/um
Fringe (metal5) 52 aF/um
Overlap (P+active) 650 aF/um
COMMENTS:
CIRCUIT PARAMETERS UNITS
Inverters K
Vinv 1.0 0.76 volts
Vinv 1.5 0.80 volts
Vol (100 uA) 2.0 0.08 volts
145
Voh (100 uA) 2.0 1.62 volts
Vinv 2.0 0.83 volts
Gain 2.0 -24.58
Ring Oscillator Freq.
D1024_THK (31-stg,3.3V) 322.43 MHz
DIV1024 (31-stg,1.8V) 372.40 MHz
Ring Oscillator Power
D1024_THK (31-stg,3.3V) 0.07 uW/MHz/gate
DIV1024 (31-stg,1.8V) 0.02 uW/MHz/gate
COMMENTS: DEEP_SUBMICRON
T1AX SPICE BSIM3 VERSION 3.1 PARAMETERS
SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8
* DATE: Dec 4/01
* LOT: T1AX WAF: 4001
* Temperature_parameters=Default
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.2E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3805625
+K1 = 0.5981832 K2 = 2.175458E-3 K3 = 1E-3
+K3B = 2.629076 W0 = 1E-7 NLX = 2.149234E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.4116057 DVT1 = 0.3365752 DVT2 = 0.0697787
+U0 = 297.4590133 UA = -6.78356E-10 UB = 1.33445E-18
+UC = -4.61214E-12 VSAT = 9.309996E4 A0 = 1.8184754
+AGS = 0.3492206 B0 = -1.585191E-8 B1 = -1E-7
+KETA = 5.39682E-3 A1 = 0 A2 = 1
+RDSW = 124.5038577 PRWG = 0.5 PRWB = -0.2
+WR = 1 WINT = 0 LINT = 5.802111E-9
+XL = -2E-8 XW = -1E-8 DWG = -1.17481E-8
+DWB = -3.105321E-9 VOFF = -0.0836352 NFACTOR = 2.5
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0 ETAB = -0.0366657
+DSUB = 1 PCLM = 1.0387434 PDIBLC1 = 0.178682
+PDIBLC2 = 0.01 PDIBLCB = -0.0826371 DROUT = 0.653609
+PSCBE1 = 1.032223E9 PSCBE2 = 5.396023E-10 PVAG = 0.220923
+DELTA = 0.01 RSH = 6.8 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.75E-10 CGSO = 7.75E-10 CGBO = 1E-12
+CJ = 9.673165E-4 PB = 0.7293021 MJ = 0.3622159
+CJSW = 2.597686E-10 PBSW = 0.6680142 MJSW = 0.1233505
+CJSWG = 3.3E-10 PBSWG = 0.6680142 MJSWG = 0.1233505
+CF = 0 PVTH0 = 2.743569E-4 PRDSW = -4.9618035
146
+PK2 = 6.870311E-4 WKETA = 7.774837E-3 LKETA = -9.045823E-3
+PU0 = 37.3850131 PUA = 1.660666E-10 PUB = 9.47369E-25
+PVSAT = 1.98836E3 PETA0 = -1E-4 PKETA = -4.207608E-3 )
*
.MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.2E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.4244996
+K1 = 0.599858 K2 = 0.0279437 K3 = 0
+K3B = 11.7223493 W0 = 1E-6 NLX = 9.709252E-8
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4283261 DVT1 = 0.2481671 DVT2 = 0.1
+U0 = 118.6156817 UA = 1.583381E-9 UB = 1E-21
+UC = -1E-10 VSAT = 2E5 A0 = 1.6970275
+AGS = 0.3889784 B0 = 1.561212E-6 B1 = 5E-6
+KETA = 0.0182318 A1 = 0.3633365 A2 = 0.3
+RDSW = 255.0721045 PRWG = 0.5 PRWB = -0.4238984
+WR = 1 WINT = 0 LINT = 1.942069E-8
+XL = -2E-8 XW = -1E-8 DWG = -3.974819E-8
+DWB = 6.976785E-9 VOFF = -0.0985219 NFACTOR = 2
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0426564 ETAB = -0.1822938
+DSUB = 0.7200259 PCLM = 2.1991692 PDIBLC1 = 1.832458E-3
+PDIBLC2 = 0.0125103 PDIBLCB = -1E-3 DROUT = 0
+PSCBE1 = 2.048769E9 PSCBE2 = 5.917325E-10 PVAG = 13.5059723
+DELTA = 0.01 RSH = 7.6 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.5E-10 CGSO = 6.5E-10 CGBO = 1E-12
+CJ = 1.116942E-3 PB = 0.8657518 MJ = 0.4292283
+CJSW = 2.000101E-10 PBSW = 0.6339172 MJSW = 0.2893301
+CJSWG = 4.22E-10 PBSWG = 0.6339172 MJSWG = 0.2893301
+CF = 0 PVTH0 = 1.786781E-3 PRDSW = 11.8314491
+PK2 = 2.552749E-3 WKETA = 2.467859E-3 LKETA = 0.0154256
+PU0 = -1.7513087 PUA = -7.55425E-11 PUB = 1E-21
+PVSAT = -50 PETA0 = 1E-4 PKETA = 1.743747E-3 )
*
147
Appendix D
MOSIS Parametric Test Results
for AMI C5 (0.50 µm) Run
MOSIS PARAMETRIC TEST RESULTS
RUN: T26B VENDOR: AMI
TECHNOLOGY: SCN05 FEATURE SIZE: 0.5 microns
INTRODUCTION: This report contains the lot average results obtained by MOSIS
from measurements of MOSIS test structures on each wafer of
this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
COMMENTS: American Microsystems, Inc. C5N
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 3.0/0.6
Vth 0.80 -0.93 volts
SHORT 20.0/0.6
Idss 443 -243 uA/um
Vth 0.70 -0.91 volts
Vpt 10.0 -10.0 volts
WIDE 20.0/0.6
Ids0 < 2.5 < 2.5 pA/um
LARGE 50/50
Vth 0.72 -0.95 volts
Vjbkd 11.6 -11.8 volts
Ijlk <50.0 <50.0 pA
Gamma 0.49 0.59 V^0.5
K’ (Uo*Cox/2) 58.6 -18.8 uA/V^2
Low-field Mobility 478.57 153.53 cm^2/V*s
COMMENTS: Poly bias varies with design technology. To account for mask and
etch bias use the appropriate value for the parameter XL in your
SPICE model card.
Design Technology XL
----------------- -------
148
SCN_SUBM (lambda=0.30) 0.00
AMI_C5 0.00
SCN (lambda=0.35) -0.10
FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS
Vth Poly >15.0 <-15.0 volts
PROCESS PARAMETERS N+ACTV P+ACTV POLY POLY2 MTL1 MTL2 MTL3 UNITS
Sheet Resistance 84.5 104.6 22.1 39.0 0.09 0.10 0.04 ohms/sq
Contact Resistance 58.4 138.5 15.2 24.7 0.77 0.70 ohms
Gate Oxide Thickness 141 angstrom
PROCESS PARAMETERS N\PLY N_WELL UNITS
Sheet Resistance 829 825 ohms/sq
Contact Resistance ohms
COMMENTS: N\POLY is N-well under polysilicon.
CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY POLY2 M1 M2 M3 N_WELL UNITS
Area (substrate) 424 727 87 33 17 11 41 aF/um^2
Area (N+active) 2441 37 17 12 aF/um^2
Area (P+active) 2359 aF/um^2
Area (poly) 883 64 17 10 aF/um^2
Area (poly2) 58 aF/um^2
Area (metal1) 37 14 aF/um^2
Area (metal2) 39 aF/um^2
Fringe (substrate) 315 262 76 59 40 aF/um
Fringe (poly) 58 41 30 aF/um
Fringe (metal1) 55 37 aF/um
Fringe (metal2) 59 aF/um
Overlap (N+active) 207 aF/um
Overlap (P+active) 264 aF/um
CIRCUIT PARAMETERS UNITS
Inverters K
Vinv 1.0 2.04 volts
Vinv 1.5 2.29 volts
Vol (100 uA) 2.0 0.13 volts
Voh (100 uA) 2.0 4.85 volts
Vinv 2.0 2.47 volts
Gain 2.0 -20.10
Ring Oscillator Freq.
DIV256 (31-stg,5.0V) 94.92 MHz
D256_WIDE (31-stg,5.0V) 148.91 MHz
Ring Oscillator Power
DIV256 (31-stg,5.0V) 0.47 uW/MHz/gate
D256_WIDE (31-stg,5.0V) 0.99 uW/MHz/gate
149
COMMENTS: SUBMICRON
T26B SPICE BSIM3 VERSION 3.1 PARAMETERS
SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8
* DATE: Aug 13/02
* LOT: T26B WAF: 3203
* Temperature_parameters=Default
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 1.41E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.6831202
+K1 = 0.8816805 K2 = -0.0937802 K3 = 20.4100577
+K3B = -7.2365541 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 3.4115308 DVT1 = 0.4312588 DVT2 = -0.1015774
+U0 = 459.4056043 UA = 1E-13 UB = 1.53315E-18
+UC = 1.752656E-11 VSAT = 1.742215E5 A0 = 0.6040461
+AGS = 0.1336177 B0 = 2.906546E-6 B1 = 5E-6
+KETA = -1.278225E-3 A1 = 4.683373E-5 A2 = 0.3328298
+RDSW = 1.495435E3 PRWG = 0.0317989 PRWB = 0.0354674
+WR = 1 WINT = 2.770012E-7 LINT = 3.032999E-8
+XL = 0 XW = 0 DWG = -2.186171E-8
+DWB = 5.441284E-8 VOFF = -8.357693E-4 NFACTOR = 1.047271
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0132197 ETAB = -2.498627E-3
+DSUB = 0.3061953 PCLM = 2.6357241 PDIBLC1 = -0.0801838
+PDIBLC2 = 3.41146E-3 PDIBLCB = 0.0459471 DROUT = 0.4643998
+PSCBE1 = 5.782445E8 PSCBE2 = 6.530591E-5 PVAG = 0
+DELTA = 0.01 RSH = 84.5 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.07E-10 CGSO = 2.07E-10 CGBO = 1E-9
+CJ = 4.202552E-4 PB = 0.9853234 MJ = 0.4429826
+CJSW = 3.292519E-10 PBSW = 0.1 MJSW = 0.1129753
+CJSWG = 1.64E-10 PBSWG = 0.1 MJSWG = 0.1129753
+CF = 0 PVTH0 = 0.0333334 PRDSW = 211.9317467
+PK2 = -0.0299731 WKETA = -0.0240476 LKETA = 1.965474E-3 )
*
.MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 1.41E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.9195653
+K1 = 0.5559776 K2 = 8.698444E-3 K3 = 5.9729105
+K3B = -0.591565 W0 = 1E-8 NLX = 4.077083E-8
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.1960105 DVT1 = 0.5261473 DVT2 = -0.1202092
+U0 = 220.7789332 UA = 3.151288E-9 UB = 1E-21
150
+UC = -5.13969E-11 VSAT = 1.741524E5 A0 = 0.8761413
+AGS = 0.1501171 B0 = 9.729034E-7 B1 = 5E-6
+KETA = -2.596552E-3 A1 = 0 A2 = 0.3
+RDSW = 3E3 PRWG = -0.0382094 PRWB = -4.289989E-3
+WR = 1 WINT = 3.026679E-7 LINT = 4.990553E-8
+XL = 0 XW = 0 DWG = -2.441288E-8
+DWB = 2.090226E-8 VOFF = -0.0705362 NFACTOR = 0.8513831
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.3028635 ETAB = -0.0641126
+DSUB = 1 PCLM = 2.2191478 PDIBLC1 = 0.0483969
+PDIBLC2 = 3.628304E-3 PDIBLCB = -0.060075 DROUT = 0.2330696
+PSCBE1 = 5.115908E9 PSCBE2 = 5.003749E-10 PVAG = 0.0149972
+DELTA = 0.01 RSH = 104.5 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.64E-10 CGSO = 2.64E-10 CGBO = 1E-9
+CJ = 7.225681E-4 PB = 0.9574686 MJ = 0.4979615
+CJSW = 2.836454E-10 PBSW = 0.99 MJSW = 0.2895449
+CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = 0.2895449
+CF = 0 PVTH0 = 5.98016E-3 PRDSW = 14.8598424
+PK2 = 3.73981E-3 WKETA = 4.213663E-3 LKETA = -5.008006E-3 )
*
Vita
Jincheol Yoo was born in Seoul, Korea on June 24, 1967. He received a Bachelor
of Science degree in Computer Science from the Korea Military Academy (KMA), Seoul,
Korea in 1989. At the same time, he was commissioned as a second lieutenant. He then
served at the Korean Army as a platoon leader. In 1991, he was sent to the Department
of Statistics at the Iowa State University for his MS degree by the Korean Army and
the KMA. After getting his MS degree, he joined the Department of Mathematics at
the KMA as an instructor. In 1995, he was transferred to the Department of Computer
Science at the KMA as a full-time instructor. With full support from the Korean Army
and the KMA, he enrolled in the Ph.D. program in Computer Science and Engineering
at the Pennsylvania State University in August, 1998. His research interests include
high speed and low power ADC design for system-on-chip and design automation of
mixed-signal circuits.
Jincheol Yoo is a student member of IEEE Circuits and Systems Society, and
IEEE Solid-State Circuits Society.