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A PRAGMATIC JOURNEY INTO FORMAL VERIFICATION

THURSDAY, MAY 15, 2014

Chris Brown and Neha Ashu Broadcom® Cambridge

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Describe formal initiative

Aims

Targets

What have we learned so far?

Formal verification applications

Engineers’ attitudes

Tools

Questions?

AGENDA

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Is an IP and chip-design center.

There are approximately 200 employees on site.

We are part of Broadcom’s Mobile Product Solutions BU.

We create market-leading video, imaging, and 3D solutions for use in mobile application processors.

We are the home of the “Raspberry Pi Apps Processor.”

BROADCOM IN CAMBRIDGE

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Inspired by last year’s event, we started a formal verification initiative within Broadcom Cambridge.

Aims:

Bugs: Found earlier, are cheaper

Simple and stand-alone methodology

FORMAL VERIFICATION INITIATIVE

UVM

FPGA

SILICON

BUG TRIANGLE

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Reduce time spent using UVM to find simple bugs by using formal verification “apps”.

Automatic Register description vs. RTL proof app

Dead code analysis app

Code coverage closure app

X propagation app

Protocol proof kits such as AXI4

Resource, freed up by spending less time with UVM for simple bugs, used for proving targeted assertions.

Select assertions that augment or replace UVM work.

Functional Verification Utopia

FPGA hardware bugs: 0

Silicon bugs: 0

To be able to sign off appropriate blocks with formal verification only.

INITIATIVE TARGETS

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Formal verification “apps”

Intended to give easier access to some parts of formal verification.

Do not be fooled; they are not necessarily easy!

Register-proof app

Needed helper code to understand how to drive control buses.

Struggled with status registers.

WHAT HAVE WE LEARNED?

Logic

Read-only

Status register

APB

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People with a simulation verification background are keen and interested in formal techniques. They see it as:

An additional skill in their toolkit.

An opportunity to reduce some effort in constrained random test benches.

Biggest barrier is methodology. I have a spec.

I have a design.

I have an assertion language.

Now what?

Need to have better understanding of formal techniques for a complete solution (end-to-end checking).

WHAT HAVE WE LEARNED? (2)

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Formal verification tools need a lot of CPU and a lot of memory.

Configuration of the formal tools to optimise for CPU and memory is not necessarily good “out of the box”.

Before AE help memory usage: >100 Gigabyte (with 1 m/c for all engines).

After AE help memory usage: ~16 Gigabit (with multiple m/c for different engines).

Good/active support from the EDA company. AE is a requirement to get the tools configured properly for optimum performance.

WHAT HAVE WE LEARNED? (3)

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We have invested significant engineering time in learning to work with the tools and methodologies.

ROI?

Our Specifics

Our IP development for current generation was almost complete as we started formal initiative.

IP had already been verified in UVM/FPGA extensively over a long period of time.

Very few bugs left to find!

Adopting/learning in preparation for next round of IP development.

ROI

Debugging FPGA/test chip silicon issues.

Rather than spend days trying to recreate an FPGA/test chip silicon issue in simulation.

Write assertions for the symptoms.

Use formal tools to provide a counter example.

HOW DO YOU MEASURE SUCCESS OF ADOPTING FORMAL TOOLS?

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Find out the designs which are good candidates to formally verify.

Completely signing off designs using formal verification.

Any checklist to check against

Metrics to measure the completeness of verification before sign-off

FUTURE CHALLENGES TO TACKLE

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Traditional (?) coverage-driven, constrained random-verification engineers are happy to learn formal verification.

Get them methodology training to quickly move up the learning curve.

Formal apps are not as easy/quick to deploy as you might have been led to believe.

Tool setup is key for good performance of formal verification tools.

CONCLUSIONS

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Thank You!

QUESTIONS?