A Leakage Current Replica Keeper for Dynamic Circuits

Based on the work presented in “A leakage Current Replica Keeper for Dynamic Circuits” by:

Yolin lih, Nestoras Tzartzanis, William W. Walker

Fujitsu Laboratories of America, Sunnyvale, CA

presented in ISSCC 2006/Session 24/High performance Digital Circuits/24.4

For class presentation in Advanced VLSI Course, Tehran University, Fall 2006

By: Bardia Bozorgzadeh

Professor: Dr. S. M. Fakhraie

Outline Introduction Conventional keepers and their problems Existing solutions and their problems Leakage current replica keeper proposal Application to a mutli-port SRAM Measurements Conclusion References

Introduction Dynamic circuits are indispensable for constructing wide high-

speed OR and AND-OR gates in CMOS. Faster and more compact than conventional logic gates. Required to build memories. These gates need keepers to maintain a high state during

evaluation.

Conventional Keeper

Conventional keeper is sized for worst-case (sPfN process corner) leakage current.[1]

Also should be week enough so that a single NFET leg can pull the dynamic node quickly in fPsN process corner.[1]

Upper limit on the number of legs decreases as processes are scaled.[1]

Delay for conventional keeper

Keeper is sized for a max voltage drop of 0.1VDD on node DN with DC noise of 0.15VDD applied to 1/4 of legs in sPfN corner.[1]

Gate fails to switch for more than 24 legs.[1] Domino gates with conventional keeper will no longer be designable.[1]

Existing solutions Conditional keeper

overhead ≥ 5 FETs

must estimate delay. (could be large)[1]

Adaptive keeperover head ≥ 4 FETs

None of these track the two critical process corners fPsN and sPfN. [1]

Leakage Current Replica (LCR) Keeper

Subthreshold is tracked using a replica circuit, and mirrored into the dynamic gate keeper.

The replica current mirror can be shared with all dynamic gates 1 FET overhead/gate Tracks all process corners as well as temperature and VDD.[1] Only random on-die variations are not tracked, but after margining for

these variations, LCR still has an advantage.[1]

Sizing LCR Keeper Wnprl = sf.∑Wni

With sf=1 will hold DN only to same voltage as KPR.

V(KPR) design critical[1]:

too low : poor replica

too high : ΔVtp sensitive sf is selected to be approximately 10, then p1 is

driven to triode region to keep DN close to VDD. Choose long L for p1 and p3 to reduce Vt

variations.[1] The size of p2 isn’t critical as long as it is bigger

than p1. [1]

Selecting a safety factor

Delay Comparison

LCR Keeper is usable for up to 32 legs. sPfN process corner presents the worst-case delay for more than 20 legs

due to replication of the leakage current by the keeper.[1] With 16 to 24 legs LCR is 25 to 40% faster than conventional keeper. [1]

Application to multi-port SRAM 1024 word × 72 bit 3 write / 4 read 3 stage domino read

path Fabricated in 90nm,

1.2V CMOS 1.34mm × 1.31mm sf 6 to 10

The 1024 × 72 3W/4R SRAM block diagram [1]

LCR SRAM single-ended 3-stage domino read path

Cont’d Previous SRAMs in this technology are desinged using high-Vt NFETs in

the dynamic gates but using LCR keeper allowed us to switch to low-Vt NFETs. [1]

Since all read paths are identical only one current mirror is used for the entire SRAM.[1]

2 × minimum length channel is used for p1 and p3 to increase Vtp and reduce its variations.

Simulated access time comparison

The delay from clk to RWD is identical for both circuits because they use identical static logic.[1]

Conclusion A leakage current replica keeper is proposed to improve

scaling of dynamic gates. Overhead is 1-FET per gate plus a portion of the replica

circuit. For equal noise margins, either:

more legs are possible;

gate is faster with the same number of gates. A fairly large safety factor is needed to account for random

on-die process variation especially FET Vt variation.

References [1] Yolin lih, Nestoras Tzartzanis, William W. Walker. “A leakage Current Replica

Keeper for Dynamic Circuits” ISSCC 2006/Session 24/High performance Digital Circuits/24.4

[2] N.H.E. Weste and David Harris, “CMOS VLSI Design. A Circuit and System perspective”. Third Edition, Boston: Addison-Wesley, 2005.

[3] A.Alvandpour et al., “A Conditional Technique for Sub-0.13µm wide Dynamic Gates,” Symp. VLSI Circuits, pp. 29-30, 2001

[4] C. R. Gautheir et al., US Patents #6,914,452 and #6,894,528, 2002.

Thank You