a flash high-precision time-to-digital converter implemented in fpga technology topical workshop on...
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A flash high-precision Time-to-Digital Converter implemented in FPGA technology
Topical Workshop on Electronics for Particle Physics
Paris, 25 September 2009
Paolo Branchini, Salvatore Loffredo
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SummarySummary
Definition and application of a TDC;
TDC’s characteristic parameters;
FPGA (Field Programmable Gate Array) devices;
TDC architectures: fine and coarse structures;
TDC Tester Board;
Conclusions.
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Time interval measurements Time interval measurements
Applications of a TDC in Physics
The flight time of particles; The life time of particles; The decay time of scintillators; Laser range finding; Time of flight mass spectrometry; Time of flight Positron Emission Tomography (TOF - PET).
TDC
Temporal
discriminator
267.83 ns
Detector
Detector
T
START
STOP
Display Physical event
Temporal
discriminator
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Dynamic range: the larger delay that can be measured;
Resolution: the least value of the measured quantity;
Readout speed: how fast the instrument can produce a result;
Differential nonlinearity: deviation of the output bin size from its ideal
value of one least significant bit (LSB);
Integral nonlinearity: deviation of the input/output characteristic and a
straight line of ideal gain (slope) that best fits the curve.
Characteristic parameters of a TDC Characteristic parameters of a TDC
_____
ii _____
LSB -LSBDNL =
LSB
_____
_____1
1ji
ji
LSB LSBINL
M LSB
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FPGA structureFPGA structure
LE LE
IN0
IN1
IN2
IN3
OUT
Slice(0)
Slice(1)
Cin Cin
Cout Cout
Virtex 5CLB
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TDC architectures: fine and coarse structuresTDC architectures: fine and coarse structures
34
TDC
Clock550MHz DCM
CLK90
CLK0
CLK180
CLK270
CLK0
Coarse TDC
Counter
State Machine
START
STOP
Fine TDC Fine TDC6 6
StartRegister
StopRegister
START
STOP
32
2
Subtractor
32
na nb
Nc
Nc [33:2]
Nc [1:0]
CLK180
Sel1[1:0]
32
32
32
CLK0
CLK0
Sel0[1:0]
Sel1[1:0]
CLK90
CLK270
CLK0
CLK180
Sel0[1:0]
CLK90
CLK270
The counter is used in free-running mode. When the START signal transition occurs, the current state of the counter is sampled by the START register, and the same
operation occurs also when the STOP signal is delivered to the TDC. The difference between the STOP and the START register is the coarse measurement of the time
interval.
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The state machineThe state machine
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
clk0 clk90clk180clk270
Ph_out(3) Ph_out(2) Ph_out(1) Ph_out(0)
4
Ph_out
4
Ph_out
State Counter
lsb
clk90clk0
clk180
clk270
STOP
4
Ph_out
clk90clk0
clk180
clk270
STARTPhase Start
register
Phase Stopregister
4
4
encoder
encoder
2
Nc [1:0]Sel0[1:0]
Sel1[1:0]
2
2
Subtractor
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
clk0 clk90clk180clk270
Ph_out(3) Ph_out(2) Ph_out(1) Ph_out(0)
4
Ph_out
4
Ph_out
State Counter
lsb
clk90clk0
clk180
clk270
STOP
4
Ph_out
clk90clk0
clk180
clk270
STARTPhase Start
register
Phase Stopregister
4
4
encoder
encoder
2
Nc [1:0]Sel0[1:0]
Sel1[1:0]
2
2
Subtractor
The state machine samples the START and the STOP signal and detects the phase difference between the START
and STOP rising edges. The least significant bit corresponds to a quarter of
the clock period
Furthermore the state machine is
usefull to the delay line selection of
the fine TDC performed in the carry chain delay line architecture.
The state counter changes the output every quarter of the clock period.
clk0
clk90
clk270
clk180
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1 2 Resolution
Fine structure(1)Fine structure(1)
Carry chain delay line This structure makes use of buffers connected between them by fast lines. The START
signal after each delay unit is sampled by pertaining flip-flop on the rising edge of the STOP signal. This structure have a very short dead time equal to one clock period.
Buffer tobuffer delay
Stop
Start
BBBB
BB
c
D
c
D
c
D
c
D
The fine TDC, for the measurement of the short time intervals has been performend using a flash architecture:
144 69.5 10MAXT N ps ns Max measurable time
1PT N Propagation time of the line
BB
c
DBB
c
D
Stop
Start
Small time interval Large time interval
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Fine structure(2)Fine structure(2)
Start
BBBB
BB
c
D
c
D
c
D
c
D
clk0
BB
c
D
c
D
clk90 clk180
BB c
D
BB c
D
BB c
D
BBBB
c
D
c
D
BB c
D
BB c
D
BB c
D
clk0 clk90 clk180 clk270
Start
clock
BB
c
D
c
D
BBBB
c
D
c
D
BB c
D
BB c
D
BB c
D
BB
c
D
c
D
clk270
BBBB
c
D
c
D
BB c
D
BB c
D
BB c
D
Choosing the right tapped delay lines
The selection of the tapped delay line reflects the phase difference between the Start signal and clk0.
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TDC Tester board (1)TDC Tester board (1)
We designed and built a PCB hosting a Virtex 5 FPGA to test the TDC architecture. On the TDC Tester board, two high stability oscillators have been installed in order to compare their performance.
The first oscillator generates an output frequency of 550 MHz.
The second one provides an output frequency of 250 MHz .
Test points for high bandwidth active probes are used to perform the Virtex 5 clock signal characterization. They are placed just near the FPGA, making the shortest distance for the device output signals.
SMA connectors are used to send the START and STOP signals to the board. They may adopt differential lines or single ended signaling schemes.
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The TDC Tester board is hosted by a VME module which allows us to test and read-out the TDC via a CPU Motorola MVME6100.
TDC Tester board (2)TDC Tester board (2)
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Test set-upTest set-upTo perform our tests we have used an architecture based on an off-shelf CPU board, the Motorola MVME6100. The VME board hosting the TDC Tester daughter card can handle A32/D16 VME cycles and is configured as slave. We have used a DTG5334 as pulse generator in order to deliver to the TDC time intervals up to 20 us with steps better than 1 ps. Since we have operated the DTGM in free running mode an accept signal was delivered by the MVME6100 to the VME slave board in order to start and stop measurements.
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Phase detectingPhase detectingWe executed tests of the phase occupancy of the rising edge of the start and stop
signal within the system clock period. The figure below shows a plot of the hit counts as function of the phase value of the clock period for a 100 ns time
interval measurements. 80000 measurements were made.
clk0
clk90
clk270
clk180
Rising edge of theStart signal
Rising edge of theStart signal
Rising edge of theStart signal
Rising edge of theStart signal
clk0 clk90 clk180 clk270
Ideal phase shifting
Clocksystem
clk0 clk90 clk180 clk270
Real phase shifting (no to scale)
Clocksystem
The START/STOP signals skew towards the clock system of the state machine can be simplified as a clock signals
deviation from the ideal behavior.
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Phase correlationPhase correlation
The correlation between the rising edge of the start and stop signal for
a 100 ns time interval measurements is reported below.
clk0 clk90 clk180 clk270
SystemClock
Phase correlation
0 1 2 3
Stop phase measure
Start
phase
measure
4
STOPSTART STOPStop
delay
line
Start delay line
The plots above are showing the hit
counts as function of the channel number for the
START/STOP carry chain delay lines
coun
ts
coun
ts
channel number channel number
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RMS of the measurementsRMS of the measurementsWe measured time interval up to 20 us and the rms of the
measurements is between 35 ps and 55 ps
RMS of the time interval measurements Multi hit measurements
Time in micro second Time in nanosecond
Co
un
ts
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Non linearity of the measurementsNon linearity of the measurementsThe TDC is linear up to 20 us and we measured the integral and differential
non linearity within the clock period on a 2 ns time interval from 100 ns to 102 ns as function of the TDC output code.
analog input (us)
Digital
output
20 usanalog input (ns) 102 ns100 ns_____
ii _____
LSB -LSBDNL =
LSB
_____
_____1
1ji
ji
LSB LSBINL
M LSB
bini
LSBi
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ConclusionsConclusions
We have measured a time resolution of about 50 ps on every single measurement.
The TDC flash architecture is virtually dead time free.
FPGA electronics technology offers high design flexibility of the TDC
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Back-up slidesBack-up slides
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Nutt’s interpolationNutt’s interpolation
T= (∆t1+ ∆t12- ∆t2)
∆t1 : time interval between the rising edges of the START signal and the next reference clock;
∆t12 : time interval between the two rising edges of the reference clock immediately following the rising edges of the START and the STOP signals;
∆t2 : time interval between the rising edges of the STOP signal and the next reference clock.
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Implementation of the TDC in the Xilinx Implementation of the TDC in the Xilinx XC5VLX50 FPGAXC5VLX50 FPGA
To perform our tests we have used an architecture based on an
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Phase detecting(2)Phase detecting(2)
clk0
clk90
clk270
clk180
Rising edge of the asyncronous signal
Rising edge of theasyncronous signal
Rising edge of theasyncronous signal
Rising edge of the asyncronous signal
clk0
asyncronous signal
D Q
clk
D Q
clk
D Q
clk
D Q
clk
syncronizer
stage
(Virtex 5
Slice)
clk90
D Q
clk
D Q
clk
D Q
clk
D Q
clk
syncronizer
stage
(Virtex 5
Slice)
clk180
D Q
clk
D Q
clk
D Q
clk
D Q
clk
syncronizer
stage
(Virtex 5
Slice)
clk270
D Q
clk
D Q
clk
D Q
clk
D Q
clk
syncronizer
stage
(Virtex 5
Slice)
The measure of the phase occupancy of the rising edge of an asyncronous signal will
depends from the skew of the signal propagating through the syncronizing stages.
q0
q90
q180
q270
HIT
HIT
HIT
HIT phase occupancy
coun
ts
delay
delay
delay
delay
delay
delay
delay
delay
clk0 clk90 clk180 clk270
Real phase shifting (no to scale)
systemclock
The asyncronous signals skew can be simplified as a clock signals
deviation from the ideal behavior.
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Delay line non linearityDelay line non linearity
BBBB
BB
c
D
c
D
c
D
STOP
BB c
D
BB c
D
BB c
D
BB
c
D
BB c
D
BB c
D
BB c
D
START
Virtex 5 slice
Virtex 5 slice
Virtex 5 slice
DELAYLINE
The slice is divided in two substructure made of couple of flip-flop.
454 ps
channel number
co
un
ts
The propagation time of the first and the third buffer inside the slice are so low that:
while the second couple of flip-flop switch often together. The mean propagation time of every buffer of the line is 13 ps.
the first couple of flip-flop switch always together,
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High Stability OscillatorsHigh Stability Oscillators
VFTX140 VFOV200
Features: Features: 550 MHz frequency; LVPECL output levels; 3.3 V supply voltage; Operating temperature
range between 0°C and 70°C ;
Frequency stability vs operating temperature is less than 0.28 ppm;
Frequency stability on overall conditions (including aging 20 years) is less than 4.6 ppm.
250 MHz frequency; HCMOS output levels; 3.3 V supply voltage; Operating temperature
range between -30°C and 70°C ;
Frequency stability vs operating temperature of 10 ppb;
Frequency stability vs supply voltage of 1 ppb;
Frequency stability vs aging/day of 0.5 ppb, aging/year 0.1 ppm.