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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 8, AUGUST 2015 4189

A Family of High-Voltage Gain Single-Phase HybridSwitched-Capacitor PFC Rectifiers

Daniel Flores Cortez and Ivo Barbi, Fellow, IEEE

Abstract—This paper presents the derivation, the analysis, andthe experimentation of a family of unidirectional three-level PFCrectifiers, based on pulse-width-modulated hybrid switched capac-itor principle. The topologies feature reduced voltage stress acrossthe switches, low number of switches, control of the output volt-age, and high-voltage gain without the utilization of transformers.Experimental results for a laboratory prototype of 220 Vrms to1600 Vdc voltages and nominal power of 2500 W are included inthe paper, to validate the theoretical analysis, where the measuredmaximum efficiency reached 97.91%. The proposed converters aresuitable for applications that require rectification with unity powerfactor and high-voltage gain.

Index Terms—High gain, hybrid switched-capacitor converters,power factor correction (PFC), three-level, unidirectional.

I. INTRODUCTION

R ECENTLY, applications requiring dc power supplies withhigh voltage have increased, for both laboratory re-

searches and industry [1], [2]. Converters with these features aredesired in renewable energy systems, X-ray systems, and motordrivers. In many of these applications, the main source is the acgrid and ac–dc conversion requires a high dc-link voltage. It canbe used to feed a load or as input stage to another power supply.The large majority of applications does not require isolation andbidirectional flow, leading to simple and robust unidirectionalsolutions. In the literature, there are a variety of proposals forhigh-voltage gain ac–dc converting, which can be divided intoactive and passive solutions.

Within the passive solutions, converters that have becomepopular are the voltage multipliers, e.g., Cockcroft–Waltonand Dickson converters [3]–[6]. These consist only of diode-capacitor cells and can be cascaded in several stages in order toincrease the voltage gain. Also, this kind of structure has not con-trolled semiconductors, besides having low voltage stress on thecomponents. However, such structures, because they operate atthe frequency of the power grid, present high capacitance, whichincreases the volume and cost. In addition, the current drawnfrom the power grid has a strong harmonic distortion, whichmakes it prohibitive for some applications. Another drawbackis the impossibility of regulating the output voltage, being the

Manuscript received June 26, 2014; revised August 7, 2014; accepted Septem-ber 17, 2014. Date of publication September 24, 2014; date of current versionMarch 5, 2015. This work was supported by the CNPQ, Federal University ofSanta Catarina and INEP. Recommended for publication by Associate Editor B.Singh.

The authors are with the Electrical Engineering Department, Power Electron-ics Institute, Federal University of Santa Catarina, Florianopolis, SC 88040-970,Brazil (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2014.2360173

function of output load and input voltage and, therefore, cannotoperate as a universal power supply.

By contrast, the active PWM solutions could have high powerfactor and excellent regulation of output voltage, independentof output load and input voltage. Typically, PFC operation isperformed by storing and transferring energy from inductors.The need for operation as PFC comes from the imposition ofstrict technical standard, such as IEC 61000-3-2, which enjoinlimit to amplitude of harmonic frequencies produced by thestatic power converter.

With the objective of increasing the voltage gain, activevoltage-doubler or three-level PWM converters are employedbecause they allow the voltage stress in the semiconductors andthe ripple current in the inductor to be reduced [7]–[12]. Addi-tionally, these converters have low conduction and commutationlosses, and high power density [7].

However, the three-level PWM converters present limita-tions concerning the voltage range operation, typically lessthan 1000 V, due to restrictions of commercial components. Forhigher voltages, other solutions must be used, such as converterswith more levels or galvanic isolation. Nonetheless, it increasesthe number of switches, cost, and complexity [13]–[17].

Due to the limitations of voltage multipliers and active con-ventional boost converters, currently the number of topologiesthat combine the output characteristics of the multiplier convert-ers operating at high frequency (switched capacitors) with theinput characteristics of conventional converters (inductive stor-age) has increased. The converters that combine such featuresare referred to as hybrid switched-capacitor converters (HSCC)[18]–[24].

HSCC are attractive because they reduce the voltage stress onthe switches, have a low number of switches and higher voltagegain and do not require isolation [18]. Additionally, they presentlow-ripple current, due to the presence of the inductor, and betteroutput voltage regulation than conventional switched-capacitortopologies. These converters are often proposed in high gaindc–dc conversion [5], [18], [20]–[29]. However, the utilizationof this concept in high gain ac–dc conversion is still unusual,what propitiates opportunities for research [30]–[33].

Due to the limitations of conventional three-level PFC recti-fiers and based on the characteristics of the voltage multiplierconverters, this paper proposes a new family of hybrid switched-capacitor PFC rectifiers with unidirectional flow and three-leveloperation for applications requiring high-voltage gain.

II. PROPOSED CONVERTERS

The family of six hybrid switched-capacitor unidirectionalac–dc converters applied to power factor correction is shown in

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4190 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 8, AUGUST 2015

Fig. 1. Family of six proposed high-voltage gain ac–dc hybrid unidirectional converters.

Fig. 1. The proposed converters are named Type I to Type VI.Every converter is composed of eight to ten diodes, eight ca-pacitors and, depending on the topology, could have one or twopower switches.

The switches of the topologies are represented by insulated-gate bipolar transistors. However, other technologies of semi-conductors, e.g., MOSFET’s can be used.

The main feature of this family is the reduced number ofpower switches to achieve high-voltage gain. It implies reducedlosses and lower number of gate-drivers circuits. The convert-ers preserve the characteristics of the voltage multipliers, i.e.,increased voltage gain. They also have the input characteris-tics of the conventional three-level converters, i.e., input currentcontrol. The capacitors Cj,k , j ∈ {1 . . . 3}, k = A,B does notrequire active control to balance voltage. A comparative analysisbetween proposed converters can be seen in Table I.

Due to the connection with the midpoint 0, the semiconduc-tors are subjected to one-quarter of the dc-link voltage in con-trast to one-half of the full dc-link voltage in typical three-levelrectifiers.

The capacitors Co,A and Co,B are not necessary for the oper-ation of topologies; however, they are inserted to provide a lowimpedance path for 120-Hz ripple in the instantaneous power.These capacitors have very large capacitance compared with thecapacitors Cj,k , j ∈ {1 . . . 3}, k = A,B.

TABLE ICOMPARATIVE EVALUATION OF THE PROPOSED THREE-LEVEL PWM

RECTIFIER SYSTEMS

Features Type I Type II Type III Type IV Type V Type VI

Semiconductors inconduction dutingfirst operation stage

3 4 4 4 3 4

Semiconductors inconduction dutingsecond operationstage

3 3 3 3 3 3

Elements subject toVo /4

all all all 8 8 8

Elements subject toVo /2

0 0 0 2 2 2

Number of fast diode 6 8 8 10 8 8Number of slow

diode2 0 2 0 2 2

A. Operational Stages

Fig. 2 shows the operational stages of the six proposed con-verters. There are two stages, one for storage and another forenergy transfer. In this figure, the inductor Lb and input voltagevg were represented by a current source ig .

The Type I converter is used to illustrate the operation stages;however, the other converters have similar operations. In order

CORTEZ AND BARBI: FAMILY OF HIGH-VOLTAGE GAIN SINGLE-PHASE HYBRID SWITCHED-CAPACITOR PFC RECTIFIERS 4191

Fig. 2. Operational stages of proposed converters: storage and energy transfer.

to simplify the equations, a small resistor rC 3,A is inserted,representing ESR of the capacitor C3,A (see Fig. 3).

The other parasitic resistances are neglected during analysis.The output capacitors Co,A and Co,B can be modeled as

voltage sources.For analysis, it is supposed that converters operate in the

no-charge conduction mode (NC), the definition proposed by[34]. It is assumed that the time constant RC of the circuit ismuch larger than the switching time, Ti , (RC � Ti), i.e., thereis no significant change of current in the capacitors during theswitching time Ti .

The first stage of operation is characterized by the turn ONof the switch S1,A [see Fig. 3(a)]. During this time interval,the inductor Lb stores energy through the input voltage vg . Asthe voltage across the capacitor C1,A is slightly larger than thevoltage over the capacitor C3,A , the diode D2,A conducts trans-ferring energy from C1,A to C3,A . The level 0 V is applied in theswitched terminal a, relative to node o. During the second stage,the switch S1,A is turned OFF and the diodes D1,A and D3,A

start conducting, transferring the energy stored in the inductorto the capacitors C1,A , C2,A and the load. During this time in-terval, the level +Vo/4 is placed on the switched terminal a,relative to node o.

In Fig. 3, it can be observed that all components are sub-mitted to one-fourth of the output voltage, allowing the use oflow-voltage semiconductors. In Fig. 4, the main waveforms ofthe Type I converter, which are valid to the positive half-cycleof the voltage grid are presented. In this figure, the details of theshape current of diode D2,A to three modes, complete charge—CC; partial charge—PC, and no charge—NC are illustrated[34]. It can be seen that PC and NC modes have similar shapes.

B. Steady-State Analysis

The steady-state analysis is focused on the Type I converter;however, it can be extended to other converters. It is consideredthat the converter operates in continuous conduction mode. Onlythe series resistances of the capacitors C3,k , k ∈ {A,B} areconsidered in the analysis. The purely sinusoidal input voltage

(a) (b)

Fig. 3. Operational stages of the Type I converter (a) Storage stage. (b) Trans-fer stage.

vg is assumed constant within one switching period Ts . Also,the input current ig ripple is neglected and dc-link voltage iskept constant, thus it can be represented by a voltage source(see Fig. 3).

Considering that both input voltage vg and input current igare purely sinusoidal, then

vg = Vg,pk · sin(ωt) (1)

ig = Ig,pk · sin(ωt) (2)

where Vg,pk and Ig,pk are the peak voltage and peak currentinput, respectively.

Neglecting the voltage drop across the inductor Lb , the func-tion of duty cycle could be defined as

d = 1 − M · sin(ωt) (3)

where M is the modulation index and equals to

M =4 · Vg,pk

Vo. (4)

Through the operation stages, it can be determined, and aset of equations can be written describing the behavior of the


Fig. 4. Main waveforms of the proposed converter, valid to the half-cycle ofgrid voltage.

currents in all the elements for each operating stage

First operation stage Second operation stage⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

i′C 1,A = −14

(1 − d)d

ig

i′C 2,A =14

(1 − d)d

ig

i′C 3,A = i′D2,A =12

(1 − d)d

ig

i′S1,A =12

(1 + d)d

ig

i′D1,b = ig

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

i′′C 1,A =14ig

i′′C 2,A = −14ig

i′′C 3,A = i′′D3,A =12ig

i′′D1,A =12ig

i′′D1,b = ig .

(5)Based on (5), the current stress and both RMS and average

values in the capacitors and semiconductors can be calculated.These values are determined substituting (5) into (6), as follows:

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

〈Ix〉Ts

avg =1Ts

(∫ dTs

0i′xdt +

∫ Ts

dTs

i′′x dt

)

〈Ix〉Ts

rms =

√1Ts

(∫ dTs

0(i′x)2dt +

∫ Ts

dTs

(i′′x)2dt

)

Ix,avg =12π

∫ π

0〈Ix〉Ts

avg dωt

Ix,avg =√

12π

∫ π

0

(〈Ix〉Ts

rms

)2dωt.

(6)

Table II lists the average current stress in semiconductors,calculated within of the switching period Ts and period of thegrid voltage Tg .

Table III shows the RMS current stress in the capacitors andsemiconductors. The term β is defined as

β =√

1 − M 2 . (7)

TABLE IIAVERAGE VALUE OF THE CURRENTS IN THE SEMICONDUCTORS

Comp. x Average value within Average value withink = A, B Ts (〈Ix 〉T s

av g ) Tg (Ix , av g )

Sj , A ig( 1 + d )

2I g , p k

8( 8−M π )

π

D1 , k ig( 1−d )

2I g , p k

8 .M

D2 , k ig( 1−d )

2I g , p k

8 .M

D3 , k ig( 1−d )

2I g , p k

8 .M

Fig. 5 shows the behavior of the normalized RMS currents,weighted by output current, defined as

Ibase =Po

Vo. (8)

Therefore, Ix = Ix/Ibase , where x represents the element in-volved. The term I∑

,rms represents the sum of RMS currents inthe semiconductors.

C. Inductor Current Ripple

The high-frequency inductor current ripple is directly ex-tracted from the operational stages of the converter.

The envelop of normalized input current through the inductoris determined by

ΔiL,pk-pk = (1 − d) · d (9)

where ΔiL,pk-pk represent the normalized current through theinductor and is defined by

ΔiL,pk-pk = ΔiL,pk-pkVo

4 · Lb · fs. (10)

As in conventional three-level converters, the maximum peakcurrent occurs when ωt = R

{arcsin

( 12M

)}, which leads to

ΔiL,pk-pk = 0.25, M > 0.5. Thus, the inductance value canbe calculated according to

Lb =Vo · Ts

16 · ΔiL,pk-pk. (11)

The (11) is valid to M > 0.5 and to all proposed converters.

D. DC-Link Voltage Ripple

Assuming that the capacitors Cj,k , j ∈ {1 . . . 3}, k = A,B,have low capacitance, then the ripple of dc-link voltage is deter-mined by the output capacitors. Thus, the choice of capacitancevalue of output capacitors Co,i , i ∈ {A,B}, is made accordingto the ripple value. Therefore

ΔvCo=

2 · Po · (Co,A + Co,B )2π · fg · Vo · Co,A · Co,B

(12)

where ΔvCorepresents the ripple across the dc-link voltage.

Each output capacitor has half of the ripple. Therefore

Co,i ≥2 · Po

π · fg · Vo · ΔvC o, i ∈ {A,B}. (13)


TABLE IIIRMS VALUE IN ALL COMPONENTS

Comp. x

k = A, BRMS value within Ts (〈Ix 〉T s

rm s ) Average value within Tg (Ix , rm s )

C1 , ki g4

√( 1−d )

d Ig , p k · 18

√(4 a t a n

(Mβ

)−β (M 2 π + 4 M π + 2 π )+ 2 π

)

√β√

π M

C2 , ki g4

√( 1−d )

d Ig , p k · 18

√(4 a t a n

(Mβ

)−β (M 2 π + 4 M π + 2 π )+ 2 π

)

√β√

π M

C3 , ki g2

√( 1−d )

d Ig , p k · 14

√(4 a t a n

(Mβ

)−β (M 2 π + 4 M π + 2 π )+ 2 π

)

√β√

π M

Sj , A ig( 1−d )

2

√1d Ig , p k

√3

1 2

√(−8 M 3 + 9 π M 2 −1 2 M −6 π )β + 1 2 a t a n

(Mβ

)6 π

M√

π ·√

β

D1 , ki g2

√(1 − d)

√6

6 · Ig , p k

√Mπ

D2 , k ig(d −1 )

2

√1d Ig , p k

√3

1 2

√(−8 M 3 + 3 π M 2 −1 2 M −6 π )β + 1 2 a t a n

(Mβ

)6 π

M√

π ·√

β

D3 , ki g2

√(1 − d)

√6

6 · Ig , p k

√Mπ

III. CONTROL STRATEGY

Suitable PWM control scheme for operation as PFC to pro-posed converters are shown in Fig. 6. Three voltages and onecurrent to obtain a good performance are measured. The in-put voltage vg is used to generate the shape current refer-ence and also to feedforward loop. The partial output voltagesvop and von are measured and processed by the output volt-age loop, it should maintain the dc-link voltage stable. Thecurrent ig is processed by a current loop to ensure the PFCoperation.

Fig. 7 shows the block diagram of the control strategy. Thereference current is generated by the voltage loop, which is re-sponsible for generating a conductance signal that the converterwill emulate, namely gin . This signal, multiplied by input volt-age, will produce the reference current. The input current iscompared with the reference generating an error signal. This er-ror goes through to a controller which, added to the feedforwardsignal, produces the modulation signal m which is synthesizedby the PWM modulator. Also, an output voltage balancing loopis inserted, whose goal is to generate small average values ininput current to ensure that partial output voltages have the sameaverage value.

A. Current-Loop Control

To obtain the current model, it is assumed that all capacitorsdo not have dynamic (large capacitance), such that it can berepresented by a voltage source. Thus, the linear model thatdepicts the modulating signal m with input current ig in thefrequency domain is given by

ig (s)m(s)

=Vo

4 · s · Lb. (14)

Fig. 5. Normalized current stress in capacitors and semiconductors.

B. Voltage-Loop Control

To model the output voltage, it is assumed that capacitorsCo,A and Co,B have much higher capacitance than capacitorsCj,k , j ∈ {1 . . . 3}, k = A,B. These capacitors shall provide alow impedance path to 120 Hz ripples in instantaneous powerand low ripple in dc-link voltage. Given these considerations, thesmall signal model that depicts variations of the output voltagewith the conductance signal is provided by

vo(s)gin(s)

=V 2

g ,pkRo

4Vo

1(sCo ·Ro

2 + 1) (15)

where Co = Co,A ‖ Co,B and Ro is the resistance of the outputload.

In order to validate the mathematical models, in Fig. 8 thebehavior of the output voltage, partial output voltages vop andvon , and input current ig to a step-up in the output voltage


Fig. 6. Control strategy of voltages and input current to PFC operation.

Fig. 7. Control blocks diagram of the input current and output voltage.

Fig. 8. Transient response to step-up in the output voltage reference.

reference from 1600 to 1700 V are presented. For the simulationcapacitors, Cj,k = 60 μF and Co,k = 470 μF, j ∈ {1 . . . 3},k = A,B were employed. One can see an excellent agreementbetween the theoretical model and the simulation results. Thecapacitors Ci,k are much smaller than the output capacitors,

TABLE IVSPECIFICATIONS OF THE PROPOSED CONVERTER

Specification Value Unit

Output Power, Po 2500 WInput Voltage, vg , rm s 220 VOutput Voltage, Vo 1600 VSwitching frequency, fs 90 kHzInductance, Lb 300 μHCapacitance, Ci , k i ∈ {1, .., 3} k ∈ {A, B } 60 μFParasitic resistance, rC 3 , k k ∈ {A, B } 300 mΩCapacitance, Co , k k ∈ {A, B } 470 μF

reducing significantly their influence on the dynamics of theloop voltage. Also, in Fig. 8, it can be seen that the partial out-put voltages vop and von are balanced around half of the outputvoltage.

IV. SIMULATION AND EXPERIMENTAL RESULTS

In order to validate the theoretical analysis and the operationof the proposed three-level ac–dc converters, simulation andexperimental results for the Type I are presented in this sec-tion. The specifications, both simulation and experimentation,are adopted according to Table IV. From the specifications, themagnitude of the output voltage relative to the input voltage, canbe verified where a gain greater than seven times is obtained.Through the output voltage value, it is expected that capaci-tors and semiconductors are subjected to 400 V, resulting in afourfold reduction relative the dc-link voltage.

A. Considerations for the Design of the CommutatedCapacitors Ci,k

During the mathematical analysis, it was considered that theconverter operates in the no charge mode. However, this op-eration mode is physically infeasible, due to it requiring highcapacitance values. For practical implementation, it is desirableto operate the converter in the partial charge mode, since it leadsto a good compromise between peak current and capacitance.It can be demonstrated that the performed analysis of the com-ponent current stress for operation in no charge mode yields toexcellent accuracy also for the partial charge mode, and there-fore, it can be used to design the converter and to predict itsbehavior.

To choose the capacitances of the commutated capacitorsCi,k , it is necessary to take into account the parasitic resis-tances of the circuit. Nevertheless, for the sake of simplicity, inthis paper, only the resistor rC 3 of the capacitor C3 is consid-ered. However, other parasitic resistances, such as the switchresistances, can affect and define the converter operation mode.Small values of parasitic resistance and capacitance not onlyincrease the peak current, during the commutation, but also thelosses in both semiconductors and capacitors. Therefore, onceselected the switching frequency, one should choose a combi-nation of capacitances and parasitic resistances that provide atleast a partial charge mode.


Fig. 9. Simulation results: voltages across capacitors vC i , k; input current,

and switched terminal voltage vao .

From the specifications listed in Table IV, the time constantof the simulation results can be determined. Therefore

RC = rC 3 · C3,i = 300 mΩ · 60 μF = 18 μs >190

kHz.(16)

From (16), it can be verified that the converter operates onthe partial-charge mode.

B. Simulation Results

The simulation results of the voltages across the capaci-tors Ci,A , vCi , A

, i ∈ {1 . . . 3}, input current ig , and switchedterminal voltage vao , are shown in Fig. 9. It can be observedthat the converter processes sinusoidal current, performing theoperation as PFC. Also, the voltage of the switched terminals ofconverter vao , has three distinct levels {+Vo/4, 0 ,−Vo/4}. Inaddition, the ripple voltage of the capacitors around the averagevalue can be seen in the same figure.

The current flowing through capacitors Ci,k and switchesSj,A , i ∈ {1 . . . 3}, k ∈ {A,B}, j ∈ {1, 2} are shown in Fig. 10.The displayed details of the current during one switching cycleare shown, where one can see that the converter operates inpartial charge mode.

C. Experimental Results

In order to verify and validate the introduced concepts, aType I prototype was built with the specifications contained inTable IV.

All diodes SiC technology were employed (IDH16S60C-Infineon) in order to avoid reverse recovery problems in theswitches. The capacitors Ci,k , i ∈ {1 . . . 3}, k ∈ {A,B}, filmcapacitors were employed (B32778G8606k 60uF 800V-Epcos)since they have low resistance and low parasitic inductance,which leads to a good performance in high frequency. The out-put capacitors Co,k electrolytic technologies were already used(B43504-A9477-M 470 uF 450 V). For switches CoolMOStechnology was employed (IPW65R080CFD 650 V-Infineon)because of their low switching losses. The digital signal proces-

Fig. 10. Simulation results: operation of the converter on the rated powercondition: current through switches and capacitors.

Fig. 11. Experimental results: output voltages vop and von (channels 1 and 3);input current grid ig (channel 2) and switched voltage terminal of the convertervao (channel 4).

sor TMS320F28335-DSP Texas instruments was used to imple-ment the control strategy shown in Fig. 6.

The experimental results of the converter operating at ratedcondition are shown in Fig. 11. The waveform of the partialoutput voltages vop and von , input current ig , and switched ter-minal voltage vao are shown. It can be seen that the partialoutput voltages are perfectly balanced around 800 V, provingthat the converter is able to regulate the output voltage. An-other important result is the input current, where it can verifythe operation as PFC. Also, the switched terminal voltage ofthe converter, alternating in the levels +400, 0, and −400 V,are shown, confirming the three-level operation.

The voltage across the capacitors C1,A and C2,A , input cur-rent ig , and switch current on the S2,A are shown in Fig. 12.It is observed that the voltages of the capacitors are equal-ized around 400 V. All semiconductors are subject to thesevoltages, and so, it is important to be equalized. The currentflow through in the switch was measured with the use of aRogowski probe (CWT015 PEM). The measurement of current


Fig. 12. Experimental results: voltages across the capacitors C1 ,A and C2 ,A

(channels 1 and 3); input current ig (channel 2) and current on the switch S2 ,A

(channel 4).

Fig. 13. Transient load response: output voltages (channels 1 and 3), inputcurrent (channel 2) and grid voltage (channel 4).

in switched-capacitor circuits is critical since it cannot insertloops in the circuit, otherwise it can change the parasitic in-ductance and consequently, the operation of the converter. Theprobe used has an inferior widthband of 116 Hz, attenuating thefrequency of 60 Hz present in the current of switch. Because ofthis fact, the current has a low frequency oscillation caused bythe probe (see Fig. 12); however, it may be ignored for analysis.

Fig. 13 shows the behavior of partial and dc-link voltages,input current and voltage grid during a disturbance in the outputload. It can be seen that the voltages after the step-up returns tothe rated value and are equally balanced.

In Fig. 14, the behavior of the voltage across the capacitorsCi,k during a disturbance in the output load is shown. The volt-ages remain balanced and close to the rated value even after thedisturbance. As a consequence, high peak currents are avoidedin the capacitors during the switching, when two capacitors areconnected in parallel.

In order to quantify the losses, tests of efficiency of the pro-posed structure were performed, employing the power analyzerYokogawa WT500. The tests were carried out using the con-

Fig. 14. Transient load response: voltage across capacitors (channels 1, 3, 4)and input current (channel 2).

Fig. 15. Measured efficiency curves for the built prototype with variation ofswitching frequency.

verter operating for various load ranges. To evaluate the powerlosses with the frequency variation, tests were performed at fre-quencies from 50 to 90 kHz in steps of 10 kHz. The efficiencycurves are shown in Fig. 15. In the figure, it can be seen thatthe efficiency increases with decreasing frequency, where themaximum efficiency was 97.91% at 50 kHz. Another importantaspect is that the efficiency curve remains above 96% for theentire load range measurement, which proves the high perfor-mance of this kind of structure.

The curve losses of Type I as a function of output power,for two frequencies, are shown in Fig. 16. One can observethat the losses are represented by quadratic equations, which isdescribed by three coefficients, as proposed by [35].

V. EXTENSION OF THE STAGES AND GENERALIZATION

The proposed family has a diode–capacitor multiplier cellwith four stages. However, this cell can be extended to n stagesso that the voltage gain can be expanded. In Fig. 17, two genericcells with the extension of stages are shown. The cells are namedcell A and cell B. Each cell has a subcell switching, which can bereconfigured generating three converters. The A cell can producethe converters Type I—realization I, Type II—realization II, and


Fig. 16. Measured losses curves to variation of switching frequency.

(a) (b)

Fig. 17. Extension of stages and generalization cells of proposed converters.

Type II—realization III, while the B cell can produce Type IV, V,and VI for n stages.

Studies about the extent of converters with more stages werenot done; however, simulations show that the PFC output andvoltage regulation characteristics are preserved.

VI. CONCLUSION

This paper presented a new family of converters, derived fromthe HSCCs concept, to high-voltage gain application with powerfactor correction. The proposed converters have three-level oper-ation and low number of switches. All switches are subjected toone-fourth of the output voltage, yielding low switching losses.Also, due to the reduced number of semiconductors in the path ofcurrent, the converters have low conduction losses. In addition,the simulation and experimental results show that the family hasinput current with low harmonic distortion and regulated outputvoltage. Through the experimental results, it was shown that thefamily has high efficiency, where it was observed that the Type Ireached maximum efficiency of 97.91%.

In summary, the proposed converters are suitable for unidi-rectional applications where the output voltage must be greaterthan 1000 V, where conventional three-level converters do notexhibit good performance. The proposed family is a solutioninstead of employing passive voltage multipliers and five-levelconverters.

ACKNOWLEDGMENT

The authors would like to thank A. L. S. Pacheco by themanufacturing of the laboratory prototype.

REFERENCES

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Daniel Flores Cortez was born in Pelotas, Brazil, in1985. He received the B.S. degree from the CatholicUniversity of Pelotas-UCPel, Pelotas, Brazil, in 2009,and the M.S. degree from the Federal University ofSanta Catarina, Florianopolis, Brazil, in 2012, bothin electrical engineering. He is currently working to-ward the Ph.D. degree in electrical engineering atthe Power Electronics Institute, Federal University ofSanta Catarina.

His interests include dc/dc bidirectional convert-ers, switched-capacitors, and power factor correction

techniques.

Ivo Barbi (M’78–SM’90–F’11) was born in Gaspar,Brazil, in 1949. He received the B.S. and M.S. de-grees in electrical engineering from the Federal Uni-versity of Santa Catarina, Florianopolis, Brazil, in1973 and 1976, respectively, and the Dr. Ing. degreefrom the Institut National Polytechnique de Toulouse,Toulouse, France, in 1979.

He founded the Brazilian Power Electronics Soci-ety and the Power Electronics Institute, Federal Uni-versity of Santa Catarina, where he is currently aProfessor.

a family of high-voltage gain single-phase hybrid switched … em periódicos... · cortez and...

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