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Presented at Design Automation Conference (DAC) San Francisco, CA, June 4, 2012. Presented by Chuck Cruse A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes

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Page 1: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

Presented at Design Automation Conference (DAC) San Francisco, CA, June 4, 2012. Presented by Chuck Cruse

A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes

Page 2: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

2 LSI Proprietary. © LSI Corporation. All rights reserved.

FPGA Hardware Prototypes Provide §“Real World” exercise of the System

• Closest to Chip Behavior • Interacts with other Physical Devices in Real-Time

§Hardware/Software integration vehicle §Detection and debug of subtle system-level “Real Time” problems (Clock Domain Issues) §Specification verification amongst various compatible products (Plugfest) §Customer demo

Page 3: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

3 LSI Proprietary. © LSI Corporation. All rights reserved.

Overcoming Issues for the FPGA Hardware Prototype

§Must hit a narrow window of opportunity • Delays in the development of the prototype reduce effectiveness

§Visibility of internal signals, while improving, remains a challenge

§Quick turnaround of incremental changes improving, but could be better

Page 4: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

Multi-FPGA Prototyping Flow Example: Cadence Rapid Prototyping Platform

HDL-ICE for fast compile

Partitioning & Board Routing

FPGA P&R

Waveforms of probes (.vcp)

Re-run test for detailed debug

ASIC RTL

© 2011 Cadence Design Systems, Inc. All Rights Reserved. 4

CTEC (optional)

HDL-ICE (optional)

IES (optional)

Verilog, VHDL, SV

• FPGA-aware RTL synthesis • Memory compilation • Probe & trigger insertion

• Clock to enable conversion • Support for complex clocking • Improves FPGA P&R time

Verilog gate-level netlist • QT primitives • FPGA memories

• Multi-FPGA partitioning • Gated clock & latch conversion • Wire-share insertion

• FPGA timing closure • Packing optimization • Hard-macro insertion

• Pre P&R model validation

Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA

Verilog gate-level netlist • QT primitives • 1 netlist for all FPGAs

Bitfiles • 1 file per FPGA

Configuration files Probes & triggers

Page 5: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

5 LSI Proprietary. © LSI Corporation. All rights reserved.

Code Staging and Cross Communication

Page 6: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

6 LSI Proprietary. © LSI Corporation. All rights reserved.

Moving Up the Food-Chain § In the past, FPGA-specific RTL has been simulated in order to demonstrate basic functionality before downloading bitstreams into the lab.

§For the future, the hope is that this approach could be expanded to include Virtual Platforms and Emulation

Page 7: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

7 ��© 2012 Cadence Design Systems, Inc. All rights reserved. CADENCE CONFIDENTIAL - INTERNAL USE ONLY CADENCE CONFIDENTIAL - INTERNAL USE ONLY

Complex Projects Require Many Model Types Need for optimized reuse of existing IP assets

Silicon / hard-macros Test chip, silicon sample

System and I/Os Motherboard, PCIE, USB

High-level models C or SystemC

Instrumentations Assertions, monitors, checkers

RTL models Verilog, VHDL, SystemVerilog

Page 8: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

8 LSI Proprietary. © LSI Corporation. All rights reserved.

Virtual Platforms for Emulation and FPGA

§System-Level Virtual Platform Modeling • Early HW/SW Integration

- Pre-RTL mutual reinforcement of HW & SW - Reduce “Big-Bang” - Integration Surprises

• Architectural Benefits - “What-If” scenarios can be tried at high level - Bring .pdf “to life” - Reduce EDS/RTL Mismatches

Page 9: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

9 LSI Proprietary. © LSI Corporation. All rights reserved.

Virtual Platform Goals § Deterministic Approach – Avoid “surprises” in integration/development

§ Leverage Virtual Platform and Emulation to create FPGA Hardware Prototype

§ Retain the benefits of software simulation

• Cycle-accuracy may suffer, but emulation and the hardware prototype will catch these issues

§ Begin hardware/software integration very early in the development process

§ Hardware/Software Integration should be more transparent when “crossing

over” from the virtual world to the hardware prototype • Emulation/HW Prototypes always result in a “step function” effort • “Step function” problem should be reduced when the virtual platform is

incorporated into the flow

Page 10: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

10 LSI Proprietary. © LSI Corporation. All rights reserved.

SCE-MI Open Standard for Virtual Platform and FPGA § Several Serial Protocols could be expected to serve as a vehicle for SCE-MI

transactions • PCIe • Altera SerialLite II • Xilinx Aurora • SAS/SATA

§OSCI and Accellera Merge

• OSCI chair Eric Lish and Accellera chair Shishpal Rawat sign merger documents to create Accellera Systems Initiative*

• This validates a SCE-MI and SystemC approach to FPGA and Virtual Platform development with a rich and developing set of open standards

* http://www.accellera.org/about

Page 11: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

PCIe Interface Kit Flexible, scalable 1 – 4 lanes

© 2011 Cadence Design Systems, Inc. All Rights Reserved. 11

Page 12: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

Evolving System Development And Verification

OPEN • Compatible with standard SW debuggers • Support for standard interfaces

CONNECTED • Multi platform compile compatibility • SpeedBridge Adapters

SCALABLE • Multiple hardware configurations • Easy transition from emulation

CLOSED • Single-vendor point solutions • Proprietary

FRAGMENTED • Niche offerings • Unconnected

LIMITED • Single level of abstraction • Block-to-system migration issues

Then Now

© 2011 Cadence Design Systems, Inc. All Rights Reserved. 12

Page 13: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

13 LSI Proprietary. © LSI Corporation. All rights reserved.

End-Of-Day Benefits

§Reduced spins of the design §Much faster chip-evaluation when silicon arrives

• Software ready to go • Integration/System-Engineering team already up to speed on the

device §Effective widening of the pre-silicon testing window

Page 14: A Deterministic Flow - DeepChip• Hard-macro insertion • Pre P&R model validation Verilog gate-level netlist(s) • FPGA primitives • 1 netlist per FPGA Verilog gate-level netlist

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