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Real World FPGA design with Verilog Miloš Milovanović miloshm @yahoo.com Jovan Popović josars @ galeb . etf . bg .ac. yu Veljko Milutinović vm @ etf . bg .ac. yu

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Real World FPGA design with Verilog. Milo š Milovanović [email protected] Jovan Popović [email protected] Veljko Milutinović [email protected]. Literature. - Real World FPGA Design with Verilog by Ken Coffman, Prentice Hall PTR - On-line Verilog HDL Quick Reference Guide - PowerPoint PPT Presentation

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Page 1: Real World FPGA design with Verilog

Real World FPGA design

with Verilog

Miloš Milovanović[email protected]

Jovan Popović[email protected]

Veljko Milutinović[email protected]

mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
Page 2: Real World FPGA design with Verilog

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Literature- Real World FPGA Design with Verilog by Ken Coffman, Prentice Hall PTR

- On-line Verilog HDL Quick Reference Guide

by Stuart Sutherland titan.etf.bg.ac.yu/~gvozden/VLSI/

Miloš Milovanović/75

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Field Programmable Gate Array design

Verilog – designed as a simulation and test language

Real World - &¨!¸!!”#$%&@#$%

/75Miloš Milovanović

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A day in the life of an FPGA Silicon Designer

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Design must be: Understandable to other designers

Logically correct

Perform under worst-case conditions of temperature and process variation

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Design must be: Reliable

Testable and can be proven to meet the specification

Do not exceed the power consumption goals

(a battery-operated circuit)Miloš Milovanović

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Understandable Design

Miloš Milovanović /75

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FPGA Architecture

Miloš Milovanović/75

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Xilinx 4K Family CLB Architecture

Miloš Milovanović/75

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Trivial Overheat Detector Example

Miloš Milovanović

“Big Brother” [email protected]

[email protected]

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Solution:

Miloš Milovanović/75

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Simulation

Miloš Milovanović/75

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Assignments Concurrent

Initial: A=B=C=E=1

A <= B + C;D <= A + E;

After assignment:A=2, D=2

Sequential

Initial: A=B=C=E=1

A = B + C;D = A + E;

After assignment:A=2, D=3

Miloš Milovanović/75

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Module – the building block

module module_name (port_name, port_name, ... );

module_itemsendmodule

module module_name (.port_name (signal_name ), .port_name (signal_name ), ... );

module_itemsendmodule

Miloš Milovanović/75

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Module Port Declarationsport_direction [port_size] port_name,

port_name, ... ;

port_direction – input, output, inoutport_size is a range from [ msb : lsb ]

Example1: Example2:parameter word = 32; input [15:12] addr;input [word-1:0] addr;

Miloš Milovanović/75

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Data Type Declarations 1register_type [size] variable_name ,

variable_name , ... ;register_type [size] memory_name [array_size];

register_type:reg - unsigned variable of any bit sizeinteger - signed 32-bit variabletime - unsigned 64-bit variablereal or realtime - double-precision floating point variable

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Data Type Declarations 2

net_type [size] #(delay) net_name , net_name , ... ;

net_type: wire or tri - Simple Interconnecting Wirewor or trior - Wired outputs OR together

wand or triand - Wired outputs AND togetherMiloš Milovanović

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Data Type Declarations 3#delay or #(delay) - Single delay for all output transitions

#(delay, delay) - Separate delays for (rising, falling) transitions

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Data Type Declarations 4- wire a, b, c; - tri [7:0] data_bus; - reg [1:8] result; // an 8-bit // unsigned variable - reg [7:0] RAM [0:1023];

8-bits wide, with 1K of addresses- wire #(2.4,1.8) carry;a net with rise, fall

delays

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Assign statement Continuous (combinational) logic

- net_type [size] net_name;assign #(delay) net_name = expression;

- net_type [size] net_name = expression;

assign out = in1 & in2; assign bidir = OE ? out : 1’bz;

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Procedural Blocks

type_of_block @(sensitivity_list) statement_group: group_name local_variable_declarations

timing_control procedural_statements end_of_statement_group

Miloš Milovanović/75

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Type of block

initial – process statements one time

always – process statements repeatedly

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Sensitivity list OPTIONAL Signals Posedge – rising-edge triggered Negedge – falling-edge triggered

example:always @ (posedge clk or posedge rst)begin … end

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Statement group

begin – end – the sequential block

fork – join – statements are evaluated concurrently

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Exampleinitial

fork #10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA;

join

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Examplealways

begin#10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA;

end

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1

Miloš Milovanović

Example

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Verilog Hierarchymodule_name

instance_name(port_list);

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Named & Positional Assignment

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Built-in Logic Primitives and, or, nand, nor, xor, nxor bufif0, bufif1, notif0, notif1

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Latches and Flipflops Clocked D flipflop

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Basic Latch

Miloš Milovanović/75

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test_out2 <= 0;

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Blocking and Nonblocking Assignments

Miloš Milovanović /75

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Blocking assignmentsare order sensitive

Miloš Milovanović/75

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Nonblocking Assignment

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Miscellaneous Verilog Syntax Items

Numbers

- default: 32 bits wide- size’base value- underscore is legal- X is undefined- Z is the high impedance

Miloš Milovanović/75

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Number examples

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Forms of Negation

! – logical negation

~ - bitwise negation

Miloš Milovanović/75

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Forms of AND & is a bitwise AND

&& is a logical AND (true/false)

Miloš Milovanović/75

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Forms of OR | is a bitwise OR

|| is a logical OR (true/false)

Miloš Milovanović/75

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AND/OR examlpe

Miloš Milovanović/75

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Equality Operators == is logical equalityhave an unknown (x) result if any of the compared bits are x or z

=== is case equalitylooks for exact match of bits

including x’s and z’s and return only true or false

Miloš Milovanović/75

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Not equal operators

!= opposite to ==

!== opposite to ===

Miloš Milovanović/75

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Also supported greater than (>)

less than (<)

greater than or equal (>=)

less than or equal (<=)Miloš Milovanović

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Shift operators

>> n – right shift (divide by 2n)

<< n – left shift (multiple by 2n)

Operating on a value which contains an x or z

gives an x result in all bit positions.Miloš Milovanović

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Shift operations example

Miloš Milovanović/75

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Conditional Operator

out <= expression ? true_assignment : false_assignment;

- Special case: expression = x or z calculates every single bit

Miloš Milovanović/75

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Math Operatorsaddition (+), subtraction (-), multiplication (*), division (/), modulus (%)

synthesis tool probably limits multiplication and division to constant powers of two

verilog assumes all reg and wire variables are unsigned

Miloš Milovanović/75

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Parameters used in modules where they are

defined

can be changed by higher-level modules

cannot be changed at run timeMiloš Milovanović

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Concatenations

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Programming Statementsif, casecasez, casexforever, repeat(number), while, for

initial begin clk = 0; #1000 forever #25 clk = ~clk;

end

Miloš Milovanović /75

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Testing…Compiler directives:

‘define, ‘ifdef, ‘else, ‘endif, ‘undef

‘include

‘timescale unit/precision example: ‘timescale 1ns/0.5ns

/75Miloš Milovanović

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System Tasks starts with $

$finish – terminate

$stop – (time out)

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System Tasks $display(format, vars…) - printf

$write(format, vars…) - $display + ‘\n’

$timeformat

$time

/75Miloš Milovanović

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System Tasks $monitor (signal list and formatting)

$monitoron

$monitoroff

/75Miloš Milovanović

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System Tasks$dumpfile(“filename”)

$dumpvars

$dumpall

$dumpvars(…)

$dumplimit(size)

/75Miloš Milovanović

Page 73: Real World FPGA design with Verilog

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System Tasks

$readmemh(“filename”, memory_name)

$readmemb(“filename”, memory_name)

/75Miloš Milovanović

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Watch for those alligators!

/75Miloš Milovanović

Page 75: Real World FPGA design with Verilog

Real World FPGA design

with Verilog

Miloš Milovanović[email protected]

Jovan Popović[email protected]

Veljko Milutinović[email protected]


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