a comprehensive method for the evaluation of the sensitivity to seus of fpga-based applications a...
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A comprehensive method for the evaluation of the sensitivity to SEUs of FPGA-based applications
A comprehensive method for the evaluation of the sensitivity to SEUs of FPGA-based applications
R. Velazco ([email protected]), F. Faure ([email protected]).
TIMA-QLF
G. Swift ([email protected])
JPL-NASA
April, 25th 2002
MotivationsMotivations
FPGAs offer the space community significant advantages over discrete logic:
Reduced weight and board space due to decrease in number of devices required.
In flight reconfiguration.
Improved reliability with reduced solder connections.
Increased flexibility to make design changes after board layout
is complete.
Problems when using FPGAs in space environment
Problems when using FPGAs in space environment
FPGA-based applications are sensitive to SEUs (internal flip-flops,…).
Problem not only encountered by FPGA. All circuits are sensitive !
SRAM-based FPGA might have their configuration altered by radiation.
Solutions exist (Partial or Total reconfiguration, TMR).
FPGA Logic may be sensitive to transient errors
Smart Clocking strategies can reduce this problem
FPGAs are suitable for space applications.
Need for qualifying them under radiation.
Analysis of the behavior of a given FPGA-based design (1)
Analysis of the behavior of a given FPGA-based design (1)
Chosen design : A scalar product state machine•Clocked implementation•a 8-bit adder•a 16-bit multiplier•a MMU (Access to SRAM memory for load/store operation)
Q
D
Clk
Analysis of the behavior of a given FPGA-based design (2)
Definitions
Analysis of the behavior of a given FPGA-based design (2)
Definitions
For a given flip-flop :•If D=1 & Q =1, state is S11, X-section is 11 •If D=0 & Q =0, state is S00 , X-section is 00 •If D=0 & Q =1, state is S01 , X-section is 01 •If D=1 & Q =0, state is S10 , X-section is 10
DFF
Clk
D Q
Analysis of the behavior of a given FPGA-based design (3)
Analysis of the behavior of a given FPGA-based design (3)
Conclusion : A given design doesn’t have the same X-section during its activity cycle !
53%
1%
0%
46%STATE 00
STATE 01
STATE 10
STATE 11
Internal flip-flops duty cycle (Simulation results)
Measuring the X-section : the “usual way” (1)Measuring the X-section : the “usual way” (1)
Shift Register Ring Counter
Upset !
Measuring the X-section : the “usual way” (2)Measuring the X-section : the “usual way” (2)
Advantage:• Easy to set-up
Drawbacks:• Mix of 3 sensitivities at the same time:
• Configuration : Connection routing• Logic : Internal connections go through logic blocks • Memory : Internal flip-flops
• Because of the clocked strategy, difficulty to capture transient errors• No information about the 4 different X-sections
Proposed Method – A case study(1)Proposed Method – A case study(1)
Target FPGA : MAX7000 from Altera
Features :•3.3V EEPROM based PLD•5000 gates•256 Macrocells•164 User I/O pins
Proposed Method – A case study(2)MAX7000 Block view
Proposed Method – A case study(2)MAX7000 Block view
Global Inputs
I/OPins
Macrocell:Logic + flip-flop
Internal signals “highway”
Proposed Method – A case study(2)Internal flip-flops test (a)
Proposed Method – A case study(2)Internal flip-flops test (a)
Global Input
MAX7000 Macrocell
Proposed Method – A case study(2)Internal flip-flops test (b)
Proposed Method – A case study(2)Internal flip-flops test (b)
•Using Global Signals reduces the amount of internal connections, thus the configuration bits inside the FPGA•Using the global clock as an enable make the design asynchronous,the flip-flop state is totally controlled. Measure of 00, 01, 10 and 11 is possible•If an upset occurs, and after a rewrite the value is still false, a configuration upset (on the routing) is recorded.
Proposed Method – A case study(3)Hardware Set-up
Proposed Method – A case study(3)Hardware Set-up
FPGA Under TEST
MonitoringFPGA
Same Hardware set-up for the test of :•flip-flops, •logic,•configuration.
I/O
Deriving the error rate of an FPGA-based design (1)
Deriving the error rate of an FPGA-based design (1)
Radiation Tests.
Data obtained :11
00
01
10
Simulation.
Data obtained:D11 : Duty cycle in S11
D00 : Duty cycle in S00
D01 : Duty cycle in S01
D10 : Duty cycle in S10
injection = (# of errors) / (# of injected upset).
Deriving the error rate of an FPGA-based design (2)
Deriving the error rate of an FPGA-based design (2)
underlying = (11* D11)+(00* D00)+ (01*D01)+(10*D10)
The underlying cross-section of the application is :
Finally, the estimated error rate is :
estimated = underlying * injection
ConclusionsConclusions
Work in progress :•Radiations testing scheduled mid May•A dedicated FPGA tester is in the design phase•Estimation & measures for a complex FPGA (Xilinx)
Future work :•A flexible software tool for fault injection and duty cycle computation
Proposed Method – A case study(3)Internal Logic test (a)
Proposed Method – A case study(3)Internal Logic test (a)
Global Inputs
Proposed Method – A case study(3)Internal Logic test (b)
Proposed Method – A case study(3)Internal Logic test (b)
•No Clock•If an output has a transient false value, an transient error is recorded.•If an output has a persistent false value, a configuration upset is recorded