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4.2.1EOS/ESD SYMPOSIUM 95-175
A Comparison of Electrostatic Discharge Models and Failure Signaturesfor CMOS Integrated Circuit Devices
M. KellyDelco Electronics Corporation
1800 E. Lincoln Road, M/S R117Kokomo, Indiana 46904-9005
(317) 451-7084
T. DiepAT&T Bell Laboratories
Engineering Research CenterP.O. Box 900
Princeton, New Jersey 08542(609) 639-2412
S. TwerefourFord Microelectronics, Inc.
9965 Federal DriveColorado Springs, Colorado 80921
(719) 528-7709
G. ServaisDelco Electronics Corporation
1800 E. Lincoln Road, M/S R117Kokomo, Indiana 46904-9005
(317) 451-7923
D. LinAT&T Bell Laboratories
Engineering Research CenterP.O. Box 900
Princeton, New Jersey 08542(609) 639-2414
G. ShahFord Motor Company, ACD, Electronics Operations
17000 Rotunda Drive, Room C160Dearborn, Michigan 48121
(313) 845-3599
ABSTRACT
Six different CMOS device codes were evaluated,according to available test standards, for ElectrostaticDischarge (ESD) sensitivity using three ESD models:
Human Body Model (HBM) Machine Model (MM) Field-Induced Charged Device Model (FCDM)
Four commercially available simulators were used: two toperform the HBM ESD evaluations and two to perform the MMESD evaluations. FCDM stressing was performed using anAT&T designed simulator. All stressing was performed atAT&T Bell Laboratories, Delco Electronics, and FordMicroelectronics. The failure threshold voltage and failuresignature associated with each ESD model and simulator weredetermined for each test sample. Threshold correlation andregression analyses were also performed.
Though the three ESD models and simulators createdmultiple failure signatures, they do not exhibit a high degree ofoverlap. Our results will show a high correlation between theESD thresholds, failing pins, failing circuitry, and failingstructures for HBM and MM stressing of the device codesevaluated.
INTRODUCTION
Over the past several years, ESD models haveproliferated as Integrated Circuit (IC) users and manufacturersendeavor to predict IC performance in applicationenvironments. The test techniques being implemented havegrown more complex as a myriad of test-pin combinations
have been specified to guarantee device performance duringproduction and field use. These complex requirements haveresulted in: difficulty measuring ESD sensitivity; a need forlarge sample sizes; an uncertainty when correlating differentsimulators or facilities; and, because ESD stressing isconsidered a destructive test, a significant increase in cost ofqualification.
Several papers have been published in the past few yearsexploring potential correlation between HBM / MM [1,2] andHBM / CDM [3,4,5]. However, an overall comparison of thethree ESD models and the corresponding failure signatures forvarious CMOS technologies has not been reported to date.
In addition, the ESD sensitivity comparisons of previousinvestigations [1,2,3,4] were conducted to evaluate the effectof individual pin combinations or utilized a threshold definitionof the 50% value for the cumulative probability plot. Theseprocedures are not a representation of procedures followed byqualification engineers. The majority of qualification engineersdetermine test failures according to the failure criteriadefinition specified in industry test specifications. We haveinvestigated the correlation between several ESD models fromthe practical standpoint of an individual tasked with performingan ESD qualification test. However, to assess the robustnessof our analysis, we have also performed two additional sets ofcorrelation analysis utilizing a 50% value and a first-fail value.In later sections of this paper, these results will be discussedshowing that the correlation big picture is robust.
This paper discusses the results of a round-robin ESDexperiment performed jointly by AT&T Bell Laboratories, DelcoElectronics, and Ford Microelectronics. To minimize thenumber of ESD models required to provide a reasonablyaccurate prediction on the ESD susceptibility of an integrated
4.2.2EOS/ESD SYMPOSIUM 95-176
circuit, the investigation examined the correlation betweenthree ESD models used by the electronics industry: HumanBody Model (HBM), Machine Model (MM), and Field-InducedCharged Device Model (FCDM). The designed experimentcontained two independent variables:
i) Two different test systems performed HBM and MMstressing and one test system performed FCDMstressing.
ii) A total of six different CMOS devices were evaluated,with each participating company providing two devicecodes.
The testing approach attempted to quantify the failingESD voltage level for each ESD model through execution oftesting procedures defined in commonly used test standards.Once all ESD stressing was completed, resulting failuresignatures and failure locations were identified. Optical andScanning Electron Microscope (SEM) photographs areincluded to illustrate typical failure characteristics for eachESD model. The observed physical characteristics of theHBM, MM, and FCDM failures at various voltage levelsprovide a valuable reference tool for the failure analyst taskedwith classifying a transient event resulting in ESD failure.
SELECTION OF TEST SAMPLES
To represent as many component CMOS technologiesand packaging configurations as possible, each participatingcompany provided two device codes of various pin counts forcomplete ESD characterization. Table 1 lists the deviceschosen for the evaluation and the corresponding technology,packaging configuration, and functional description. Thesedevices represent components used in the real world.
Table 1: Devices used in round-robin experiment
Device PackageType
Technology Description
X1 44 PLCC 0.9 m3 volt / 5 volt CMOS
Echo cancellor
X2 100 EIAJ 0.9 m5 volt CMOS
ASIC for diskdrive system
X3 40 PDIP 1.5 m5 volt CMOS
Audioapplications
X4 28 PLCC 1.5 m5 volt CMOS
Bus interface forcommunication
and data
X5 28 PDIP 1.2 m5 volt CMOS
Controls modulecommunications
for vehicle
X6 24 PDIP 1.5 m5 volt CMOS
2K x 8 bit staticRAM
TEST EQUIPMENT AND PROCEDURE
The Human Body Model is designed to simulate a humanbody discharging accumulated static charge (via a fingertip)through a device to ground (see Fig. 1). It comprises a seriesRC network of a 100 pF capacitor and a 1500 resistor [6,7].
I
Time (ns)
t
Cur
rent
(Am
ps)
0 100ns
0.33
0
Figure 1: 500 volt HBM ESD discharge waveform through ashort (for waveform details, see [6,7]).
The Machine Model is designed to simulate a machine(test equipment, furniture, etc.) discharging accumulated staticcharge through a device to ground (see Fig. 2). It comprises aseries RC network of a 200 pF capacitor, a resistor ofapproximately 8.5 , and an inductor of approximately 0.5 H[8].
Time (ns)t
I
Cur
rent
(Am
ps)
0 100ns
8.75
0
Figure 2: 500 volt MM ESD discharge waveform through ashort (for waveform details, see [8]).
The Charged Device Model, on the other hand, simulatesa charged device (e.g., sliding down a shipping tube, etc.)discharging directly to ground (see Fig. 3) [9,10,11].
4.2.3EOS/ESD SYMPOSIUM 95-177
Time (ns)
IC
urre
nt (
Am
ps)
t0 5ns
0
4.5
Figure 3: 500 volt FCDM ESD discharge waveform using a4 pF module (for waveform details, see [11]).
All Human Body Model (HBM) and Machine Model (MM)ESD stressing was performed using two different commerciallyavailable ESD simulators and Field-Induced Charged DeviceModel (FCDM) ESD stressing was performed using an AT&Tdesigned simulator [12,13]. To insure proper simulation andrepeatable ESD results, simulator waveform performance wasverified following the procedure outlined in the ESDAssociation HBM and MM ESD specifications [6,8] and theJEDEC FCDM ESD specification [11]. Based upon familiaritywith the CDM event and characterization procedure, AT&T BellLaboratories performed all FCDM stressing. FordMicroelectronics and Delco Electronics, both automotiveelectronics users and manufacturers, performed all HBM andMM ESD stressing.
Prior to ESD characterizations, complete DC parametricand functional testing per applicable device specificationrequirements was performed on all test samples. For HBMand MM stressing, all pins on each device were subjected toESD stressing with three positive and three negative pulseswith a one second delay between each pulse. Devicestressing was accomplished following the pin combinationcriteria outlined in the ESD Association HBM and MM ESDspecifications [6,8]. For FCDM stressing, each pin wasstressed with three positive and three negative pulses with atleast 0.1 second delay between pulses, following theprocedure outlined in the JEDEC FCDM ESD specification[11].
The stress voltage levels for each ESD model wereselected based on prior experience with the devices and areshown in Table 2. For devices X1 and X2, a step-stressprocedure was used on a sample of three available devicesper device code. For devices X3 through X6, a new sample ofthree devices was used at each stress voltage level to avoidany cumulative effect due to the ESD stressing itself [14]. Atotal of 933 devices were stressed for this study. Once thestressing was completed, all devices were returned to theoriginating company for complete DC parametric andfunctional testing per applicable device specificationrequirements. Devices failing the electrical testing criteriawere then submitted for failure analysis.
ELECTRICAL RESULTS
To insure an ac