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Modern Traffic and Transportation Engineering Research MTTER
MTTER Volume 2, Issue 2 April 2013 PP. 95-102 www.vkingpub.com ©American V-King Scientific Publishing
95
A Comparative Study of IEEE 802.11p Physical
Layer Coding Schemes and FPGA Implementation
for Inter Vehicle Communications George Kiokes 1, George Economakos 2, Angelos Amditis 3, Nikolaos K. Uzunoglu 4
1 Department of Electronics, Electric power, Telecommunications, Hellenic Air-Force Academy 2 School of Electrical and Computer Engineering, National Technical University of Athens, Microprocessors and Digital
Systems Lab 3 Institute of Communication and Computer Systems (ICCS), National Technical University of Athens, I-SENSE Group 4 School of Electrical and Computer Engineering, National Technical University of Athens, Microwaves and Optics Lab
Athens, Greece 1 [email protected]; 2
Abstract- This paper provides a comprehensive investigation of
the performance and practical implementation issues of two
coding schemes, employing Concatenated Reed Solomon Codes
with Convolutional Codes and Turbo Codes, over vehicular
ad-hoc networks based on the IEEE 802.11p specifications. In
this article we present the results of an evaluation of system
performance using simulation for the two different coding
schemes. We concentrate our evaluation on different
propagation conditions (Additive white Gaussian noise–AWGN,
Ricean Fading and Rayleigh Fading). BER (Bit Error Rate) and
SNR (Signal to Noise Ratio) for different data rates are
examined and tested. The Turbo coding scheme achieves
significant performance improvements compared to the other
technique. The Forward Error Correction (FEC) system model
in the transmitter and the receiver with the two schemes has
been implemented in a Field Programmable Gate Array (FPGA)
from Xilinx using the System Generator tool-flow for fast
prototyping. At the end, a test-bed was developed using the
Nallatech XtremeDsp Development Kit with a Xilinx Virtex-4
FPGA, for comparing simulation results with real time
implementations. The overall conclusion of this paper is that
Turbo Codes offer considerably improved performance with
low hardware complexity to the 802.11p standard, directly
applicable to the Intelligent Transport System (ITS) domain.
Keywords- Turbo Codes; Reed Solomon Codes; FEC; FPGA
I. INTRODUCTION
Effective use of an ITS cannot only improve vehicular
safety but also enhance the efficiency of current transport
systems and driving comfort. Dedicated short-range
communications (DSRC) system is a critical component of
ITS for the future transport telematic services. This demand
leads to wireless access for vehicular environments
(WAVE), which is also regulated by the IEEE 802.11p
standard [1], [2]. In American Society for Testing and
Materials (ASTM) 2213-03 standard [3], IEEE 802.11 and
802.11a are modified as a medium access control (MAC)
and physical layer (PHY) specifications, respectively, for
the DSRC system.
In 1949, Claude Shannon developed a result that has
become one of the fundamental theorems of coding theory.
In his analysis he quantified the maximum theoretical
capacity for a communications channel, the Shannon limit,
and indicated that error-correcting channel codes must exist
that allowed this maximum capacity to be achieved. In [4]
Irving Reed and Gus Solomon published a paper which
describes a new class of error-correcting codes that are now
called Reed-Solomon (RS) codes. RS codes are the most
popular class of block codes [5]. In today‟s systems,
convolutional codes are the most widely used channel codes.
They owe their popularity to good performance and
flexibility to achieve different coding rates. Block codes are
different from convolutional codes in the sense that the code
has a definite code word length n, instead of a variable code
word length. Another important difference between block
codes and convolutional codes is that block codes are
designed using algebraic properties of polynomials or
curves over finite fields, whereas convolutional codes are
designed using exhaustive computer searches. Concatenated
codes are built by combining an outer code and an inner
code. The outer code is usually a Reed-Solomon block code
and the inner code a convolutional code. In 1993 Berrou,
Glavieux and Thitimajshima [6] proposed “a new class of
convolution codes called turbo codes whose performance in
terms of Bit Error Rate (BER) are close to the Shannon
limit”. The authors described an approach to coding that, in
their supporting analysis, indicated that it was possible to
operate within 0.7dB of the Shannon limit.
IEEE 802.11p Physical Layer (PHY) is designed for
operating at high user mobility (vehicular communication)
and aims at communication distances of up to 1000 m. The
standard intends to support road transport, traffic
applications and public safety over roadside and high-speed
mobile units, or between high-speed vehicles. It is a
variation of the IEEE 802.11a standard, which is based on
the OFDM (Orthogonal Frequency Division Modulation)
technique. At first, the standard was designed for Vehicle to
Infrastructure (V2I) systems but it was market demand that
has caused the adaption with the Vehicle to Vehicle (V2V)
communications systems.
The performance analysis of the 802.11p standard has
been extensively studied in the literature [7], [8], [9] [10].
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For instance, in [7] the authors conduct a feasibility study of
delay-critical safety applications over vehicular ad hoc
networks based on the emerging DSRC standard. They
came to the conclusion that DSRC achieves promising
latency performance, yet the throughput performance needs
further improvement. In a similar simulation study [10], the
authors present simulation results which reveal that the
802.11p system can efficiently mitigate inter-symbol
interference and inter-carrier interference introduced by
multi-path delay spread in the high mobility environment,
but against frequency selective fading BER values are
increased. To overcome this problem, the authors propose a
different value of the guard interval (3, 2 μs).
This paper provides another way improving the
performance of the system. More specifically, a
comprehensive investigation of the performance for two
different coding schemes (concatenated Reed-Solomon/
Convolutional codes and Turbo codes) over vehicular
ad-hoc networks and practical implementation issues are
presented.
Through the remaining sections, presentation is
organized as follows: First, the architecture of the
implemented system is described. Following that, the coding
techniques are analyzed and presented. Furthermore,
simulation results achieved by using different coding
schemes for physical layer performance estimation are given,
in terms of Bit Error Rate (BER) versus Signal-to-Noise
Ratio (Eb/No). Next, the FEC system model in the
transmitter with the two coding schemes is implemented in a
Field Programmable Gate Array (FPGA) from Xilinx using
the System Generator tool-flow and comparative figures of
the corresponding implementation requirements are reported.
Finally, a comparison between simulation results and real
time implementations is given, offering quantitative
evaluation of the proposed approach.
II. IEEE 802.11P SYSTEM ARCHITECTURE
The IEEE 802.11p standard specifies an OFDM physical
layer that employs 64 subcarriers. OFDM separates the
usable bandwidth, typically 10-20 MHz, into 52 orthogonal
sub-channels or subcarriers at different frequencies. 48
subcarrier frequencies are used for data transmission and
four subcarrier frequencies are used for pilot transmission to
provide overall data transmission at 3, 4.5, 6, 9, 12, 18, 24,
or 27 Mbps. Support for transmitting and receiving data
rates at 3, 6, and 12 Mb/s is mandatory. The 52 subcarriers
are modulated using Binary or Quadrature Phase Shift
Keying (BPSK or QPSK), or using Quadrature Amplitude
Modulation (16QAM or 64QAM). Forward error correction
coding (convolutional coding) is used with a coding rate of
1/2, 2/3, or 3/4.
The mobile radio channel places fundamental limitations
on the performance of mobile communications systems. The
transmission path between transmitter and receiver can vary
from a simple clear path to one that is severely obstructed
by buildings, mountains etc. The radio channel of a wireless
communication system is often described as being either
LOS (line of sight) path or NLOS (no line of sight) path. In
a LOS link, a signal travels over a direct and a
ground-reflected propagation path from the transmitter to
the receiver. A LOS link requires that most of the first
Fresnel zone is free of any obstruction. The two-ray path
model is ideal to represents the LOS path since it is based
on geometric optics and considers both the direct path and a
ground-reflected propagation path. In a NLOS link, a signal
reaches the receiver through reflections, scattering, and
diffractions. The signals arriving at the receiver consists of
components from the direct path, multiple reflected paths,
scattered energy, and diffracted propagation paths. For the
N-LOS path it is found that average received signal power
decreases logarithmically with distance.
III. CONCATENATED CODES – TURBO CODES
Concatenated codes were proposed as a means of
obtaining long codes with modest decoding complexity.
Concatenated codes are built by combining an outer code
and an inner code, as shown in Fig. 1. This makes for a
large coding gain with less implementation complexity, as
compared to a single code. This coding is followed by
interleaving to randomize the occurrence of bit errors, due
to deep fades in certain subcarriers.
The outer code is usually a (n, k, t) Reed-Solomon code
over Galois Field (2k). The inner code is frequently a
convolutional code. The purpose of the inner code is to
improve the quality of the code system (consisting of the
inner encoder, the channel, and the inner decoder) that the
outer RS code sees. When the inner decoder (Viterbi) makes
a decoding error, it typically involves a few consecutive
stages of the decoding trellis, which results in a short burst
of errors.
Fig. 1 A concatenated Reed Solomon – Convolutional code
It is theoretically possible to approach the Shannon limit
by using a block code with large block length or a
convolutional code with a large constraint length. The
processing power required to decode such long codes makes
this approach impractical. Turbo codes overcome this
limitation by using recursive coders and iterative soft
decoders. A turbo encoder [11] is the parallel concatenation
of a number of two block codes (Fig. 2). The first one
accepts a sequence of entry bits and provides for each
entering bit a parity check bit C1. The entry in the second
encoder is a recomposed version (message data via
interleavers) of the entry sequence bits and provides a parity
check bit C2.
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The interleaver design has a significant effect on code
performance. The initial entry bits in combination with the
two parity check bits are multiplexed and provide the
sequence IC1C2IC1C2, which is the input sequence followed
by the parity check bits from the first encoder and then the
parity bits from the second encoder. The outputs of the
two coders may be multiplexed into the stream giving a rate
R=1/3 code, or they may be punctured to give a rate R=1/2
code.
At the receiver, the signal is demodulated with its
associated noise and a soft output provided to the decoder.
Each decoder operates on the systematic and parity bits
associated with its constituent encoder and produces soft
outputs of the original data bits in the form of a posteriori
probabilities. The decoders then share their respective soft
information in an iterative fashion. The output of each
decoder is interleaved (or deinterleaved) and passed to the
next decoding module as it is a priori information [12]. For
this decoding scheme, an algorithm is required that provides
estimates for the posterior probabilities of each input bit.
The two main types of algorithms are Maximum
A-Posteriori probability (MAP) algorithm, also commonly
known as the BCJR algorithm, after its inventors: Bahl,
Cocke, Jelinek and Raviv [13] and the Soft Output Viterbi
Algorithm (SOVA) [14]. MAP algorithm looks for the most
likely symbol received, while SOVA algorithm looks for the
most likely sequence. Both MAP and SOVA algorithms
perform similarly at high Eb/No. SOVA algorithm is very
similar to the standard Viterbi algorithm used in hard
demodulators. Decoding continues in an iterative fashion for
a fixed number of iterations or until a given convergence
criteria is met.
Fig. 2 Block diagram of a turbo encoder with puncturing
IV. MODELING IEEE 802.11P – SIMULATION RESULTS
In order to evaluate the coding options presented in the
previous sections, IEEE 802.11p PHY was simulated
following the ASTM E2213-03 “Standard Specification for
Telecommunications and Information Exchange between
Roadside and Vehicle Systems” physical layer
characteristics. A full system model was implemented in
Matlab – Simulink, employing a concatenated RS
convolutional code and a turbo code, for different channel
paths respectively. We have estimated Bit Error Rate (BER)
and Packet Error Rate (PER) versus Signal to Noise Ratio
(SNR) for all the modulation constellations and we
compared it with the originally specified scheme.
Convolutional codes can be specified as CC (n, k, m),
where n is the number of output bits, k is the number of
input bits, and m is the constraint length of the encoder
output. The IEEE 802.11p standard uses (171oct133oct) code
with constraint length seven and free minimum distance of
ten. A Viterbi decoder is used to decode the convolutional
codes with a trace back depth of 34 and hard decision.
Through puncturing we can reduce the free distance of six
or five depending on the code rate.
RS error correction is a coding scheme which works by
first constructing a polynomial from the data symbols to be
transmitted, and then sending an over-sampled version of
the polynomial instead of the original symbols themselves.
An RS code is specified as RS (n, k, t) with L-bit symbols,
where n is the number of bytes after encoding, k is the
number of data bytes before encoding and t is the number of
data bytes that can be corrected. This means that the encoder
takes k data symbols of L bits each and adds 2t parity
symbols to construct an n-symbol codeword. The
concatenated scheme was derived from a systematic RS (n =
255, k = 239, t = 8) borrowed from the IEEE 802.16e
(WIMAX) standard using a Galois Field (28), employing a
random interleaver between the inner and the outer encoder.
For the performance evaluation of the turbo codes we
use a punctured parallel concatenation of two convolutional
encoders with constraint length K=3 and the frame size of
512 bits. The model generates turbo code, and decodes the
code iteratively (5 iterations) using MAP detectors. A
random interleaver is used to rearrange the elements of its
input vector through a random permutation. The generates a
codeword with code rate 1/2.
All simulations were conducted under AWGN, Ricean
and Rayleigh fading and had a fixed packet length of N = 20
OFDM symbols per packet. The relative vehicular velocity
was 70 km/h. The distance which the measurements took
place was 100m for the LOS and the N-LOS path between
transmitter and receiver. We assumed 400 ns RMS delay
spread. The Doppler spread was found to be 376 Hz. For the
LOS path the Ricean k factor was 3 dB. The performance
measures in the simulations are the packet error rate and the
bit error rate versus average Eb/No. Note that the PDU size
for all these modes is 256 bytes. Our simulation results for
AWGN (Fig. 3) environment have shown that with 16QAM
the performance was excellent for the turbo coding chain. In
the second case (Fig. 4), with a LOS path, it is observed that
turbo coding continues to perform better and the coding gain
ranges from 1 to 3dB. Regarding the third case (Fig. 5) over
Rayleigh fading channel, our results have shown that
performance obtained by turbo coding in BPSK is better
than the concatenated convolutional coding by 6 dB in the
5th iteration. It must be noted that below BER of 10-4 an
error floor occurs in all cases. The error floor is a
phenomenon encountered in modern iterated sparse
graph-based error correcting codes like turbo codes. The
region where the BER curve flattens out is called the error
floor and hinders the ability of a turbo code to achieve
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extremely small bit-error rates. The error floor is due to the
presence of a few low-weight code words. At low SNR,
these code words are insignificant, but as SNR increases,
they begin to dominate the performance of the code. The
error flooring effect can be combated in several ways. One
way is to use a slightly different Recursive Systematic
Convolutional encoder with a more favourable distance
spectrum. However, in order to lower the error floor at high
SNR, performance at low SNR will suffer [15].
Figure 6 presents the PER performance of 16QAM for
AWGN which lies between 10-2 and 10-1 for the turbo
coding scheme. From our simulation results we came to the
conclusion that the capability of block codes in combination
with convolutional codes for error correction is not
profitable in our propagation conditions. Although we used
an interleaver, the expected improvement of performance
was not observed. A reason that can explain this situation is
the small number of subcarriers according our PHY
specifications was not able to take advantage of the diversity
the coding provides. Furthermore the use of shortened R-S
codes is possible to improve our system performance. On
the other hand the turbo coding scheme achieves excellent
results under all conditions and environments. Regarding
PER curves a more comprehensive simulation of different
packet lengths is planned to see how system capacity affects
the performance.
Fig. 3 Simulation Results for 16QAM CC, RSCC, Turbo in AWGN
environment
Fig. 4 Simulation Results for QPSK CC, RSCC, Turbo in Ricean
Fading-LOS PATH environment
Fig. 5 Simulation Results for BPSK CC, RSCC, Turbo in Rayleigh
Fading-NLOS PATH environment
Fig. 6 Simulation Results for PER of 16QAM AWGN environment
V. FPGA IMPLEMENTATION
With ever increasing system complexities, all major advanced designs have grown too massive and complex to design and verify using traditional RTL methodologies. ESL (electronic system level) design is an emerging design methodology that allows designers to work at higher levels of abstraction than typically supported by register transfer level (RTL) descriptions. Electronic System Level is now an established approach at most of the world‟s leading System-on-a-chip (SoC) design companies, and is being used increasingly in system design.
Further evaluation of the two different coding schemes involves the comparison of their corresponding hardware implementations. For telecommunication applications, ESL tools like Xilinx‟s System Generator [15], Altera‟s DSP builder [16] and Synplicity‟s Synplify DSP [17] have been developed and works with Matlab and Simulink [18]. These tools develop highly parallel systems with the industry‟s most advanced FPGAs and provide system modeling and automatic code generation from Simulink.
In this paper, we have used System Generator to generate VHDL source code from the Xilinx Blockset. Xilinx System Generator is an add-on to the Simulink. It adds Xilinx block set to the current Simulink library. After the models are analyzed through Simulink, an equivalent Xilinx model is implemented using the Xilinx block sets.
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After all the performance parameters are set including the System Generator Token containing the FPGA clock period and Simulink system period, Xilinx model is then run once with all the necessary inputs connected to the appropriate Simulink models. This provides the System Generator with all the necessary parameters required for the implementation.
After simulation, pre-built parameterizable cores are used to automatically generate VHDL code for the whole system, accordingly to user selections. System Generator design flow is depicted in Fig. 7. All our models were developed based on an OFDM Library v1.0 FEC Blockset and the WIMAX 802.16-2004 demonstration design kindly offered by Xilinx, and we have simulated the Forward Error Correction coding chain of the transmitter and the receiver for 802.11p PHY, with the two different coding schemes, turbo coding and concatenated RS convolutional coding respectively.
MATALAB/SIMULINK
XILINX SYSTEM
GENERATOR
XILINX ISE
FPGA
MODEL SIM
HARDWARE
SYNTHESIS, PLACE AND ROUTE
SIMULATIONCODE / BLOCKS
CODE / BLOCKS
Fig. 7 Xilinx System Generator design flow
The coding chain (Fig. 8) of the concatenated scheme for the transmitter consists of the following functional subsystems
Randomizer
Reed Solomon Encoder
Convolutional Encoder
Interleaver
Modulator
They are applied in this order at transmission. The corresponding operations in the receiver are applied in reverse order. At the beginning, data are imported serially into the randomizer. Randomization introduces protection through information theoretic uncertainly avoiding long sequences of consecutive ones or consecutives zeros. After that, the data field shall be coded with an outer RS encoder and an inner convolutional encoder of coding rate R = 1/2, corresponding to BPSK modulation data rate. The output bits of the encoder are interleaved using an interleaver block.
The size of the interleaver increases the effective block length, significantly improving the performance. The interleaved bits are then modulated using a BPSK modulator. Furthermore we have integrated the turbo coding scheme in our 802.11p PHY FEC (Fig. 9) and we have estimated the essential parameters. The generated VHDL code was synthesized for different FPGA device families through synthesis, place and route stages, in ISE software. For implementation, we chose three different FPGA development boards with enhanced DSP and I/O capabilities, the low-cost Spartan-3 1500 from NuHorizons (with Spartan-3 family FPGA device), mid-cost XUPV2Pro from Digilent (with Virtex-2Pro family FPGA device) and the high-cost XtremeDSP from Nallatech (with Virtex-4 family FPGA device).
Fig. 8 IEEE 802.11p Tx RS-CC chain Xilinx Blockset Implementation
Fig. 9 IEEE 802.11p Turbo coding scheme
Implementation results are shown in Table I which lists
speed and resource usage (in terms of the building blocks of
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an FPGA) results for all 3 boards (shorthand NuHo, Digi
and Nalla) under the following columns: a) Period,
the critical path of the circuit in ns, b) LUT, the number of
4-input Look-Up Table function generators required, c) FF,
the number of 1-bit flip-flops required, d) Slice, the number
of FPGA slices required given that an FPGA slice has two
LUTs and two FFs, and e) Mem, the dedicated memory
blocks required. The speed reported for each design in Table
I shows that more expensive devices (of the Virtex family)
offer better performance. Moreover, the XC2VP30 device
found in the Digilent board offers better performance than
the XC4VSX35 device found in the Nallatech board. This is
expected since the former, despite being part of an older
family, is more advanced (XC2VP30 has 2 hard PowerPC
cores while XC4VSX35 has none, and also has a little fewer
LUTs, almost double dedicated memory blocks and 2/3 of
the dedicated Dsp blocks, compared to the XC4VSX35) and
slightly more expensive. This does not influence however
the overall judgement of the containing development boards.
The Nallatech board is more expensive and best suited for
the application because it contains other expensive hardware
components, like the two 14-bit 105 MHz ADC channels
and the two 14-bit 160 MSPS DACs.
TABLE I FPGA TRANSMITTER IMPLEMENTATION DETAILS
Board Period LUT FF Slic
e
Me
m
802.11p
NuHo 16.047 1009 747 699 9
Digi 8.553 1014 746 688 9
Nalla 11.710 1127 782 769 9
802.11p
RS-CC
NuHo 16.175 1009 747 714 9
Digi 8.579 1014 747 682 9
Nalla 12.059 1128 788 824 9
802.11p
Turbo
NuHo 17.191 1114 845 803 9
Digi 8.850 1119 844 753 9
Nalla 12.828 1236 887 811 9
Another issue that affects performance is functionality,
so the turbo coding scheme for five iterations comes with
speed degradation of 7.1% from the simple 802.11p and
6.3% from the RS-CC in the NuHorizons board. This is an
expected figure and can go lower when using specific
timing constraints in the design process. However, for the
Nallatech board, our implementation of turbo coding offers
more functionality and speed improvements too, up to
18.5% (turbo coding over RS-CC). This is a very valuable
result and is reported due to the optimum fitting of the
application to the modern architecture of the Virtex-4 family.
Even though these numbers may change if more aggressive
optimization techniques are used, they are very promising.
The resources reported in Table 1 show that more
functionality requires more resources in every case, as
expected. However, the resource overhead is always below
10%. Taken into account that in all cases the resources used
(LUTs, FFs, dedicated memories, dedicated DSP blocks) are
below 5% off all the resources available in the specific
FPGA, this overhead can be considered negligible for large
designs. Moreover, since an FPGA slice contains 2 LUTs
and 2 FFs, these 2 types of components are packed together
for more resource savings. For example, the 9% area
overhead between the simple 802.11p and the Turbo coded
in LUTs for the Nallatech board is translated in a 7.8% are
overhead in terms of slices. This packaging can be made
denser with correct design techniques and thus, area
overhead can be further decreased. Implementation results
for the receiver are depicted in Table 2 only for Nallatech
Development board. The implementation of the receiver
FEC coding chain is a lot more complex than that of the
encoder since it requires more computations, use of larger
arrays of data and the storing of these data to more memory
blocks. However, the device utilization is kept at reasonable
rates; which is a crucial part of area-restricted applications,
such as the implementation on an embedded system. The
receiver occupies a total of 1.000 slices out of the 15.360
slices available on the FPGA, meaning that the device
utilization is at 15% in terms of occupied slices with Turbo
coding offers more functionality as in transmitter. Overall,
results show that turbo coding can be implemented in FPGA
without significant performance loss in any case, and with
possible performance improvements in some cases.
TABLE II FPGA RECEIVER IMPLEMENTATION DETAILS
Board Period LUT FF Slice Mem
802.11p
Nalla 15.223 1465 1016 1000 12
802.11p
RS-CC
Nalla 15.676 1472 1026 1023 12
802.11p
Turbo
Nalla 16.183 1606 1105 1117 12
To further quantify the improvements suggested through
extensive simulation, a test-bed (Fig. 10) was developed to
compare the theoretical model variation with real time
implementation. The FEC system for the turbo coding
scheme of the transmitter and the receiver was implemented
with two identical Nallatech XtremeDsp Development Kit,
using Xilinx ISE software to generate the programming
bitfile, Nallatech FUSE tool to connect the XtremeDSP
Motherboard through USB interface to a notebook computer,
and assign the bitfile to the Virtex-4 device. The Digital to
Analog outputs on the Nallatech board were connected
through MCX-BNC cables to channels on the Fluke
PM3380B oscilloscope. The development kit achieves a top
frequency of 105 MHz which means tclk
= 9.5 ns. For
measurement, we performed co-simulation with the VHDL
models generated from System Generator for the transmitter
and the receiver.
Preliminary results show high accuracy between initial
simulation-only results and final, VHDL/Simulink
co-simulation measurements (Fig. 11), where each curve
corresponds to a specific coding iteration (ITERi) and the
pure simulation models (-SIM.) or the HW/SW co-simulated
models (-IMPL.). The real time implementation model‟s
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BER curves, are proven to be slightly worse compared to the
initial, theoretical ones.
Fig. 10 An FPGA test-bed for FEC coding chain hardware architecture using
Nallatech XtremeDSP kit, notebook with Fuse software for the transmitter
configuration and Fluke PM3380B oscilloscope
Fig. 11 Turbo coding scheme for real time implementations and theoretical
model simulations
VI. CONCLUSIONS
This article presented the performance evaluation results
of a comparative study for IEEE 802.11p PHY employing
two different coding schemes, concatenated Reed Solomon
convolutional coding and turbo coding. From the obtained
simulation results, the BER vs SNR for different kinds of
modulation schemes in different channels are calculated. In
general wireless communication systems, convolutional
codes provide powerful error correction capability,
especially in mobile environments with low signal-to-noise
ratio. In IEEE 802.16 system, Reed-Solomon code and
convolutional code are concatenated for channel coding but
in IEEE 802.11p, only convolutional code is adopted for
error correction. Both of them are OFDM based designs. As
a first step in our evaluation, we have explored concatenated
codes using two encoders and we have seen that the
capability of block codes in combination with convolutional
codes for error correction is not profitable in our
propagation conditions. As a second step, we tested turbo
codes using two encoders and we came to the conclusion
that turbo codes tend to outperform the other coding
schemes. The results presented in this paper show that in all
environmental cases they achieved significant improvement
in our propagation conditions. However, as observed from
the presented plots, it must be noted that there is an error
floor associated with turbo codes. More specific, when we
have low BER the curve flattens a little. According to [12]
the error floor, which appears at higher SNRs, is thus
ostensibly due to the presence of a minimum Hamming
distance between codewords. Taking everything into
account, we have shown how turbo codes and decoders can
be used to improve the performance of the IEEE 802.11p
system. Finally, we presented implementations of the FEC
coding chain with Xilinx FPGAs using ESL as a fast
prototyping approach. The experiments conducted so far
show that the implementation of the 802.11p turbo coding in
different FPGAs does not impose any significant
performance or resource usage overhead compared to the
802.11p and the 802.11p RS-CC. In addition a test-bed was
developed to compare the theoretical model variation with
real time implementation. Preliminary results show high
accuracy between initial simulation results and
implementation measurements. In the future we intend to
perform further experiments and we will develop the whole
PHY transceiver including the OFDM part in System
Generator using the Nallatech XtremeDSP Development
Kit.
ACKNOWLEDGMENT
The authors would like to thank Xilinx and their University program representatives for their contribution by providing us the Xilinx OFDM Library v1.0 FEC Blockset & WIMAX 802.16-2004 demonstration design and collateral.
REFERENCES
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Kiokes George graduated in 2000 from
Technological Educational Institute of
Piraeus with a diploma of Electrical
Engineering. In 2004 graduated from
National Technical University of Athens
with a diploma of Electrical and Computer
Engineering. He obtained his PhD (Dec.
2009) in the Microwaves and Fiber Optics
Laboratory of the National Technical
University of Athens. The objective of his thesis was the analysis
and the implementation in Field Programmable Gate Array (FPGA)
of the PHY for the Automotive WLAN standard. His research
interests focuses within the areas of vehicular communications,
wireless communications, and FPGAs. He has participated in
many FP6 and FP7 EU co-funded research projects as a member of
I-sense group at the Institute of Communication and Computer
systems. In January 2012 he became an adjunct Lecturer at the
Department of Electronics, Electric power, Telecommunications,
Hellenic Air-Force Academy.
Dr George Economakos received his
Diploma in Electrical and Computer
Engineering from the National Technical
University of Athens, Greece, in 1992. He
received the Ph.D. Degree in Electrical and
Computer Engineering, from the National
Technical University of Athens in 1999. He
is currently working an Assistant Professor
of Electrical and Computer Engineering,
National Technical University of Athens, Greece. His research
interests include design automation, high-level synthesis,
electronic system level design, reconfigurable computing and
design for low power. He has published more than 110 papers in
international journals and conferences and served as a reviewer in
most of them, being a member of the program committee 4 times. He
was investigator in numerous research projects funded from the
Greek Government and Industry as well as the European
Commission. He is a member of the ACM, IEEE and
EUROMICRO and has served as a member in more than 10
standardization groups in the field of design automation.
Dr. Angelos J. Amditis was born in
Sydney of Australia (1968). He has
obtained the Diploma in Electrical and
Computer Engineering from the National
Technical University of Athens - NTUA
(Greece) in 1992, and his Ph.D. in
Electrical and Computer Engineering
(Telecommunications) from NTUA
(Greece) in 1997. He has been teaching in
various courses (communication and computer networks,
communication theory etc.) of the Electrical and Computer
Engineering Dep. of NTUA,
of ICCS and of the Hellenic Naval Academy. He is a Research
Director of the Institute of Communication and Computer Systems
and member of its Board of Directors; and the writer of several
peer reviewed journal articles, book chapters and conference
papers. His current research interests are in the fields of Intelligent
Transportation Systems (ADAS, Human Machine Interfaces,
Information Fusion...), Virtual Reality, Sensors for monitoring
purposes, Telematics, Driver monitoring, Telecommunications
systems, EMC/EMI, Electromagnetic sensors etc. He has
participated in a large number of Research projects being the
scientific responsible of more than forty projects in the last 10
years (e.g. interactIVe, HAVE-IT, euroFOT, TELEFOT,
MiniFaros, PowerUp, PreVent, AIDE, INTUITION, SAFESPOT,
SENSATION etc.).
Nikolaos K. Uzunoglu was born in
Constantinopole, Turkey, in 1951. He
received the B.Sc. degree in electrical
engineering from the Istanbul Technical
University, Istanbul, Turkey, in 1973, and
the M.Sc. and Ph.D. degrees from the
University of Essex, Essex, U.K., in 1974
and 1976, respectively. From 1977 to 1984,
he was with the Hellenic Navy Research
and Development Office. In 1984, he became an Associate
Professor and, in 1988, a Professor of electrical engineering at the
National Technical University of Athens (NTUA), Athens, Greece.
From 1991 to 1999, he was the Director of the Institute of
Communication and Computer Science (ICCS), NTUA. His
research interests include electromagnetic theory, microwaves,
fiber optics, biological process simulations, and biomedical
engineering. Prof. Uzunoglu is a member of the Academy of
Sciences of Armenia. He was the recipient of the 1981
International G. Marconi Award in Telecommunication.