a 5.25-ghz cmos folded-cascode even-harmonic mixer for low-voltage applications ming-feng huang,...
TRANSCRIPT
A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage ApplicationsMing-Feng Huang, Chung J. Kuo, Senior Member, IEEE, and Shuenn-Yuh Lee, Member, IEEEIEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 2, FEBRUARY 2006
指導教授 :林志明 級別 :體積所碩一
學生 :呂致遠Mail:[email protected]
民國 95年 3月 28 日
Outline
Abstract Introduction Schematic Microphotograph Experimental result Comparison Conclusion References
Abstract
5.25-GHz folded-cascode evenharmonic mixer (FEHM)
Reduce the headroom voltage A current reuse circuit Frequency-doubling technique Conversion gain of 8.3 dB IIP3 of 0.03 dBm Supply voltage of 0.9 V LO power of 5.5 dBm Power consumption of 4.95 mW IF frequency of 500 kHz
Introduction
The low-voltage RF integrated-circuit (RFIC) development for portable communication equipments has been a focus due to the advances in device technology for high-speed
applications. More and more designers have proposed RFIC for high-speed and low-voltage applications.
Schematic(EHM)fIF=fRF-2fLO
Current reuse circuit
Frequency-doubling
circuit
Folded technique
Lowvoltage
Schematic of the proposed full monolithic FEHM
ReduceHeadroom
voltage
Bias buffer
VDD=0.9VVRF=0.5VDD
MicrophotographL_tank:st
dNT:2.5
PADNOT ON WAFER
ON PCB
C_tank:mimcap
L1:stdNT:5.5
RF-RF+
LO-LO+
VRF
IF+IF-
?
VLOVDDGND
Conclusion
FEHM with folded technique Verified by experimental data Large conversion gain Low complexity High operational frequency Direct conversion receivers.
REFERENCES
[1] M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, N. Ito, T. Yoshitomi, T. Ohguro, H. S. Momose, and H. Iwai, “0.15-m RF CMOS technology compatible with logic CMOS for low-voltage operation,” IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 737–742, Mar. 1998. [2] T. Manku, G. Beck, and E. J. Shin, “A low-voltage design technique for RF integrated circuits,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 10, pp. 1408–1413, Oct. 1998. [3] F. Svelto, M. Conta, V. D. Torre, and R. Castello, “A low-voltage topology for CMOS RF mixers,” IEEE Trans. Consumer Electron., vol. 45, no. 3, pp. 299–309, May 1999. [4] J. R. Long, “A low-voltage 5.1–5.8-GHz image-reject downconverter RF IC,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1320–1328, Sep. 2000. [5] E. Abou-Allam, J. J. Nisbet, and M. C. Maliepaard, “Low-voltage 1.9-GHz front-end receiver in 0.5-m CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1434–1443, Oct. 2001. [6] M. N. El-Gamal, K. H. Lee, and T. K. Tsang, “Very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications,” Proc. Inst. Elect. Eng. Circuits, Devices Syst., vol. 149, pp. 355–362, Oct.–Dec. 2002. [7] U. Yodprasit and C. C. Enz, “Simple topology for low-voltage and lowpower RF quadrature oscillators,” Electron. Lett., vol. 40, pp. 458–460, Apr. 2004. [8] K.Kwok and H. C. Luong, “Ultra-low-voltage high-performanceCMOS VCO’s using transformer feedback,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 652–660, Mar. 2005. [9] B. Matinpour, S. Chakraborty, and J. Laskar, “Novel DC-offset cancellation techniques for even-harmonic direct conversion receivers,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2554–2559, Dec. 2000. [10] T. Yamaji, H. Tanimoto, and H. Kokatsu, “An I/Q active balanced harmonic mixer with IM2 cancellers and a 45 phase shifter,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2240–2246, Dec. 1998. [11] T. Yamaji and H. Tanimoto, “A 2 GHz balanced harmonic mixer for direct-conversion receivers,” in Proc. IEEE Custom Integrated Circuits Conf., May 1997, pp. 9.6.1–9.6.4. [12] Z. Zhang, Z. Chen, and J. Lau, “A 900 MHz CMOS balanced harmonic mixer for direct conversion receivers,” in Proc. IEEE Radio Wireless Conf., Sep. 2000, pp. 219–222.
REFERENCES [13] S. J. Fang, S. T. Lee, and D. J. Allstot, “A 2 GHz CMOS even harmonic mixer for direct conversion receivers,” in Proc. IEEE Int. Symp. Circuits Syst. , vol. 4, 2002, pp. 807–810. [14] L. Sheng, J. C. Jensen, and L. E. Larson, “A wide-bandwidth Si/SiGe HBT direct conversion subharmonic mixer/downconverter,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1329–1337, Sep. 2000. [15] M. Goldfarb, E. Balboni, and J. Cavey, “Even harmonic double-balanced active mixer for use in direct conversion receivers,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1762–1766, Oct. 2003. [16] Z. Zhang, L. Tsui, Z. Chen, and J. Lau, “A CMOS self-mixing-free front-end for direct conversion applications,” in Proc. IEEE Int. Circuits Syst. Symp., May 2001, pp. 386–389. [17] S.-Y. Lee, M.-F. Huang, and C. J. Kuo, “Analysis and implementation of a CMOS even harmonic mixer with current reuse for heterodyne/direct conversion receivers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp. 1741–1751, Sep. 2005. [18] M.-F. Huang, S.-Y. Lee, and C. J. Kuo, “A CMOS even harmonic mixer with current reuse for low power applications,” in Proc. ACM Int. Low Power Electron. Design Symp., Aug. 2004, pp. 290–295. [19] , “Design and analysis of a CMOS even harmonic mixer with current reuse circuits,” in Proc. IEEE Asia–Pacific Circuits Syst. Conf., Dec. 2004, pp. 269–272. [20] A. N. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and mixer,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1939–1944, Dec. 1996. [21] S.-G. Lee and J.-K. Choi, “Current-reuse bleeding mixer,” Electron. Lett., vol. 36, pp. 696–697, Apr. 2000. [22] B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, 1998. [23] , Design of Analog CMOS Integrated Circuits, Singapore: Mc- Graw-Hill, 2001. [24] L. Sheng and L. E. Larson, “An Si–SiGe BiCMOS direct-conversion mixer with second-order and third-order nonlinearity cancellation for WCDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 11, pp. 2211–2220, Nov. 2003. [25] E. A. M. Klumperink, S. M. Louwsma, G. J. M. Wienk, and B. Nauta, “A CMOSswitched transconductor mixer,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1231–1240, Aug. 2004.