8a3xxxx 48qfn evk user manual - renesas
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8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 1 February 15, 2019
Description
The 8Axxxx 48QFN EVK is designed to help customers evaluate IDT ClockMatrix devices. This document discusses the following about the EVK:
Introduces the board and its power supply and jumper settings
Describes the input and output connectors for normaloperation
Explains how to bring up the board using the TimingCommander software GUI
Discusses how to configure and program the board togenerate standard-compliant frequencies
Kit Contents
8A34xxx 48QFN Evaluation Board
USB Type A cable
Requirements
IDT Timing Commander Software Installed (available atwww.idt.com/timingcommander)
ClockMatrix GUI (available at www.idt.com/clockmatrix)
USB 2.0 or USB 3.0 interface
Windows XP SP3 or later
Processor: Minimum 1GHz
Memory: Minimum 512MB; recommended 1GB
Available disk space: Minimum 600MB (1.5GB 64-bit);recommended 1GB (2GB 64-bit)
Network access during installation if the .NET framework is notcurrently installed on the system
8A3xxxx 48QFN EVK Board
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 2 February 15, 2019
Important Notes
Disclaimer
Integrated Device Technology, Inc. and its affiliated companies (herein referred to as “IDT”) shall not be liable for any damages arising out of defects resulting from
(i) delivered hardware or software
(ii) non-observance of instructions contained in this manual and in any other documentation provided to user, or
(iii) misuse, abuse, use under abnormal conditions, or alteration by anyone other than IDT.
TO THE EXTENT PERMITTED BY LAW, IDT HEREBY EXPRESSLY DISCLAIMS AND USER EXPRESSLY WAIVES ANY AND ALL WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY AND OF FITNESS FOR A PARTICULAR PURPOSE, STATUTORY WARRANTY OF NON-INFRINGEMENT, AND ANY OTHER WARRANTY THAT MAY ARISE BY REASON OF USAGE OF TRADE, CUSTOM, OR COURSE OF DEALING.
Important Equipment Warning: Ensure the correct connection of all cables. Supplying the board using the wrong polarity could result in damage to the board and/or the equipment. Check that all jumpers have been removed from the board before applying power.
Contents
1. Usage Guide .................................................................................................................................................................................................4
1.1 Board Overview ...................................................................................................................................................................................4
1.2 Board Power Supply ............................................................................................................................................................................5
1.3 Voltage Selection Jumpers ..................................................................................................................................................................5
1.4 GPIO Switches, LEDs, and Test Points ..............................................................................................................................................6
1.5 USB Jack .............................................................................................................................................................................................7
1.6 Onboard EEPROM ..............................................................................................................................................................................7
1.7 I2C/SPI Auxiliary Path Specifications ...................................................................................................................................................7
2. Working with Timing Commander™ for Programing/Configuration ..............................................................................................................8
2.1 Default Operation ................................................................................................................................................................................8
2.2 Using Timing Commander to Control the Board ................................................................................................................................10
2.3 Output Terminations and Rework to Take 1PPS Input ......................................................................................................................16
3. How to Upgrade the Firmware ....................................................................................................................................................................17
3.1 Upload Firmware to the RAM ............................................................................................................................................................17
3.2 Upload Firmware into the EEPROM ..................................................................................................................................................19
3.3 Verify the EEPROM Programming ....................................................................................................................................................20
4. Schematics .................................................................................................................................................................................................21
5. Ordering Information ...................................................................................................................................................................................21
6. Revision History ..........................................................................................................................................................................................21
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8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 3 February 15, 2019
List of Figures
Figure 1. Overview of 48QFN ClockMatrix Evaluation Board .............................................................................................................................4
Figure 2. Example of Voltage Jumpers ...............................................................................................................................................................5
Figure 3. GPIO Setting and Status Display Area ................................................................................................................................................7
Figure 4. Board Setting for Default Operation ....................................................................................................................................................9
Figure 5. Starting Up Timing Commander GUI .................................................................................................................................................10
Figure 6. Selecting 8A34001 using Personality File v4.6 ..................................................................................................................................11
Figure 7. Timing Commander GUI with a Settings File Opened .......................................................................................................................12
Figure 8. Setting I2C for Connecting the Board with GUI ..................................................................................................................................13
Figure 9. A Green Band appears when a Valid Connection is Made ................................................................................................................13
Figure 10. Firmware Version Mismatch Warning Message ................................................................................................................................14
Figure 11. Reading Firmware Version ................................................................................................................................................................14
Figure 12. Read Firmware Version of ClockMatrix Chip .....................................................................................................................................15
Figure 13. AC Coupling and Terminations for Input Clock ..................................................................................................................................16
Figure 14. Configuring CLK0 as CMOS to Receive a 1PPS Input ......................................................................................................................16
List of Tables
Table 1. GPIO Settings ......................................................................................................................................................................................6
Table 2. EEPROM I2C Connections ..................................................................................................................................................................7
Table 3. I2C/SPI Path Connections....................................................................................................................................................................7
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 4 February 15, 2019
1. Usage Guide
1.1 Board Overview
The following diagram identifies various components of the board: input and output SMA connectors, power supply jacks, and some jumper settings necessary for the board operations.
Figure 1. Overview of 48QFN ClockMatrix Evaluation Board
Detailed descriptions of the board are as follows.
Input SMA Connectors – There are two differential inputs labeled CLK0/nCLK0–CLK1/nCLK1. Each input clock can be configureddifferentially (LVDS, PECL 2.5V, and PECL 3.3V) or in single-ended format (CMOS).
Output SMA Connectors – There are four outputs labeled as Q8/nQ8–Q11/nQ11. Each output clock can be configured differentially(LVDS, LVPECL, or user-defined amplitude), or in single-ended format (LVCMOS – in-phase or out-of-phase)
GPIO switch, LEDs, and test points – There are eight GPIOs available. Each GPIO can be set a “low” or “high” level (if input) or displayedwith an LED (if output). Some GPIOs are used to set the chip in a certain working condition on power-up. For more information, see GPIOSwitches, LEDs, and Test Points.
USB connector – A USB mini-connector connects the evaluation board to a PC for GUI communications. No power is drawn from the USBconnector other than to power the FTDI USB chip.
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VCCO voltage selection jumpers – Each output voltage can be individually supplied with 1.8V, 2.5V, or 3.3V. These jumpers are used toselect the voltage for the output voltages.
Reset button – A small button is used to reset the board.
OSCI Input connector – An SMA connector, J45, can optionally supply a clock signal to overdrive the crystal.
OCXO/TCXO reference – An SMA connector, J46, can supply a local OCXO/TCXO reference as an optional reference for System DPLL.
Crystal – A crystal of various frequencies must be present for board operations. A 3225 footprint is provided for SMT crystals. For easyplug-in of a canned crystal, two through holes are also available.
EEPROM – An SO-8 socket is provided to hold an EEPROM device of compatible package. EEROM is used to store firmware andcustomer configuration data, if needed.
1.2 Board Power Supply
The board uses a single +5V supply for its power supplies. When running the board, set the bench power supply at 5V/2A. The red jack (J1) is positive; the black jack (J2) is the ground.
Multiple LDOs are used to generate 3.3V, 2.5V, and 1.8V from the +5V supply.
1.3 Voltage Selection Jumpers
There are nine headers/jumpers to select different voltages for different functional blocks of the chip. Each header is labeled pin 1 and pin 3 – jumping pin 1 and pin 2 will select 3.3V; jumping pin 2 and pin 3 will select 2.5V; no jumper will have 1.8V.
Please see the following example for JP4 and JP9 – JP4 will select 2.5V; JP9 will select 3.3V.
Figure 2. Example of Voltage Jumpers
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 6 February 15, 2019
The following list shows which header/jumper is used to select what voltage:
JP1 – VDDD
JP2 – VDDA
JP3 – VCC_GPIO_DC
JP4 – VDDO_Q8_3_5
JP5 – VDDO_Q2_4_11
JP6 – VDDO_1_10_7
JP7 – VDD_CLK0
JP8 – VDD_CLK1
JP9 – VDDO_Q0_9_6
Important Equipment Warning: VDD_FOD voltage is selected by resistors R908 and R909. In order to prevent damage to the device, both R908 and R909 should not be stuffed, in which case VDD_FOD = 1.8V.
1.4 GPIO Switches, LEDs, and Test Points
An 8-bit dip switch sets the logic levels for eight GPIOs. The following table shows the GPIO levels for each setting and the corresponding LED state.
Table 1. GPIO Settings
Dip Switch Position GPIO Logic Level LED
Left Low On
Center High if GPIO is configured as Input
High or Low according to the GPIO output setting
High if GPIO is configured as Input
High or Low according to the GPIO output setting
Right High Off
Please see the picture and labels in Figure 3.
When the GPIOs are configured as outputs (such as User-Controlled or LOL indicator), the dip switch for the corresponding GPIO should be placed in the center position. The LED will indicate the state of the GPIO.
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© 2019 Integrated Device Technology, Inc. 7 February 15, 2019
Figure 3. GPIO Setting and Status Display Area
1.5 USB Jack
The board has a USB mini-connector. The other end of the USB cable is a USB Type A connector going to a PC.
1.6 Onboard EEPROM
An onboard EEPROM is used to store device firmware and/or customer’s configuration data. There are two headers/jumpers, JP10 and JP11, used to select the I2C communication paths for the EEPROM.
Table 2. EEPROM I2C Connections
JP10/JP11 JP10/JP11
Jumper Position Both Pin 1 and 2 Both Pin 2 and 3
EEPROM I2C Path FDTI and EEPROM EEPROM and CM Chip
1.7 I2C/SPI Auxiliary Path Specifications
I2C and SPI connections can be configured using onboard jumpers. There are four headers/jumpers that control the auxiliary serial stream signals.
Table 3. I2C/SPI Path Connections
JP12/JP13 JP12/JP13 JP14/JP15 JP14/JP15
Jumper Position Pin 1 and 2 Pin 2 and 3 Pin 1 and 2 Pin 2 and 3
CM Chip Serial Port Path
SCLK/SDA Connected to on-
board FTDI I2C Chip (Default)
SCLK/SDA Connected to J4 for external
I2C/SPI controller use
NONE SDI/nCS Connected to J4 for external I2C/SPI
controller use
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 8 February 15, 2019
2. Working with Timing Commander™ for Programing/Configuration
The following sections are best cross-referenced with the ClockMatrix GUI Step-by-Step User Guide which is available on www.idt.com.
2.1 Default Operation
The board can operate off an EEPROM that has stored all information including firmware and a default configuration data. A default operation provides a sanity check on the board before running the board through the IDT Timing Commander. Please set the board in the following default conditions (see Figure 4 for jumper and switch positions).
Set all the GPIOs to the center position. This will ensure that GPIO8 and GPIO9 are high and that the serial port is configured for I2C 1-byte addressing.
VDDA = 3.3V, VCC_GPIO_DC = 3.3V, and VDDO_Qx = 3.3V
Crystal frequency = 50MHz
CLK0 = 25MHz
EEPROM is connected to ClockMatrix chip through an I2C bus by jumping Pin 2 and 3 of JP10 and JP11
With the above default conditions ready, connect the board to the PC using a USB type A to USB mini cable, and power up the board using a single +5V supply. On power-up, the ClockMatrix chip will read its firmware and configuration data from EEPROM and update all registers. When this process is completed, the following frequencies are available:
Q0 = 122.88MHz
Q1 = 122.88MHz
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 9 February 15, 2019
Figure 4. Board Setting for Default Operation
Important Equipment Warning: In order to set GPIO8 and GPIO9 to “High”, the switches for GPIO8 and GPIO9 must be set either to the “+” (high) position or the center position. !
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 10 February 15, 2019
2.2 Using Timing Commander to Control the Board
Once the default operation is successful, complete the following steps to configure and program the ClockMatrix device per your specific application requirements using Timing Commander GUI tools:
1. Power up the board and set the main serial port in I2C mode by GPIO9 = “high”. Set GPIO8 = “High”. Connect the board to the PC.
2. Start the Timing Commander software. You will see options of “New Setting File” and “Open Setting file”. For a new configuration, select “New Setting File”.
Figure 5. Starting Up Timing Commander GUI
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 11 February 15, 2019
3. After selecting “New Settings File”, a device selection window will pop up. In the window, choose the intended device in the list (in this example, 8A34001 is selected). Click the button at the lower right corner of the window (red circle) to browse and select the correct personality file (in this example, personality v4.6 is selected). Click OK.
Figure 6. Selecting 8A34001 using Personality File v4.6
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 12 February 15, 2019
4. The GUI window with the 8A34001 block diagram will open for configurations; or if “Open Settings File” is selected in Step 3, you will be prompted to browse and select an existing .tcs file and the personality file. When the configuration file is open, all configured values will be displayed (see Figure 7).
Figure 7. Timing Commander GUI with a Settings File Opened
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 13 February 15, 2019
5. In order to connect the board with Timing Commander (PC), click the button (red circle) at the up-right corner of the GUI to set up thecommunication protocols (see Figure 7).
After I2C and one-byte addressing are selected, click OK to close the window.
Figure 8. Setting I2C for Connecting the Board with GUI
6. Click on the chip symbol at the upper-right corner to initiate the connection. The connection is valid when a green band appears at theupper-right corner of the window, as shown below.
Figure 9. A Green Band appears when a Valid Connection is Made
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 14 February 15, 2019
7. If ClockMatrix chip’s firmware, or firmware loaded from EEPROM, has a different version from that in the Personality file, a firmware version mismatch warning message will appear. Click “Close” button to close the message window and a connection is made.
Figure 10. Firmware Version Mismatch Warning Message
8. Once the connection is made, the firmware version can be read within the GUI. Click the “Firmware Utility” button to bring up the Firmware Utility window, as shown below.
Figure 11. Reading Firmware Version
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 15 February 15, 2019
9. Within the Firmware Utility window, click the “Get Firmware Version” button to read the firmware version.
Figure 12. Read Firmware Version of ClockMatrix Chip
10. In the case where the firmware version mismatches each other, a firmware upgrade is necessary to update the chip’s firmware. To do so, complete the steps in How to Upgrade the Firmware to update the chip’s firmware.
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 16 February 15, 2019
2.3 Output Terminations and Rework to Take 1PPS Input
All outputs are terminated per LVDS with a 100Ω resistor across the output pair. When the output is configured as PECL2.5 and PECL3.3 or user-defined differential, the output clock will still be switching. The amplitude may be different from expected until the hardware termination matches the signaling type configured for the output.
The following rework must be implemented in order to support a 1PPS input clock. All input clocks for this board are ac-coupled and terminated as in the following figure.
Figure 13. AC Coupling and Terminations for Input Clock
For a 1PPS input, a single-ended input with DC-coupling is recommended. As such, the populated AC-coupling capacitor must be removed and the input must be configured as LVCMOS, not differential.
1. In Figure 13, to make CLK0 supportive of 1PPS input, first configure CLK0 as LVCMOS in Timing Commander (see Figure 14).
Figure 14. Configuring CLK0 as CMOS to Receive a 1PPS Input
2. Once in LVCMOS mode, CLK0_P and CLK0_N will be two separate LVCMOS inputs instead of a differential pair. To make CLK0_P receive a 1PPS input, replace C881 with a 0Ω resistor; and at the same time, remove R765 and R770.
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 17 February 15, 2019
3. How to Upgrade the Firmware
3.1 Upload Firmware to the RAM
1. Connect to the EVK board.
2. Power up the board with no EEPROM present. This ensures the firmware is 4.0.2.7017, as displayed in the figure.
3. The GUI will indicate that the firmware on the chip does not match the GUI firmware. Press “Close”.
4. Open the “Firmware Utility” window by clicking on the button as follows.
5. Update the Firmware first. Press “Update RAM to Current FW Only”.
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 18 February 15, 2019
6. In the next window, press “Yes” and wait around 3-4 minutes.
7. Once the firmware is updated, the following window will indicate a successful update. Click “Close”.
8. Press “Get Firmware Version” to verify that the RAM was updated correctly, then click “Close”.
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 19 February 15, 2019
3.2 Upload Firmware into the EEPROM
1. Once the firmware has been updated to the chip (steps 1 to 8), install the EEPROM on the EVK board.
2. Press “Write Firmware to EEPROM Only”.
3. In the next window, press “Yes”.
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 20 February 15, 2019
4. When asked to “Verify” the EEPROM, press “No”.
5. In the next window, press “Close” to start the EEPROM write.
6. Wait about 5 minutes for the EEPROM write to complete. Click “Close” in the following window.
3.3 Verify the EEPROM Programming
7. Power cycle the board.
8. Disconnect and reconnect to the chip.
9. Read back the firmware version to ensure it is correct (see steps 3 to 7).
8A3xxxx 48QFN EVK User Manual
© 2019 Integrated Device Technology, Inc. 21 February 15, 2019
4. Schematics
Please see the schematics located at the end of this document.
5. Ordering Information
Orderable Part Number Description
8A34043-EVK 8A3xxxx 48QFN Evaluation Kit
6. Revision History
Revision Date Description of Change
February 15, 2019 Initial release.
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MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
92
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
Pow
er S
uppl
ies
1
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
92
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
Pow
er S
uppl
ies
1
R29
26.1
k
R70
844
.2k
R77
21k
R18
21k
C866
1.0uF
R902 10k
C83
8
0.01
uF
D3
LNJ3
47W
83R
A
NC
RvR 19-11-14BZX84C5V6
D1
DIODE ZENER 5.6V 350MW SOT23-3
1
2
3
R907 52.3k
R16 52.3k
C80
4
10uF
R90
544
.2k
C95
3
0.1u
F
C8670.01uF
R15
26.1
k
C3 0.01
uF
R707 52.3k
C9 1.0uF
R598 10k
C84
1
0.1u
FR
709
21k
RvR
02-09-15
U70
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
R90
421
k
R26 10k
C86
3
0.1u
F
C95
4
10uF
JP3
VD
DA
_SE
L
C956 1.0uF
JP2
VD
DA
_SE
L
C845 0.1u
F03-09-15
RvR
AD
M71
71A
CP
Z-R
7
U69
IC R
EG
LD
O A
DJ
1A 8
LFC
SP
SS
4
EN
5
VIN
7
VIN
8V
OU
T1
VO
UT
2
SE
NS
E3
GN
D6
GN
DP
AD
9
R599 17.4k
C84
2
10uF
C837 10uF
R909 0DNS
19-02-14
RvR
J1 111-
0702
-001
PO
ST
BIN
DIN
G IN
SU
LAT
ED
RE
D
11
C86
4
10uF
C86
5
0.01
uF
C957 0.01uF
C846 10uF
R486 3k
D16
LNJ3
47W
83R
A
JP1
VD
DA
_SE
L
C79
9
0.1u
F
R908 0DNS
19-02-14
RvR
J2 111-
0703
-001
PO
ST
BIN
DIN
G IN
SU
L G
RO
UN
DE
D B
LCK
11
R30 52.3k
RvR
02-09-15
U89
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
RT
112
06L3
50S
LTH
YR
R703 10k
C15 1.0uF
C8
0.01
uF
C14
0.01
uF
C80
0
10uF
R90
326
.1k
R597 1k
R76
44.2
kR
1744
.2k
C16 0.01uF
RvR
02-09-15
U9
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
R70
626
.1k
C836 1000pF
R12 10k
RvR
02-09-15
U17
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
C80
3
0.1u
F
C10 0.01uF
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SILKSCRN:
VDDO_Q8,Q3,Q5
SILKSCRN:
VDDO_Q0,Q9,Q6
SILKSCRN:
VDDO_Q1,Q10,Q7
SILKSCRN:
VDDO_Q2,Q4,Q11
SILKSCRN:
VDD_CLK1
3V3
2V5
SILKSCRN:
3.3V Top
2.5V Bot
1.8V Float
3V3
2V5
SILKSCRN:
3.3V Top
2.5V Bot
1.8V Float
3V3
2V5
SILKSCRN:
3.3V Top
2.5V Bot
1.8V Float
3V3
2V5
SILKSCRN:
3.3V Top
2.5V Bot
1.8V Float
3V3
2V5
SILKSCRN:
3.3V Top
2.5V Bot
1.8V Float
5V0
VD
DO
_Q1_
10_7
5V0
VD
DO
_Q2_
4_11
VD
DO
_Q8_
3_5
5V0
VD
DO
_Q0_
9_6
5V0
5V0
VD
D_C
LK1
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
93
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
Pow
er S
uppl
ies
2
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
93
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
Pow
er S
uppl
ies
2
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
93
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
Pow
er S
uppl
ies
2
R64
26.1
k
C81
2
0.1u
F
C20
0.01
uF
C4060.01uF
R55 10k
R400 10kR
8921
kR
5026
.1k
RvR
02-09-15
U19
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
C81
0
0.1u
F
C40
7
0.01
uF
C81
3
10uF
R50
144
.2k
TP
1
C26
0.01
uF
C81
6
0.1u
F
R47 10k
R92
44.2
k
C81
1
10uF
JP4
VD
DA
_SE
L
R61 10k
R40
526
.1k
R58 52.3k
JP8
VD
DA
_SE
L
C81
7
10uF
R50
321
k
C23
0.01
uF
R40 10k
R35 52.3k
C27 1.0uF
JP9
VD
DA
_SE
L
RvR
02-09-15
U40
1
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
C21 1.0uF
R93
21k
R84
44.2
k
R406 52.3k
C29
0.01
uF
C28 0.01uF
C30 1.0uF
R65 52.3k
C22 0.01uF
C24 1.0uF
R51 52.3k
RvR
02-09-15
U21
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
C81
4
0.1u
F
R40
844
.2k
R85
21k
C40
8
0.1u
F
C31 0.01uF
R88
44.2
k
C25 0.01uF
JP5
VD
DA
_SE
L
C81
5
10uF
C4051.0uF
R57
26.1
k
RvR
02-09-15
U22
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
C40
9
10uF
R43
26.1
k
RvR
02-09-15
U20
LP38
798S
D-A
DJ/
NO
PB
IC R
EG
LD
O A
DJ
0.8A
12W
SO
N
IN1
IN2
IN_C
P3
CP
4
EN
5
GN
D6
GN
D7
FB
8
SE
T9
OU
T_F
B10
OU
T11
OU
T12
DA
P13
JP6
VD
DA
_SE
L
R40
721
k
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
USB 3V3
SILKSCRN:
USB PWR
Notes:
1.By connecting I2C to the header's pin 1 and 3, this is
to give I2C access to external I2C master;
2.By installing R926 and R927, FTDI can also access Aux
I2C port (also removing R87 and R88). This feature is not
expected to be used.
3.Normal use: FTDI controls I2C port; Header is connected
to Aux port in SPI configuration.
3V3_
FT
DI
1V8_
FT
DI
5V0_
US
B
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
3V3
3V3
3V3
3V3
3V3
CLK
_FT
DI_
PLL
_SC
L_O
D6
FT
DI_
PLL
_SD
A_O
D6
SP
I_S
CLK
6S
PI_
SD
IO6
SP
I_S
DI
6S
PI_
CS
N6
CLK
_LO
CA
L_S
CL_
OD
6LO
CA
L_S
DA
_OD
6
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
94
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
FT
DI U
SB
Int
erfa
ce
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
94
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
FT
DI U
SB
Int
erfa
ce
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
94
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
FT
DI U
SB
Int
erfa
ce
L84
220
08-10-14
EMT
XB
0104
RG
YR
U40
4
IC V
OLT
-LE
VE
L T
RA
NS
LAT
OR
14-
QF
N
DN
S
VC
CA
1
A1
2
A2
3
A3
4
A4
5
NC
16
GN
D7
OE
8
NC
29
B4
10B
311
B2
12B
113
VC
CB
14
GN
D_P
AD
15
C48 0.1uF
GN
DG
ND RK
24-07-13
Y1
AB
M8G
-12.
000M
HZ
-18-
D2Y
-TC
RY
ST
AL
12.0
000M
HZ
20P
PM
4S
MD
13 2 4
C45 0.1uF
C413 0.1uF
EM06-02-13J1
7
5481
9058
9C
ON
N R
CP
T U
SB
MIN
I-B
5P
OS
RA
SM
T
VB
US
1
DA
TA
_N2
DA
TA
_P3
ID4
GN
D5
GN
D_S
HLD
6
GN
D_S
HLD
7
GN
D_S
HLD
8
GN
D_S
HLD
9
C687 10uF
RK
16-08-13
FT
2232
HQ
-RE
EL
U1
IC U
SB
HS
DU
AL
UA
RT
/FIF
O 6
4-Q
FN
GN
D1
OS
CI
2
OS
CO
3
VP
HY
4
GN
D5
RE
F6
DA
TA
_N7
DA
TA
_P8
VP
LL9
AG
ND
10
GN
D11
VC
OR
E12
TE
ST
13
RE
SE
T_N
14
GN
D15
AD
BU
S0
16
AD
BU
S1
17
AD
BU
S2
18
AD
BU
S3
19
VC
CIO
20A
DB
US
421
AD
BU
S5
22
AD
BU
S6
23
AD
BU
S7
24
GN
D25
AC
BU
S0
26
AC
BU
S1
27
AC
BU
S2
28
AC
BU
S3
29
AC
BU
S4
30
VC
CIO
31
AC
BU
S5
32
AC
BU
S6
33
AC
BU
S7
34
GN
D35
SU
SP
EN
D_N
36
VC
OR
E37
BD
BU
S0
38
BD
BU
S1
39
BD
BU
S2
40
BD
BU
S3
41
VC
CIO
42
BD
BU
S4
43
BD
BU
S5
44
BD
BU
S6
45
BD
BU
S7
46
GN
D47
BC
BU
S0
48
VR
EG
OU
T49
VR
EG
IN50
GN
D51
BC
BU
S1
52
BC
BU
S2
53
BC
BU
S3
54
BC
BU
S4
55
VC
CIO
56
BC
BU
S5
57
BC
BU
S6
58
BC
BU
S7/
PW
RS
AV
_N59
PW
RE
N_N
60
EE
DA
TA
61E
EC
LK
62E
EC
S63
VC
OR
E64
GN
D_P
AD
65
C42 0.1uF
DB24-07-14
TP
D4S
012D
RY
RU55
IC 4
CH
ES
D S
OLU
TIO
N W
/CLA
MP
6S
ON
US
BD
_P1
US
BD
_N2
VB
US
6
ID3
GN
D4
NC
5
R38310k
R42
41k
18-03-13
RK
N25
10-6
V0C
-RB
-WD
J4 CO
NN
HE
AD
ER
10P
OS
SM
T V
ER
T 3
0AU
11
33
55
77
99
22
44
66
88
1010
R420 4.7k
R38417.4k
C684
4.7uF
03-09-15
RvR
AD
M71
71A
CP
Z-R
7
U57
IC R
EG
LD
O A
DJ
1A 8
LFC
SP
SS
4
EN
5
VIN
7
VIN
8V
OU
T1
VO
UT
2
SE
NS
E3
GN
D6
GN
DP
AD
9
R38
21k
C688 10uF
08-10-14
EM
TX
B01
04R
GY
R
U40
3
IC V
OLT
-LE
VE
L T
RA
NS
LAT
OR
14-
QF
N
VC
CA
1
A1
2
A2
3
A3
4
A4
5
NC
16
GN
D7
OE
8
NC
29
B4
10B
311
B2
12B
113
VC
CB
14
GN
D_P
AD
15
C41 0.1uF
R38
10
R421 4.7k
C43 0.1uF
D2
LNJ3
47W
83R
A
C411 0.1uF
C690 12pFC685
4.7uF
R422 0DNS
R42
51k
C412 0.1uF
C40 0.1uF
C39 0.1uF
C46 3.3uF
C686 1000pF
C69112pF
C38 0.1uF
R385 12k
R418 4.7k
R4741k
C44 0.1uF
R41
033
L83
220
C47 0.1uF
R423 0DNS
C410 0.1uF
R41
233
R419 4.7k
R41
133
R41
333
SP
I_S
DIO
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
GPIO[0]
GPIO[4]
GPIO[8]
GPIO[1]
GPIO[5]
GPIO[9]
GPIO[2]
GPIO[3]
Note for Silkcreen:
Place GPIO[x] lable close to each
corresponding LED and Test point.
GND
SILKSCRN:
SILKSCRN:
HL
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
GP
IO0
6
GP
IO1
6
GP
IO2
6
GP
IO3
6
GP
IO4
6
GP
IO5
6
GP
IO8
6
GP
IO9
6
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
95
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
RK
DB
RK
27 O
cto
ber
2016
GP
IO L
ED
s
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
95
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
RK
DB
RK
27 O
cto
ber
2016
GP
IO L
ED
s
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
95
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
RK
DB
RK
27 O
cto
ber
2016
GP
IO L
ED
s
TP
10
R43
11k
TP
6
R42
81k
R48
71k
R49
61k
U40
5
DIP
_SW
8
VC
C1
nc1
2
nc2
3
nc3
4
nc4
5
nc5
6
nc6
7
VE
E8
s89
s710
s611
s512
s413
s314
s215
s116
R49
51k
TP
2
R49
21k
R49
91k
R48
81k
R43
21k
TP
11
TP
7
R42
91k
R43
31k
TP
3
D6
LNJ3
47W
83R
A
TP
4
R42
61k
R49
11k
TP
5
R42
71k
D4
LNJ3
47W
83R
A
TP
18
D11
LNJ3
47W
83R
A
R43
01k
D9
LNJ3
47W
83R
A
D8
LNJ3
47W
83R
A
D7
LNJ3
47W
83R
A
D10
LNJ3
47W
83R
A
R50
01k
D5
LNJ3
47W
83R
A
GP
IO0
GP
IO1
GP
IO3
GP
IO4
GP
IO5
GP
IO2
GP
IO8
GP
IO9
GP
IO0
GP
IO2
GP
IO0
GP
IO1
GP
IO3
GP
IO4
GP
IO5
GP
IO4
GP
IO8
GP
IO1
GP
IO5
GP
IO9
GP
IO2
GP
IO3
GP
IO8
GP
IO9
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Place sockets to
match spacing of
through-hole crystal
Place close to
crystal Y3
SILKSCRN:
OSCI
SILKSCRN:
JUMPER IN = WP OFF
SILKSCRN:
RESET
Default Jump
between CM
and EEPROM
JP12~JP15 Default Jump Up
SPI Bus
I2 Bus
SILKSCRN:
JUMPER IN = JTAG
VC
C_G
PIO
_DC
VC
C_G
PIO
_DC
3V3
5V0
VC
C_G
PIO
_DC
CLK
_FT
DI_
PLL
_SC
L_O
D4
FT
DI_
PLL
_SD
A_O
D4
SP
I_S
CLK
4
SP
I_S
DIO
4
SP
I_S
DI
4
SP
I_C
SN
4
CLK
_LO
CA
L_S
CL_
OD
4
LOC
AL_
SD
A_O
D4
PLL
_SP
I_S
CLK
_AU
X
PLL
_SP
I_S
DIO
_AU
X
PLL
_SP
I_S
DI_
AU
X
PLL
_SP
I_C
SN
_AU
X
OS
CI
OS
CO
TS
T_C
HIP
_RS
T_N
_OD
JTA
G_S
EL
PLL
_EE
PR
OM
_SD
A_O
D4PLL
_EE
PR
OM
_SC
L_O
D4
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
96
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
PLL
Cor
e
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
96
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
PLL
Cor
e
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
96
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
PLL
Cor
e
R450 0
JP10
EE
PR
OM
_SE
L
RK
19-03-13
J45
5-18
1483
2-1
15-01-16RvR
0552
-2-1
5-01
-11-
27-1
0-0
P1
DN
S1
R11
733
R47
00
DN
S
C426 0.01uF
04-06-14
RvR
SW
1
KM
R21
1GLF
SS
WIT
CH
TA
CT
ILE
SP
ST
-NO
0.0
5A 3
2V
12 53
4
C76
610
pF
R447 4.7k
RvR
11-11-14
A08
-LC
-TT
P3
IC S
OC
KE
T S
TR
AIG
HT
8P
OS
TIN
11
22
33
44
55
66
77
88
R12
133
R442 10k
R453 4.7k
C417 0.1uF
JP13
EE
PR
OM
_SE
L
Y2
A-5
0.00
0-12
-EX
TC
RY
ST
AL
50M
HZ
12P
F 3
0PP
M H
C49
/U
DN
S
R11
833
R935 4.7k
C415 0.1uF
15-01-16RvR
0552
-2-1
5-01
-11-
27-1
0-0
P2
DN
S
1
R12
233
R454 4.7k
R47
10
DN
S
R446 4.7k
R448 4.7k
R443 10kDNS
R44
91k
C75
91.
0uF
DN
S
R11
933
R455 4.7k
JP14
EE
PR
OM
_SE
L
28-01-14
RvR
U40
8
24LC
64-I
/PIC
EE
PR
OM
64K
BIT
400
KH
Z 8
DIP
DN
S
A0
1
A1
2
A2
3
VS
S4
SD
A5
SC
L6
WP
7
VC
C8
18-03-13
RK
TS
M-1
02-0
1-T
-SV
J83
CO
NN
HE
AD
ER
2P
OS
0.1
IN P
ITC
H S
MD
11
22
18-03-13
RK
TS
M-1
02-0
1-T
-SV
J7 CO
NN
HE
AD
ER
2P
OS
0.1
IN P
ITC
H S
MD
11
22
R444 10k
R46
90
DN
S
R445 1k
C416 0.1uFDNS
C76
510
pF
R452 4.7kDNS
R473 10DNS
JP11
EE
PR
OM
_SE
L
R12
033
JP15
EE
PR
OM
_SE
L
R451 4.7kDNS
NC
1N
C2 DM
25-11-15
Y3
CX
3225
GB
5000
0P0H
PQ
CC
CR
YS
TA
L 50
.000
MH
Z 2
0PP
M 1
8PF
SM
D
13 2 4
EM08-04-14
U40
7
TP
S38
08G
01D
RV
RA
DJ
SU
PP
LYM
ON
ITO
R P
RG
DLY
6Q
FN
CT
3
GN
D5
RE
SE
T_N
6V
DD
1
SE
NS
E2
MR
_N
4
GN
D_P
AD
7
JP12
EE
PR
OM
_SE
L
R46
839
R47
20
DN
S
EE
PR
OM
_SC
L_O
DE
EP
RO
M_S
DA
_OD
PLL
_EE
PR
OM
_SC
L_O
D
PLL
_EE
PR
OM
_SD
A_O
D
EE
PR
OM
_SD
A_O
D
EE
PR
OM
_SC
L_O
D
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SILKSCRN:
CLK0_N
SILKSCRN:
CLK0_P
PLACE NEAR OSCILLATOR
SILKSCRN:
CLK1_N
SILKSCRN:
CLK1_P
SILKSCRN:
CLK OSC
3V3
VD
D_C
LK1
VD
D_C
LK1
CLK
_CLO
CK
0_P
CLK
_CLO
CK
0_N
CLK
_CLO
CK
1_P
CLK
_CLO
CK
1_N
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
97
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
RK
DB
RK
27 O
cto
ber
2016
PLL
Inp
ut C
lock
s
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
97
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
RK
DB
RK
27 O
cto
ber
2016
PLL
Inp
ut C
lock
s
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
97
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
RK
DB
RK
27 O
cto
ber
2016
PLL
Inp
ut C
lock
s
C88
11.
0uF
R7812.67k
C88
51.
0uF
R776 2.67k
13-11-13
RvR
MH
6
MT
G25
0C12
5PP
LAT
ED
MH
250M
IL P
AD
125
MIL
DIA
ME
TE
R
1
20-03-13
RK
Y4
M61
41LF
12.8
MH
ZM
ER
C 9
X7
HO
T C
MO
S 3
.3V
OC
XO
VC
C4
NC
1O
UT
3
GN
D2
R91
20
R14
333
DN
S
13-11-13
RvR
MH
1
MT
G25
0C12
5PP
LAT
ED
MH
250
MIL
PA
D 1
25M
IL D
IAM
ET
ER
1
R76
749
.9
R460 2.67kR771 2.67k
13-11-13
RvR
MH
7
MT
G25
0C12
5PP
LAT
ED
MH
250
MIL
PA
D 1
25M
IL D
IAM
ET
ER
1
L97
220
RK
19-03-13
J21
5-18
1483
2-1
13-11-13
RvR
MH
10
MT
G25
0C12
5PP
LAT
ED
MH
250M
IL P
AD
125
MIL
DIA
ME
TE
R
1
13-11-13
RvR
MH
2
MT
G25
0C12
5PP
LAT
ED
MH
250
MIL
PA
D 1
25M
IL D
IAM
ET
ER
1
R51
149
.9
R91
60
R77
949
.9
R782 2.67k
RK19-03-13
J82
5-18
1483
2-1
13-11-13
RvR
MH
8
MT
G25
0C12
5PP
LAT
ED
MH
250
MIL
PA
D 1
25M
IL D
IAM
ET
ER
1
C196 0.1uF
RK
19-03-13
J22
5-18
1483
2-1
CO
NN
SO
CK
ET
SM
A S
TR
DIE
CA
ST
PC
B
13-11-13
RvR
MH
3
MT
G25
0C12
5PP
LAT
ED
MH
250M
IL P
AD
125
MIL
DIA
ME
TE
R
1
R91
449
.9
RK
19-03-13
J19
5-18
1483
2-1
C195 10uF
13-11-13
RvR
MH
9
MT
G25
0C12
5PP
LAT
ED
MH
250M
IL P
AD
125
MIL
DIA
ME
TE
R
1
13-11-13
RvR
MH
11
MT
G25
0C12
5PP
LAT
ED
MH
250
MIL
PA
D 1
25M
IL D
IAM
ET
ER
1
R7652.67k
13-11-13
RvR
MH
4
MT
G25
0C12
5PP
LAT
ED
MH
250M
IL P
AD
125
MIL
DIA
ME
TE
R
1
C844 0.1uF
C88
21.
0uF
RK
19-03-13
J20
5-18
1483
2-1
TP
19
13-11-13
RvR
MH
12
MT
G25
0C12
5PP
LAT
ED
MH
250
MIL
PA
D 1
25M
IL D
IAM
ET
ER
1
R7752.67k
R7702.67k
13-11-13
RvR
MH
5
MT
G25
0C12
5PP
LAT
ED
MH
250M
IL P
AD
125
MIL
DIA
ME
TE
R
1
C88
71.
0uF
CLK
_EX
T_O
SC
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SILKSCRN:
Q11_P
SILKSCRN:
Q10_P
SILKSCRN:
Q9_P
SILKSCRN:
Q8_P
SILKSCRN:
Q11_N
SILKSCRN:
Q10_N
SILKSCRN:
Q9_N
SILKSCRN:
Q8_N
PLACE PARALLEL
TERMINATIONS
CLOSE TO U58
CLK
_Q8_
P7
CLK
_Q8_
N7
CLK
_Q9_
P7
CLK
_Q9_
N7
CLK
_Q10
_P7
CLK
_Q10
_N7
CLK
_Q11
_P7
CLK
_Q11
_N7
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
98
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
PLL
Out
put C
lock
s
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
98
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
PLL
Out
put C
lock
s
OF
PR
OJE
CT
NA
ME
DR
AW
N
CH
EC
K
DE
SIG
NT
ITL
E
DR
AW
ING
NU
MB
ER
RE
VIS
ION
RE
LE
AS
E D
AT
ES
HE
ET
SU
BT
ITL
E
1.2
SK
-102
80-0
1
IDT
8A34
001
98
Fid
us S
yste
ms
375
Te
rry
Fox D
rive,
Ott
aw
a,
ON
K2K
0J8
Indira3
DB
DB
DB
27 O
cto
ber
2016
PLL
Out
put C
lock
sR761 100
R73
70
R74
60
R752 100
RK19-03-13J7
6
5-18
1483
2-1
RK19-03-13J7
4
5-18
1483
2-1
R734 100 R743 100
RK19-03-13J7
2
5-18
1483
2-1
R75
70
RK19-03-13J7
0
5-18
1483
2-1
RK19-03-13J7
7
5-18
1483
2-1
CO
NN
SO
CK
ET
SM
AS
TR
DIE
CA
ST
PC
B
R74
70
RK19-03-13J7
5
5-18
1483
2-1
CO
NN
SO
CK
ET
SM
A S
TR
DIE
CA
ST
PC
B
R76
40
RK19-03-13J7
3
5-18
1483
2-1
CO
NN
SO
CK
ET
SM
A S
TR
DIE
CA
ST
PC
B
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R73
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R74
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5 5
4 4
3 3
2 2
1 1
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3_5
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9_6
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4_11
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10_7
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DD
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PLL
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C8780.1uF
L107
220
C87510uF
R23
50
C694 0.1uF
C726 0.1uF
R39
20
C724 0.1uF
C731 10uF
L104
220
C727 10uF
L522
0
C87910uF
C722 0.1uF
C871 0.1uF
C96010uF
R87
50
C695 0.1uF
R89
60
L110
220
L422
0
C94510uF
R88
7
0
C699 10uF
C8760.1uF C8800.1uF
C732 0.1uF
C9610.1uF
C959 0.1uF
C728 0.1uF
R88
00
C93910uF
C696 10uF
C700 0.1uF
C9460.1uF
C729 10uF
R89
90
L99
220
C95110uF
L101
220
C697 0.1uF
R89
30
C9400.1uF
C692 10uF
R93
6
0
R88
90
C730 0.1uF
L96
220
C87310uF
C9520.1uF
C698 0.1uF
C733 10uF
L111
220
C87710uF
R88
50
C725 10uF
L100
220
C723 10uF
C958 0.1uF
C693 0.1uF
C734 0.1uF
C8720.1uF
R87
70
R89
0
0
C721 10uF
C8740.1uF
L102
220
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