04/19/23 1

Design for Manufacturability

Prof. Shiyan Hu

shiyan@mtu.edu

Office: EERC 731

204/19/23

Outline

• Manufacturability Basics

• CMP

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oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

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Lithography systems

504/19/23

Lithography Primer: Basics

• The famous Raleigh Equation:

: Wavelength of the exposure system

NA: Numerical Aperture (sine of the capture angle of the lens, and is a measure of the size of the lens system)

k1: process dependent adjustment factor

• Exposure = the amount of light or other radiant energy received per unit area of sensitized material.

• Depth of Focus (DOF) = a deviation from a defined reference plane wherein the required resolution for photolithography is still achievable.

• Animation: http://www.microscopy.fsu.edu/primer/anatomy/numaperture.html

604/19/23

Numerical Aperture

•NA=nsin n=refractive index for air, UB =1. Practical limit ≈ 0.93

•NA increase DOF decrease

• Immersion lithography ? n>1 (e.g., water)

704/19/23

k1

•k1 is complex process depending on RET techniques, photoresist performance, etc

•Practical lower limit ≈ 0.25

•Minimum resolvable dimension with 193nm steppers = 0.25*193/0.93 = 52nm

Source: www.icknowledge.com

804/19/23

Mask versus Printing

0.25µ 0.18µ

0.13µ 90-nm 65-nm

Layout

Figures courtesy Synopsys Inc.

904/19/23

Design Rules Explosion

Number of design rules per process node

0

100

200

300

400

500

600

700

0.35um 0.25um 180nm 150nm 130nm 90nm

1004/19/23

CMP & Area Fill

Area fill feature insertionDecreases local density variation Decreases the ILD thickness variation after CMP

Post-CMP ILD thicknessFeatures

Area fillfeatures

wafer carrier silicon wafer

polishing pad

polishing table

slurry feeder

slurry

Chemical-Mechanical Planarization (CMP)Polishing pad wear, slurry composition, pad elasticity make this a very difficult process step

1104/19/23

Density Control Objectives

Objective for Design = Min-Fill [Wong et al, DAC’00]

minimize total amount of added fill subject to UB on window density variation

1204/19/23

Tiling and its Impact on PD

The Tiling Problem: Given a layout and a CMP model, determine the location and amount of dummy features needed toachieve a planarity target, and then modify the layout accordingly.

1304/19/23

Tiling for ILD (Al Metallurgy)

1404/19/23

Tiling for Copper CMP

1504/19/23

Results from Tiling for STI - I

Density and Post-CMP Topography Simulations for a DSP chip from Motorola:Density and Post-CMP Topography Simulations for a DSP chip from Motorola:

Original: max = 284A Tiled: max = 150A

Topography

Shape

Density

1604/19/23

CMP Topography Variation

• CMP Topography variation – T =HMAX-HMIN..

• Observations– Topography variation

determines the depth of focus in lithography, an important factor of manufacturability.

– Topography variation is determined by the feature density distribution of the circuit layout.

– Feature density distribution varies with shuttle mask floorplans

1704/19/23

OPC/RET-Aware Routing [Huang, DAC’04; Mitra et al, DAC’05]

OPC friendlyNot OPC friendly