Analog and Mixed-Signal Center, TAMU

Vi VoS/Hcircuit

S/H commandVi

Vo

t

t

S/H: S H S H S H S H S

Block Diagram Idealized Response

Sample-and-Hold Circuit

TrackError

Performances of S & H

Realistic Transient Response:

Input &OutputVoltage

t

t

Vin

Vout

Pedestal

Voltage Drift

CK

ta th

S/H Circuit Waveforms and Performance Parameters

tac

ts

tap

H S H

Droop

Vo

Vi

Vi

Vo

Holdstep

Feedthrough

Droop Vo

Vi

Desiredoutput

Design of Track and hold

Performance Definition• Acquisition Time: the required time for the output transient after

the sampling signal.

• Hold Settling Time: the time after the hold signal required for theoutput to settle within an acceptable error.

• Pedestal Error: due to the transition of sample to hold mode.

• Voltage Drift: the rate of discharge of the sampling capacitorduring the hold mode.

• Dynamic Range: the ratio of the maximum and minimum input level,which can be sampled with a given resolution.

Performance Definition• Nonlinearity Error: the maximum deviation of the Vout/Vin

characteristic from the straight line passed through the end points.

• Gain Error: the deviation of the slope of the straight line from unity.

P0

0

VoutQ

G1

Vin

Gain Error= 1 - G

NonlinearityError

Analog and Mixed-Signal Center, TAMU

Track and hold

Performance Definition• Hold Mode Feedthrough: the percentage of the input signal that

appears at the output during the hold mode.

Vin Vout

CK

CS

Cp

S

Parasitic capacitors

Performance Definition

• Aperture Error: the random variation of the turn off time of theswitch results in an uncertain sampling time.

Maximum AllowableAperture Error for 1/2 LSB:

10nsec

1nsec

100psec

10psec

1MHz 10MHz 100MHz 1GHz

6 bits6 bits

12 bits

12 bits

10 bits

10 bits

8 bits8 bits

∆f

fin

1Nin

max2f

1t

+π=∆

t

ApertureError

SamplingError

Vin

Ideal samplingpoint

t

CK

Performance DefinitionPerformance Definition

• Signal-to-Noise Ratio (SNR): the ration of the signal power to thenoise power at the output. The sources of noise are the input andoutput buffer, switch, and clock jitter.

• Signal to Noise + Distortion Ratio (SNDR): the ration of signal powerto the total noise and harmonic power at the output. The source ofharmonics are the nonlinearity of the buffers and the switch.

Vout

nBin nBout

Vin

S

CK

nsw* **

Sample-and-Hold Basic Architectures

Fig. 1 An open-loop track and holdrealized using MOS technology.

Fig. 2 An open-loop track and hold realizedusing a CMOS transmission gate.

( )

( )

hld

SSDDOVOX

hld

intnDDOXC

WLVC

hld

hldC

intnDDtnGSeff

eff

effOXCHC

C

VVWLCV

CVVVWLC

CQ

V

VVVVVV

V

WLVCQQ

hld

effOX

hld

−−≅′∆

−−−=−=

∆=′∆

−−=−=

==∆

−−

−

−

−

2

bygiven is where22

2

11

1

1

1

Analysis

.

. VoutV′

clkφ

clkφ

clkφ

VoutV′

1

1

Vin

Vin

Q1

Q1

Chld

Chld

.clkφ

VoutV′

1VinQ1

Chld

clkφ

. .Q2

Fig. 3 An open-loop track and hold realized usingan n-channel switch along with a dummyswitch for clock-feedthrough cancellation.

1 1

Input Buffer

CH

CK OutputBuffer

SVin Vout

X..

Analog and Mixed-Signal Center, TAMU

Vout

Buffered Sample & Hold CircuitBuffered Sample & Hold CircuitInput and Output Buffer:

The capacitor voltage during the hold mode can be affected by the current drawn by the following circuit. Therefore, the output voltage is buffered.

Bin Bout

Vin

S

CK

Analog and Mixed-Signal Center, TAMU

Unity Gain Buffer Circuit:BJT and CMOS implementations

Vin

M1 M2

M3

VDD

Vout

ISS IF

M4

Vin

Q1 Q2

Q3

Rc

Vcc

Vout

IEE IF

Bipolar Technology CMOS Technology

Track & Hold (T&H) Circuit

VoutGmVin S

CK+

- A+

-V1

V-

Simple Closed-Loop Architecture:

During the sampling time, the drain and source voltage of MOSswitch are closed to ground. Thus the charge injection and clockfeedthrough introduce an offset voltage at the output and isindependent of the input voltage.

Disadvantage: stability problems and low speed.

T&H Circuit: Closed-Loop Architecture

VoutGmVin

CK

+

- A+

-V1

V-

Offset Voltage Cancellation:

The charge injection and clock feedthrough can be cancel out byapplying a replica of the offset voltage to the positive terminalof the second amplifier (common-mode voltage).

Cs

M1

M2CK

T&H Circuit: Switched CapacitorSwitched-Capacitor Architecture:

This architecture consists of sampling capacitor CS, amplifierGm, and MOS switches.

Gm+

-Vin

Vout

CS

Hold Mode (CK=0)

Gm+

-

Vout

CS

Track Mode (CK=1)

Vin

Gm+

-

Vout

CSVin

CK

M2

CK

M3

CK

M1

Vout

Vin

Evolution of S/H Architectures

Vout.

.+

+-

-Gm A0S

CK CH

X

Fig A. Closed-loop sample-and-hold architecture.

. 1Vin

Q1

Chld

φclk

.-+ Vout

Fig B. Including an opamp in a feedback loopof a sample and hold to increase the input impedance.

Vout

. 1Vin

Q1

Chld

φclk

.-+

Q2

Q3

φclk

C. Adding on additional switch to the S/H ofFig B to minimize slewing time.

..

+

+-

-

ChldOpamp 1

Opamp 2

Vin

φclk

φclk Q2

Q1

Fig D An improved configuration for an S/H ascompared to that of Fig C

. 1Vin

Q1

Chld

φclk

.-+

Q2

Q3

φclk

.

Design of Track and hold

T&H Circuit: Current-ModeCurrent-Mode Architecture:

Advantages: high-speed (over 100MHz) and low voltage (<1.2).The speed depends on the time constant given by:

1m

S

g

C=τ

11oxS LW)A1(C32

C •+=

)VV(LW

Cg TnGSox1m −µ=S

CKM2

Iout

VDD

M1

Iin

CS

I AI

CK

Iin

Iout

A1

-

+

+

D1 D2

A2

-

+

RF

+Vo-

CH

+

SW

SwitchdriverS/H

Vi

Two Op Amps S/H Circuit

A1LT118A+

-+

A1LT11010

+

A3LT118A-

+

A4LT118A

+

-

+Vo-

Vi 2kΩ

R1

C150pF

2kΩ

R2

20Ω

R3

VCC

S D

Cds

GCgd

Q12N5432

C3

100pF

CH1nF

R8

5kΩ

C5

10pF R7200kΩ

R9

10kΩ

R10

50kΩ

R116.2kΩ

D26.2V

R72kΩ

D1

HP2810

C2

150pFQ22N2222

VEE

R61kΩ

Q3

2N2907

R5

1kΩS/H

A 5 MHz track-and-hold circuit, using discrete components,with charge compensation to minimize the hold step.

Fig. The clock waveforms for Vin and φclk used to illustrate how a finite slope for the samplingclock introduces sampling-time jitter.

actual1−st

ideal1−stinV

Sampling jitter

clkφ

ideal2−st

actual2−st

Vout.

.+

+-

-

CH

Vin

GmA0

.

..

M1

M2

CK

CK

X

C2

Fig. Closed-loop sample-and-hold architecture with pedestal cancellation.

S/H Open Loop Architecture with Miller Capacitance.

+

-A0.

.

..

CK

VinVout

M1

M2

ZC1

C2

XY

+

-A0.

.

..

Vin Vout

ZC1

C2

X

Y

(a) (b)

+

-A0

.Vout

ZC1

C2

X

Y

(c)Fig. Open-loop architecture with Miller capacitance. (a) Basic circuit; (b) equivalent circuit in

the acquisition mode; (c) equivalent circuit in the hold mode.

The open-loop architecture with Miller capacitance employs two different values of capacitancein the acquisition and hold modes to achieve high speed and small pedestal error. This is accomplished using a Miller amplifier that multiplies the effective value of the sampling capacitorby a large number when the SHA enters the hold mode.

Switched-Capacitor S/H Implementationsφ1

φ2

A switched-capacitor sample and hole and low-pass filter.φ2A

A switched-capacitor S/H.

.

.. . -+

vout

vinC1

C2φ2

φ1

.

.-+vin .

.

-+

...

1

..

.

φ1A

S1

S4

CS

S2φ1B

COF

φ1B

S3

φ2B

S5

CH

Vout

φ2S

S6

φ1BCX

S7

.

MULTIPLEXED-INPUT ARCHITECTURES

. ..

CK

Vin VoutGm1 R

Gm2

CKCH

(a)

Vout

RoutA

XCH

Multiplexed-input architecture. (a) Basic (single-ended) circuit;(b) equivalent circuit in the hold mode.

Fig. 15(a) Dual-loop multiplexed architecture.

Equivalent circuits of dual-loop multiplexed-input architecture. (b) Acquisition mode; (c) hold mode.

Vout

Gm1

R

C2

+

-

-

+

-+

+-.

C1

X

Y

(c)

.Vout.

CK

Vin

Gm1 R

Gm2

CK

C2

+

-

-

+

.

.+

+

-

-

-+

+-

R1

R2

X

.

Y

C1

S1

S2

.

R2

Vout

Vin

Gm1 R

C2

+

-

-

+

-+

+-

R1 .C1

(b)

.

T&H Circuit: Current-Mode

Closed-Loop Current-Mode Architecture:

This architecture needs stability and speed considerations.The distortion of Gm2 affects directly the output current [21].

Gm1

CK

+

- A+

-V-

Cs

M1

Iin Gm2

+

-

CC

Iout

T&H Circuit: Example

BiCMOS Track & Hold Amplifier (12-Bit & 50Msps):This circuit consists of input buffer, hold section, and outputbuffer [3].

CS=3pFCFF is a feed-forwardcompensationcapacitor forthe chargeinjection of Q4

Vout

R5

Q15Q13

R3R2

Q12

R1

Q11

VBB3

GND

Q10Q1

Q2Vin

CFF

Q3

Q4

Q6

Q5

Vcc

VBB2 M2

M1VBB1

CS

CK(Track)

CK(Hold)

R4

Q14

Q7

Q8

M4

M3

D1Q9

RECYCLING S/H ARCHITECTURE

Fig. 16 Recycling architecture.

. .

. .B1 B2

VinVout

S1S5

...

X1

C1

S3

S4

Y1

C2

XY

C3S2

-

+Gm

. .B1 B2

Vin Vout

...

X1

C1

Y1

C2

XY

C3

-

+Gm

(a)

B1 B2

Vout

X1

C1

Y1

C2

XY

C3

-

+Gm

(b)

Fig. 17 Equivalent circuits of recycling architecture. (a) Sampling mode; (b) hold mode.

+Vo-

A1

+

-

+Vi

Offset

A2

-

+

R

VCC

R

CH

Cgd

SW

SW driver

S/H

Integratating Amplifier S/H Circuit

+Vo-

Buffer

+Vi

-

+

R R

CHSW1

SW driver

S/H

SW3

C(=CH)SW2

Improved S/H Circuit

L.Dai and R. Harjani,” CMOS Switched-Op-Amp Based Sample and Hold Circuit,IEEE JSSC, January 2000, pp 109-113

+-

+1

vi

vo

RCgs Cgd

ON

OFF

φ

∆q

M1 Ch

Charge injection and clock feedthrough mechanism

)VV(WLCQ TGSoxch −−=

h

TGSox

h

ch'

C

)VV(kWLC

C

QkV

−−=

⋅=∆

hpara

paraSSDD''

CC

C)VV(V

+

−−=∆

Channel charge in (top) triode and (bottom) saturation

S G D S G DVG

S G D S G DVG

SOP-

++1

Ch

A VoutVin

Switched-Op-Amp-Based S/H Circuit

Vin+

Vin-Gm+

-

+1

Gm+

-

+1

1m

Vout+

Vout-

R1=100k

R2=100k

φ

φ

S1

S2

M14/2

M24/2

Ch1=1p

Ch2=1p

φIb=5u

Vdd=5V

φIb=5u

Vdd=5V

1m

Simplified model of the pseudo-differential SOP-based S/H

GSNNparah

NparaNerr V

CC

CV

+−=

GSPPparah

PparaPerr V

CC

CV

+−=

clk

pbias

M19

M5

M3

M6

M4

M1 M2 VinM8

Vdd

pcas

nbias clk

ncas

M7M16 M12

M10M11

M13 M17

3

2

1M18

M9

Ch

clk

M15

M14Vbuf

Voutclk

Folded cascode switched op-amp in the unity-gain feedback configuration

Simulation results for acomplete cycle of sampled-

and-held waveform

Time(us)

Dif

fere

ntia

l Inp

ut /

Out

put

(V)

Frequency (kHz)

PSD

of

Inpu

t (d

B/H

z)

Simulation results of thespectrum of the sampled-

and-held waveform

[1] U.L. McCreary and P.R. Gray, “All-MOS charge redistribution analog-to-digital conversiontechniques,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 371-379, Dec. 1975.

[2] P. Van Peteghem and W. Sanaen, “Single versus complementary switches: A discussion ofclock feedthrough in SC circuits,” in Proc. 12th Eur. Solid-State Circuits Conf. (ESSCIRC‘86), Delft, the Netherlands, Sept. 1986, pp. 16-18.

[3] C. Eichenberger and W. Guggenbuhl, “Dummy transistor compensation of analog MOSswitches,” IEEE J. Solid-State Circuits, vol. 24, pp. 1143-1146, Aug. 1991.

[4] M. Nayebi and B.A. Wooley, “A 10-bit video BiCMOS track-and-hold amplifier,” IEEE J.Solid-State Circuits, vol. 24, pp. 1507-1516, Dec. 1989.

[5] P.J. Lim and B.A. Wooley, “A high-speed sample-and-hold technique using a miller holdcapacitance,” IEEE Solid-State Circuits, vol. 26, pp. 643-651, Apr. 1991.

[6] G.C. Temes, Y. Huang, and P.F. Ferguson Jr., “A high-frequency track-and-hold stage withoffset and gain compensation,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 559-560. Aug. 1995.

[7] S. Brigati, F. Maloberti, and G. Torelli, “A CMOS sample and hold for high-speed ADC’s,”in Proc. IEEE Int. Symp. Circuits and Systems Circuits and Systems Connecting theWorld, vol. 1, May 1996, pp. 163-166.

[8] J.H. Shieh, M. Patil, and B.J. Sheu, “Measurement and analysis of charge injection inMOS switches,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 277-281, Apr. 1986.

[9] G. Wegman, E.A. Vittoz, and F. Rahali, “Charge injection in analog MOS switches,” IEEEJ. Solid-State Circuits, vol. SC-22, pp. 1091-1097, Dec. 1987.

[10] D. Jons and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.[11] J. Crols and M. Steyaert, “Switched-opamp: An approach to realize full CMOS switched-

capacitor circuits at very low power supply voltages,” IEEE J. Solid-State Circuits, vol. 29, no. 8, Aug. 1994.

References