488 ieee transactions on advanced packaging, vol. 28,...

488 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 3, AUGUST 2005

Sea of Leads Compliant I/O Interconnect ProcessIntegration for the Ultimate Enabling of Chips

With Low-k Interlayer DielectricsMuhannad S. Bakir, Member, IEEE, Bing Dang, Student Member, IEEE, Richard Emery, Gilroy Vandentop,

Paul A. Kohl, Member, IEEE, and James D. Meindl, Life Fellow, IEEE

Abstract—Sea of leads (SoL) process integration for the seriesof steps required to transform a fully intact die at the wafer levelto a die that is assembled onto a board is described. The primarygoal is to address the issues involved in reconciling the fabrica-tion and assembly requirements of compliant leads, such as SoL,with those of standard semiconductor processes and chip assemblytechniques. The effort is motivated in-part by the potential failureof the low-k interlayer dielectric in microprocessors as a result ofhigh mechanical stresses due to the coefficient of thermal expansion(CTE) mismatch between the chip and the board. SoL, and othercompliant interconnections, mitigate this problem by mechanicallydecoupling the chip and the board. While compliant leads offeradvantages over C4 technology, there is much to consider duringthe series of steps needed to transform the fully intact dice at thewafer level to dice that are assembled onto the board. The use ofan encapsulation film over the leads during wafer sawing is shownto be necessary for slippery leads and other free-standing com-pliant leads. The use of a suitable flux when the leads are finishedwith a nickel–oxide nonwettable layer is essential for a successfulwafer-level solder reflow. Successful die assembly using thermo-compression bonding is demonstrated using two different SoL dicewith correspondingly different substrates. The resistance of a chainof 30 cascaded leads is 2.7 .

Index Terms—Compliant leads, input/output (I/O), intercon-nects, low-k, packaging.

I. INTRODUCTION

I N ORDER to improve the electrical performance of mi-croprocessors, semiconductor manufacturers are seeking

to reduce the dielectric constant of the interlayer-dielectricseparating the Cu conductors that form the chip’s multilayerinterconnect network. The processes employed to produce thislow interlayer-dielectric constant material (low-k) also tendto reduce its mechanical strength. In present technology, themechanical strength of the dielectric is low enough that it cancause failure during microprocessor use. The driving force forthis failure is the mechanical stress imparted on the dielectricdue to the thermal expansion mismatch between the silicon

Manuscript received May 25, 2004; revised December 7, 2004. This workwas supported in part by the Microelectronics Advanced Research Corporation(MARCO), its participating companies, and by the Defense Advanced ResearchProjects Agency (DARPA) under Contract 2003-IT-674.

M. S. Bakir, B. Dang, P. A. Kohl, and J. D. Meindl are with the Microelec-tronics Research Center, Georgia Institute of Technology, Atlanta, GA 30332-0269 USA (e-mail: [email protected]).

R. Emery and G. Vandentop are with Intel Corporation, Chandler, AZ 85248USA.

Digital Object Identifier 10.1109/TADVP.2005.848386

die and the composite substrate (often engineered to be expan-sion-matched to copper) as the system goes through thermalexcursions. Therefore, architectural changes that minimize thisstress are attractive.

This paper presents results from the process integration ofsea of leads (SoL) [1]–[3] compliant I/O interconnections withan Intel chip. SoL provides compliant electrical I/O intercon-nects, which interconnect a die to a board while decoupling thedeformations of the two. This decoupling is accomplished bydesigning the leads to behave as mechanical springs. Variousapproaches to compliant interconnections have been describedin the literature [1]–[15]. The primary goal of the research wasto study the issues involved in reconciling the fabrication andassembly requirements of compliant leads, such as SoL, withthose of standard semiconductor processes and standard chipassembly techniques. The chips used for these experiments areone of Intel’s test chips used to characterize the reliability ofvarious interconnections. The on-chip interconnects are Cu, andthe uppermost layer on the chips is a polymer.

Process integration of SoL with the Intel chip is described inSection II. Section III describes the issues involved in selectinga suitable flux for SoL. Wafer sawing issues are described inSection IV. Finally, the use of thermocompression bonding tomitigate the solder height variation on the board is described inSection V. Section VI is the conclusion.

II. FABRICATION FEATURES

The key features of SoL fabrication are described in this sec-tion (Fig. 1). Intel supplied several 8-in Si wafers. Each 8-inwafer was sawed into rectangular pieces (70 60 mm) to ac-commodate the substrate size limitation of the mask aligners atGeorgia Tech. SoL (without embedded air gaps) was fabricatedon the Si pieces using the processes described in [1], [2]. How-ever, there were some important differences. The leads were fab-ricated above the top-most polymer film of the wafer [Fig. 1(a)].Thus, the first process step was to sputter a seed layer [Fig. 1(b)].All but one Si piece were coated with a Ti/Au/Ti (300 Å/0.2

m/300 Å) seed layer using a dc sputterer. The remaining Sipiece was coated with a seed layer that yielded slippery leads[1]. Slippery leads are designed and fabricated to have no adhe-sion with the underlying polymer to enhance their mechanicalflexibility [1]. The method used to fabricate the slippery leadswas identical to the one described in [1], where titanium islandswere first patterned over the vias followed by a gold blanket

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BAKIR et al.: SEA OF LEADS COMPLIANT I/O INTERCONNECT PROCESS INTEGRATION 489

Fig. 1. Schematic of the process used to fabricate SoL. (a) Si wafer as received(die pads are exposed through polymer film). (b) A seed layer is deposited andthe gold leads are electroplated. (c) Nickel is electroplated above the gold leadsand oxidized. (d) Before the solder balls are electroplated on the tip of each lead,the nickel–oxide film is etched. Finally, the seed layer is etched to electricallyisolate the leads.

coating. Following seed layer deposition and resist patterning,the leads were electroplated [Fig. 1(b)]. The total thickness ofthe leads was 10 m. An 8- m-thick gold layer was electro-plated into the resist cavity followed by a 2- m nickel layerto create a nickel over gold lead with no nickel sidewall cov-erage on the gold portion of the lead [Fig. 1(c)]. The same resistlayer used to electroplate the gold layer was also used to electro-plate the nickel layer. The photoresist used during the electro-plating process is NR9–8000 (manufactured by Futurrex) andis spin coated to a 12- m thickness. The purpose of the nickellayer in this paper is two fold. First, nickel provides an excel-lent under bump metallization. Second, heavily oxidized nickelfilm around the solder bumps provides a simple method of con-fining the solder during reflow and assembly. After the leadswere plated, the rectangular Si pieces were placed in a Plas-maTherm RIE and exposed to an O -rich plasma for approxi-mately 10 min. The seed layer was not etched prior to this stepto protect the chip’s underlying polymer during RIE. Fig. 2 is amicrograph of the Intel chip after the leads were electroplated. Aresist layer (NR9–8000, Futurrex) was spin coated next on therectangular Si pieces and patterned such that vias were fabri-cated at the bump end of the leads. Next, the nickel–oxide layerwas etched to prepare the surface for solder deposition. Fol-lowing the wet etch, the samples were placed in a solder platingsolution, where 60/40 Sn/Pb solder bumps were plated to an ap-proximate height of 30 m [Fig. 1(d)]. Following the platingprocess, the seed layer was etched.

Fig. 3 illustrates a set of leads with a solder bump on each oftheir tips.

III. SELECTION OF FLUX

Once SoL was fabricated, the Si pieces were shipped backto Intel where dicing of the individual chips and assembly tookplace. The first task was to experiment with solder reflow. If theflux is too aggressive, the nickel–oxide layer will be removed,and the solder will wick the entire lead. Fig. 4 is a micrographof a set of leads after being placed in a reflow oven when no flux

Fig. 2. Die micrograph of the Intel chip after fabrication of the compliant leads(no solder bumps).

was dispensed on the sample. The bumps do not show evidenceof a good reflow, as expected. On the other hand, Fig. 5 is a mi-crograph illustrating the bumps when an organic flux was usedduring the reflow process. The bumps are spherical in shape andare confined to the tips of the leads, as desired. Finally, Fig. 6is a micrograph illustrating the consequences of using a moreaggressive acid-based flux. It is clear that this flux is too aggres-sive because it removed the nickel–oxide layer. This caused thesolder to wick most of the lead. Such an event would preventthe successful assembly of chips. All reflow operations wereperformed in a nitrogen environment and at a peak temperatureof 220 C. The above discussion underscores the difficulty ofcontrolling solder when metallic compliant leads are used. Themetal used to fabricate the leads is typically selected from me-chanical and electrical performance perspectives. If the leadsare completely encapsulated with a dielectric, as is done foron-chip interconnects, the leads would lose their ability to me-chanically deform. Thus, the solder barrier should be integratedwith the lead without adversely affecting its mechanical proper-ties. Other methods of containing the solder during reflow, suchas the use of a polymer dam on the leads [1], could have beenused instead. The nickel–oxide approach was used in this workbecause its processing was more established at the time of theexperiments.

IV. COMPATIBILITY WITH WAFER SAWING

A. Encapsulation of the Leads

Once a suitable flux was selected, the next issue was thedicing of a wafer with compliant leads on its surface. High-pres-sure deionized (DI) water is used during the sawing process. Asa result, it was important to somehow protect the leads fromthe high-pressure water stream. This led to encapsulating theleads with a material during the sawing process. This materialhad to meet the requirements of being transparent to allow thealignment of the saw to the saw streets on the wafer. Moreover,the material had to be easily removable. Some of the thick re-sists used in typical MEMS fabrication were the first candidatesfor use as the encapsulating material. However, most were not


Fig. 3. SEM images of leads with solder bumps on each of their tips as fabricated on the wafer.

Fig. 4. Micrograph of solder bumps on the tips of the leads after reflow. Noflux was used in this case.

Fig. 5. Micrograph of solder bumps on the tips of the leads after reflow. Anorganic flux was dispensed on the sample prior to reflow. It is clear that thesolder is confined at the tips of the leads.

sufficiently transparent to the vision system used on the sawingequipment. In addition, most could only be removed through adry etch.

Fig. 7 is a schematic illustrating how the wafer was sawedafter being encapsulated. First, the saw was used to cut throughmost of the encapsulating material. Next, the saw was used toscribe 70 m into the wafer. Finally, a third saw singulated thedice. It was important to also select a material that is soft enoughto absorb the stress induced during the sawing process.

Fig. 8 compares the results of sawing on two different encap-sulating materials. Based on the listed requirements, the mate-

Fig. 6. Micrograph of solder bumps on the tips of the leads after reflow. Amore aggressive flux (acid-based) was dispensed on the sample prior to reflow.It is clear that the solder wets most of the lead.

Fig. 7. Wafer sawing details.

rial (GenTak 130) shown in Fig. 8(b) was selected as a suitablematerial to encapsulate the wafer. The use of the encapsulatingmaterial was especially needed for the slippery leads [1], [2].Most of the “adhered” leads were fully intact after dicing, evenwithout an encapsulation layer. However, many of the slipperyleads delaminated from the wafer or were damaged when noencapsulation layer was used during dicing. When an encap-sulation layer was used with the slippery leads, the leads wereunaffected by the high-pressure DI water.

B. Saw Street Shifting

An issue encountered during the sawing process was sawstreet reduction. This problem is illustrated in Fig. 9 and can bedescribed as follows: the compliant leads at the edges of the die


Fig. 8. This figure illustrates the importance of selecting a suitableencapsulating material during wafer sawing. (a) Illustrates results from usingone material. It is clear that severe damage was caused to the material.(b) Illustrates the results of sawing using a different material (GenTak 130).

Fig. 9. Schematic illustrating the saw street reduction problem.

Fig. 10. Micrograph of the sawed streets.

extend beyond the active region of the die. As a result, they ex-tend well into the saw streets between the dice. Since we did notconsider wafer dicing during the layout design, this problem wasdiscovered during the sawing process. To compensate for thisproblem, the positions of the saw streets were slightly shifted.Fig. 10 is a micrograph of the sawed streets after being shifted.This solution prevented the need to redesign the layout.

V. SOL ASSEMBLY

Following wafer sawing, the next task was assembly. Whileassembly of the Intel dice was done at Intel, dice with a differentlead pattern and density were bonded at Georgia Tech in order

Fig. 11. Schematic illustrating the process flow diagram ofthermocompression bonding and the two bonding profiles.

Fig. 12. Micrographs of the die and board after assembly and applicationof shear force on the assembled die under the second bonding profile. Themicrographs illustrate that the leads made good contact with the bumps on theboard. (A segment of each lead remained attached to the bumps on the PWBafter the die was sheared off.) Above results are for a chip with adhered leads.

to expedite the research study. In this section, we report bothsets of results.

Two types of boards were used for the SoL Intel die attach-ment; one with and one without solder bumps. The height vari-ation of the solder bumps on the board was relatively large.Even the boards without solder bumps were nonplanar. As aresult, when the chips were flip-chip bonded (with no appliedforce during solder reflow), only a few leads made contact withthe solder/pads on the board. In order to compensate for thisproblem, thermocompression bonding was used. The completebonding profile is illustrated in Fig. 11. The peak bonding tem-perature was 220 C. The organic flux described previously was


Fig. 13. Layout of the board used for the interconnection of SoL dice.

Fig. 14. Photomicrograph of an SoL Si die bonded to a glass substrate with a layout shown in Fig. 13.

coated on the PWB. Next, the SoL chips were bonded using ther-mocompression. The SoL chips used for this experiment con-tained leads without solder bumps on their tips. Instead, the tipsof the leads were coated with a gold finish (0.2- m thick). Thediameter of the gold finish was exactly equal to the solder bumpdiameter (40 m). The gold finish was sputtered on the waferand patterned using a subtractive process. A suitable bondingprofile, which consists of both temperature and force, had tobe identified. As a result, two different bonding profiles weretested. The difference between the two profiles is the time du-ration at the peak temperature, as shown in Fig. 11. In orderto characterize the mechanical interconnection of the leads andthus, the chip to the solder bumps on the PWB, a shear force wasapplied on the chips following their attachment. Fig. 12 illus-trates the die and board after detachment. Each lead broke intotwo segments as a result of the applied shear force. These ex-periments confirm that mechanical interconnection was attainedbetween the SoL chip and the board.

Similar results were attained from the dice bonded at GeorgiaTech. Each die contained 922 leads distributed in an area arrayover 1 1 cm . The leads were fabricated such that they wereslippery [1]. The solder bumps fabricated above the leads were50 m in diameter and 30 m in height. The solder bumps(60/40 SnPb) were electroplated. The height variation of thebumps electroplated on the leads was less than 3 m. The leads

were approximately 220 m in length and 30 m in width. Theleads were interconnected in pairs by metallic interconnects atthe die level. The board layout contained the complementaryinterconnects between the board pads such that the leads couldbe cascaded together in rows. Each row contained a total of 30leads. A total of 27 rows were inspected after the assembly ofeach die. Fig. 13 illustrates the board layout. The copper pads onthe board were 150 150 m large and 1- m thick. The soldermask used on the board is a 10- m-thick film of the photodefin-able polymer Avatrel 2000P (Promerus, LLC). Vias of diameter50 m (same diameter as bumps on the leads) were fabricatedat the center of the bonding pads. The large test pads shownin Fig. 13 were used to electrically test each row. The boardsused in this experiment were glass substrates. This choice ofsubstrate was partly due to the optical transparency of glass,which allows for simple inspection of the bonded leads. Themaximum bonding temperature was 220 C, and the peak ap-plied load during bonding was 100 g. Figs. 14 and 15 are pho-tomicrographs of a Si SoL die bonded to the glass substrate pat-tern shown in Fig. 13. Electrical testing confirmed the intercon-nection of the chain of leads. More than ten SoL chips wereassembled. For each of the assembled chips, more than 20 outof the 27 rows of cascaded leads had an electrical resistanceof 2.7 , which agrees with the calculated resistance. The mea-sured resistance of the remaining rows was greater than 200 k ,


Fig. 15. High magnification image of the bonded die shown in Fig. 14.

indicating an open. Random defects in the fabrication are themain cause of the opens.

VI. CONCLUSION

This paper has described the process integration of sea ofleads (SoL) chip I/O interconnections with an Intel chip. Theprimary objective of this research was to investigate how to rec-oncile the fabrication and assembly requirements of compliantleads, such as SoL, with those of standard semiconductor pro-cesses and standard chip assembly techniques. The leads werefabricated using the processes described in [1] and [2]. Goldleads with a nickel–oxide nonwettable top surface were fabri-cated to confine the solder bumps to the tips of the leads. It wasexperimentally verified that the use of the proper flux duringsolder reflow and assembly was essential in preventing solderfrom alloying the entire surface of the leads. The use of an en-capsulating film over the leads during wafer sawing was nec-essary for the slippery leads. Finally, using thermocompressionbonding, SoL dice were successfully attached to boards.

REFERENCES

[1] M. Bakir, H. Reed, H. Thacker, C. Patel, P. Kohl, K. Martin, andJ. Meindl, “Sea of leads (SoL) ultrahigh density wafer-level chipinput/output interconnections for gigascale integration,” IEEE Trans.Electron Devices, vol. 50, no. 10, pp. 2039–2048, Oct. 2003.

[2] M. Bakir, H. Reed, A. Mule, J. Jayachandran, P. Kohl, K. Martin, T.Gaylord, and J. Meindl, “Chip-to-module interconnections using “Seaof leads” technology,” MRS Bull., vol. 28, no. 1, pp. 61–67, Jan. 2003.

[3] M. Bakir, B. Dang, R. Emery, G. Vandentop, K. Martin, P. Kohl, and J.Meindl, “Chip integration of Sea of leads compliant I/O interconnectionsfor the ultimate enabling of chips with low-k interlayer dielectrics,” inProc. Electronic Components Technol. Conf., 2004, pp. 1167–1173.

[4] M. Bakir and J. Meindl, “Sea of polymer pillars electrical and opticalchip I/O interconnections for gigascale integration,” IEEE Trans. Elec-tron Devices, vol. 51, no. 7, pp. 1069–1077, Jul. 2004.

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[9] D. Smith, D. Fork, R. Thornton, A. Alimonda, C. Chua, C. Dunnrowicz,and J. Ho, “Flip-chip bonding on 6-�m pitch using thin-film microspringtechnology,” in Proc. Electronic Components Technol. Conf., 1998, pp.325–329.

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[14] G. Gardner, B. Harkness, E. Ohare, H. Meynen, M. Bulcke, M. Gon-zalez, and E. Beyne, “Integration of a low stress photopatternablesilicone into a wafer level package,” in Proc. Electronic ComponentsTechnol. Conf., 2004, pp. 170–174.

[15] R. Fillion, R. Wojnarowski, H. Colc, and G. Claydon, “On-wafer processfor stress-free area array floating pads,” in Proc. Int. Symp. Microelec-tronics, 2001, pp. 100–105.

Muhannad S. Bakir (S’99–M’04) received theB.E.E. degree (summa cum laude) from AuburnUniversity, Auburn, AL, in 1999 and the M.S.E.E.degree and the Ph.D. degree in electrical and com-puter engineering from the Georgia Institute ofTechnology (Georgia Tech), Atlanta, in 2000 and2003, respectively.

He is currently a Research Engineer II at theMicroelectronics Research Center, Georgia Tech.His primary area of interest is developing long-termintegrated electrical and optical I/O interconnection

and packaging technologies for gigascale integration. He has published morethan 20 refereed and invited publications that have appeared in conferenceproceedings and journals.

Dr. Bakir is a recipient of the Georgia Tech President’s Fellowship(1999–2003) and the Intel Ph.D. Fellowship (2002–2003). The awards hereceived while at Auburn include IEEE’s most outstanding graduating seniorfrom Auburn’s Department of Electrical and Computer Engineering in Spring1999 and the International Engineering Consortium’s William L. EverittStudent Award of Excellence in 1999. He was also on the Engineering Dean’sHonor List for ten quarters. He has been awarded a MARCO Inventor Recogni-tion Award (2002) and is a recipient of the Best Conference Paper Award fromthe 2002 Electronic Components and Technology Conference (ECTC).


Bing Dang (S’01) received the B.S. and M.S.degrees in metallurgical physical chemistry fromthe University of Science and Technology Beijing,Beijing, China, in 1995 and 1998, respectively, andthe M.S. degree in materials engineering and theM.S. degree in electrical and computer engineeringfrom Auburn University, Auburn, AL, in 2000 and2002, respectively. He is currently pursuing thePh.D. degree in electrical and computer engineeringat the Georgia Institute of Technology, Atlanta.

His primary research interest is the integrated in-terconnection and packaging technologies for gigascale integrated circuits. Hehas published eight papers in journals and international conference proceedings.He received an Auburn University Graduate Research Fellowship (1998–2002).

Mr. Dang was recognized as an outstanding graduate student in the Collegeof Engineering, Auburn University (1999–2000).

Richard Emery, photograph and biography not available at the time ofpublication.

Gilroy Vandentop, photograph and biography not available at the time ofpublication.

Paul A. Kohl (A’92–M’03) received the B.S. degreefrom Bethany College, Bethany, WV, and the Ph.D.degree from the University of Texas, Austin, in 1974and 1978, respectively.

He was with AT&T Bell Laboratories, MurrayHill, NJ, from 1978 to 1989. He is currently Regents’Professor of Chemical Engineering at the Georgia In-stitute of Technology, Atlanta. His research interestsinclude materials and processing for microelectronicdevices and electrochemical engineering.

James D. Meindl (M’56–SM’66–F’68–LF’97)received the Bachelor’s, Master’s and Doctor’sdegrees in electrical engineering from the CarnegieInstitute of Technology, Carnegie-Mellon University,Pittsburgh, PA.

He is the Director of the Joseph M. Pettit Micro-electronics Research Center and the Joseph M. PettitChair Professor of Microelectronics at the GeorgiaInstitute of Technology, Atlanta. He is also Directorof the Interconnect Focus Center, a multiuniversityresearch effort managed jointly by the Microelec-

tronics Advanced Research Corporation and the Defense Advanced ResearchProjects Agency for the Department of Defense. His current research interestsfocus on physical limits on gigascale integration and nanotechnology.

Prof. Meindl is a Life Fellow of the American Association for the Advance-ment of Science and a Member of the American Academy of Arts and Sciencesand the National Academy of Engineering. In September 2004, he was presentedwith the 2004 SRC Aristotle Award, recognizing outstanding teaching in itsbroadest sense. He was awarded first place on the IEEE International Solid StateCircuits Conference 50-Year Anniversary Author Honor Roll, 2003. He receivedthe Georgia Institute of Technology 2001 Class of 1934 Distinguished ProfessorAward, the IEEE Third Millenium Medal in 2000, the 1999 SIA University Re-search Award, and the 1997 Hamerschlag Distinguished Alumnus Award fromCarnegie-Mellon University.

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