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ABSTRACT

A Low Noise Amplifier (LNA) with operating frequency range

between 4.05 GHz to 4.15 GHz is designed as part of the ground

station receiver that recovers 16QAM modulated satellite signals. A

link budget is performed to determine the LNA gain and the noise

figure needed to achieve the required BER. Subsequently Cadence

Design Tool is used to design the LNA. The results shown in the

paper are from Cadence simulation.

INTRODUCTION

Downlink signals are sent from a satellite to a designated ground

station. Due to rain and space losses, the signals at ground station

receiver input are expected to be very weak, approximately -62.4

dBm according to the system link budget. The signals must be

amplified properly so that an acceptable BER of 10-7 could be

achieved at the output of the analog front end. Thus a reliable LNA

with low noise figure and proper gain is designed to support this

operation. Since the LNA is the first device after the antenna feed, its

gain and noise figure must be carefully designed to satisfy the

receiver BER requirement for 16QAM. A link budget is first

performed to determine the maximum LNA noise figure and

minimum LNA gain needed to accomplish this objective. A separate

gain noise figure budget is also done to determine overall system

noise power. Next various types of LNAs were selected to compare

their performances. Finally Cadence design tool is used to implement

and simulate the selected design.

The LNA design constraints are following: Vdd must equal to 1.8 V;

power consumption is less than 10mw; Center frequency of data

transmission is at 4.1 GHz; input VSWR ratio should be 1.5:1;

output VSWR ratio should be 2:1, and IIP3 should be greater than -5

dBm. The Cadence simulation results demonstrate that we almost

meet all design specifications. In addition, the designed LNA also

meets the required BER for the 32 QAM modulation scheme.

DESIGN AND METHODOLOGY

The project fulfillment can be divided into two inter-dependent parts:

a systems-level (Link-Budgeting) and a circuits-level part (LNA

design).

A link budget is first created to determine the necessary gain and

noise figure of the LNA. Table 1 shows the overall ground station

link budget. This budget is for the 16-QAM modulation scheme.

Table1: Ground Station Receiver Link Budget

Table 2: Noise Link-Budget

Rec Antenna Ant. Feed LNA BPF 1 Mixer BPF2 AMP BF3

Gain (dB) 15.8 -0.1 10 -3 -6 -2 20 -5

Gain (linear) 38.02 0.98 10.00 0.50 0.25 0.63 100.00 0.32

NF (dB) 0.1 6 3 6 2 8 5

NF (linear) 1.02 3.98 2.00 3.98 1.58 6.31 3.16

Noise Temp 430 430 290 290 290 290 1540 290

Total Rec NF 12.13

Total Rec NF (dB) 10.84

Sys Noise Temp 2771.0 3657.0

Sys Noise Temp (dB) 34.4 35.6

The link budget shown above is based on the receiver gain and noise

figure budget shown in Table 2. The above table shows that the LNA

must have at least 10 dB gain and a noise figure no greater than 6 dB

in order to close the link. After the link budget is generated and

verified, various types of LNA designs are studied. Eventually a

single-ended Cascode LNA with inductive source degeneration

similar to the one shown in Figure 1 is selected for this task.

4.1 GHz Ground Station Low Noise Amplifier

Design

Raghuram Kamath, Bo Huang

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Figure 1: Cascode LNA [1]

In this design, three NMOS transistors of 0.18 um technology are

used with M3 functioning as the current mirror. The advantages of

using this Cascode design are low noise figure and reasonably high

gain. The inductors shown in Figure 1 are modeled with the inclusion

of parasitic resistance. The first parameter determined is transistor

width. Small signal analysis is then performed to determine other

transistor parameters such as Cgs and Lgs [2]. Finally the transducer

gain and noise figure of the LNA are determined. After all of the

LNA parameters are computed, Cadence was used to model and

simulate the LNA design.

SIMULATION AND RESULTS

Given below are the simulation results using the SpectreRF simulator

tool of Cadence.

Figure 2: Plot of GT (Transducer Gain)

Figure 3: Plot of GP (Power gain)

Figure 4: Plot of NF (Noise Figure)

Figure 5: Plot of the input port VSWR (VSWR1)

Figure 6: Plot of the output port VSWR (VSWR2)

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Figure 7: Plot of IIP3

Figure 8: Plot of all the parameters of interest

We can also see that the BER requirement of the modulation scheme

of 32 QAM is also satisfactorily attained, albeit with a small link

room. The following table shows the link budget in the case of 32

QAM. Note that the transmitter antenna gain has been increased to

58dB.

Table 3: Link-Budget of 32QAM scenario

DISCUSSION AND CONCLUSION

The schematic of the LNA and the test bench is given below:

Figure 9: LNA schematic

Figure 10: Test Bench schematic

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In conclusion, the constraints and the simulated values are compared

in the following table:

The LNA design satisfactorily achieved the task of implementing a

system with a BER of 10-7 in a 6.2Mbps channel, in both, 16 QAM

and 32 QAM scenarios.

Since the frequency of operation of the cellular systems in North

America is lower than 4.1 GHz, we need to make changes in the

system design. The bandwidth of each channel needs to be decreased,

since the cellular system has to support a lot of simultaneous traffic,

even if frequency is reused. Depending on the system, there may be a

soft-limit on the maximum number of traffic supported by each band.

Due to the traffic, there is a rise in the noise floor and hence the LNA

has to deal with more noise as contributed by the channel, and hence

this degrades the system performance. The LNA, for its proper

operation has to be operated in the saturation region. This becomes

more difficult to maintain if there are a lot of disturbances. It may be

possible that the LNA might give different gains for different

incoming signals and hence a AGC (Automatic Gain control) may

have to be used with the design.

Overall, this design is not ideal for the cellular operations, since it

may have to deal with issues it may not counter. This design was a

specific one, with hard constraints, hence we could simulate this

fairly reasonably well. However in a real cellular environment, this

would not be very feasible to implement.

BIBLIOGRAPHY AND REFERENCES

[1] Rashad. M. Ramzan, Tutorial-2, CMOS Low Noise Amplifier

Design.

[2] Thmoas H. Lee, “The Design of CMOS Radio-Frequency

Integrated Circuits”, 2nd edition, pp384-386.

[3] Sungkyung Park and Wonchan Kim, “Design of a 1.8 GHz low-

noise amplifier for RF front-end in a 0.8,”Consumer Electronics,

IEEE Transactions on, vol. 47, no. 0098, 2001.

[4] D. K. Shaeffer, T. Lee, “A 1.5V, 1.5GHz CMOS Low Noise

Amplifier,” IEEE Journal of Solid-State Circuits, vol. 32 no.5

May 1997.

[5] B. Razavi, R.H. Yan, K.F. Lee, “Impact of Distributed Gate

Resistance on the Performance of MOS Devices,” IEEE

Transactions on Circuits and Systems - I: Fundamental Theory

and Applications, vol. 41, no. 11, Nov. 1994.

[6] B. Razavi, “CMOS Technology Characterization for Analog and

RF Design,” IEEE Journal of Solid-State Circuits, vol. 34, no. 3,

March. 1999.