4 instruction set architectures
TRANSCRIPT
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Instruction SetArchitectures
Source:
Null and Lobur. The Essentials of Computer Organization andArchitecture. Chapter
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!hat distinguishes instruction sfrom each other"• Operand storage:
• Stac# structure
• $egisters
• %oth
• Number of e&plicit operands per instruction
• Operand location 'combination of operands allo(ed per instruction)• $egister*to*register
• $egister*to*memor+
• ,emor+*to*memor+
• Operations• T+pes of operations
• !hich operations are allo(ed to access memor+
• T+pe and size of operands• Addresses
• Numbers- or
• Characters"
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esign decisions
•Instruction set must match the architecture
• /actors• Amount of space a program re0uires
• Comple&it+ of the instruction set• Amount of decoding necessar+
•Comple&it+ of the tas#s performed b+ the instruction
• Length of the instructions
• Total number of instructions
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Trade*o1s
•
Short 2s. long instructions• Short:
• less space and fetched 0uic#l+
• Limits the number of instructions as (ell as the size and number of operands
• /i&ed length 2s. 2ariable length• Easier to decode but (aste space
• ,emor+ organization a1ects instruction format
• E.g. Is the memor+ b+te*addressable"
• /i&ed length but e&pandable (hen it comes to the number of operands 'e&paopcode)
• Number of addressing modes
• %ig*endian or little*endian"
• 3o( man+ registers"
• 3o( should the+ be organized"
• 3o( should operands be stored in the C45"
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Internal storage in the C45
• Three possible choices in ho( to store data in the C45• Stac# architecture
• operands are in a stac# '(ith operands at TO4)
• /acilitates e2aluation of e&pressions
• No random access- therefore code produced is ine6cient
• Stac# causes a bottlenec#
• Accumulator architecture
• One operand is implicitl+ in the accumulator
• $educes comple&it+
• ,emor+ tra6c is high
• 7eneral*purpose register '74$) architecture
• Longer fetch and decode times
• 5seful for machines (ith slo( memories
• Three t+pes
• ,emor+*memor+
• $egister*memor+
• Load*store
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Number of operands and instrulengths• /i&ed length
• !astes space
• /ast
• %etter performance (hen pipelining is used
• 8ariable length• ,ore comple& to decode
• Sa2es storage space
• Compromise: t(o or three instruction lengths. Instruction lengths must be cthe (ord length of the machine. If unaligned- space is (asted.
• Common instruction formats• Opcode onl+
• Opcode 9 address
• Opcode 9 ; addresses
• Opcode 9 < addresses
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Comparison of architectures=treatment of opcodes•
Stac# architecture• Opcodes ta#e operands from top of stac#
• Intermediate results are put in top of stac#
• 4ro2ides a mechanism for parameter passing
• $e0uire a 45S3 and a 4O4 instruction- both of (hich are allo(ed a operand >
• 45S3 > retrie2es a data 2alue from memor+ > and places it at TO4 of stac#.
• 4O4 > retrie2es remo2es the element at the TO4 of stac# and puts it in memo
• E6cient for e2aluating long arithmetic e&pressions in re2erse 4olish'$4N) a#a postfx notation
• Onl+ certain instructions are allo(ed to access memor+? all instructuse operands from the stac#.
• ,ost instructions contain onl+ opcodes.
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E&panding opcodes
•
Number of operands is dependent on the instruction length• Not all instructions ha2e the same number of operands.
• E&panding opcodes: compromise solution bet(een rich set opcodes 'opcodes (hich contain a comple& set of instructioha2ing short opcodes
• Short opcode: man+ operands
•
$ich set: all the bits can be used for uni0ue instructions• E&le: @*bit instruction format ma+ ha2e at least t(o po
• *bit opcode follo(ed b+ three *bit addresses '(here the addressregister and there are @ registers)
• *bit opcode follo(ed b+ a ;*bit address '(here the address ma+memor+ location).
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E&panding opcode: E&le
•
SpeciBcations 'instruction format has @ bits)• instructions (ith three addresses
• instructions (ith t(o addresses
•
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An implementation of thespeciBcations•
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!hat if the speciBcations are:
•
;*bit instruction format• There are D registers.
• Instructions cannot access memor+ directl+.
•
!ill these support• instructions (ith < registers
• ; instructions (ith register
• @ instructions (ith registers
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Instruction T+pes
• ata ,o2ement
• Arithmetic Operations
• %oolean Logic Instructions
• %it ,anipulation Instructions
• InputFOutput Instructions
• Instructions for Transfer of Control
• Special 4urpose Instructions
Orthogonalit+• No redundanc+ in instructions
• Instruction set must be consistent
• Addressing modes of operands must be independent from the operands
• Conse0uences:• /acilitates language compiler construction
• Long instruction (ords
• Longer programs
• ,ore memor+ use
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Address ,odes
•
Immediate addressing: 2alue follo(s the opcode• irect addressing: 2alue obtained b+ the speciBed m
address in the instruction• $egister addressing: register is used to specif+ the operan
• Indirect addressing: bits in the address Beld specif+ a•
$egister indirect addressing: register contains the pointer• Inde&ed addressing: inde& register is used to store a
added to the operand• %ased addressing: a base address register is used to store
• Stac# addressing: operand is assumed to be on the s
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8ariants of pre2ious addressingmodes•
Indirect inde&ed addressing: Indirect and inde&eaddressing are used at the same time
• %aseFo1set addressing: Adds an o1set to a specregister and adds this to the speciBed operand Ga pointerH- leading to the address of the actual oto be used in the instruction.
• Auto*increment and auto*decrement: automaticincrements or decrements the register used- thureducing the code size
• Self*relati2e addressing: computes the address o
operand from the current operation
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4ipelining
•
/etch*decode*e&ecute: normall+ each cloc# pulse controls a• !hat if the steps are bro#en do(n into smaller steps- and so
can be performed in parallel"• ,inisteps:
. /etch instruction
;. ecode opcode
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3o( pipelining (or#s
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle Cycle ! Cycle
S S; S< S S S@
Instruction
S S; S< S S S@
Instruction ;
S S; S< S S S@
Instruction <
S S; S< S S
Instruction
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Speedup computation
•
Speedup is a1ected b+ the number of stages.• /or a k *stage pipeline
• Assume a cloc# c+cle time of t p- i.e. it ta#es t p time per stag
• Assume n instructions 'tas$s) to process.
• Thus- it ta#es Tas# k & t p time to complete
• The remaining n – 1 tas#s emerge from the pipeline one pethus the total time for these tas#s of 'n – 1)t p.
• Thus- to complete n tas#s using a k *stage pipeline re0uires
'k & t p) 9 'n 1) t p 'k 9 n 1) t p
or
k 9 'n 1) cloc# c+cles
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Speedup computation
•
!ithout a pipeline- for n instructions re0uire nt n c+(here t n k & t p
• To compute speedup- (e di2ide the time re0uired no pipeline b+ the time re0uired if there is a pipeli
Thus as - (e see that approaches n- (hich results theoretical speedup of
(here k is the number of stages in the pipel
•
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Constraints of pipelining
•
$esource conKicts 'structural hazards)• ata dependencies
• Conditional branch statements• 4roposed solutions
• %ranch prediction
•ela+ed branch 'compiler resolution through a rearrangememachine code)
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Sample of codes (ith the preB& propert+
I4 addresses