classifying instruction set architectures stack register- register register – memory accumulator...
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Classifying Instruction Set
Architectures
Stack Register- Register Register – Memory Accumulator Memory – Memory
Load-Store/ Register-register
Code C=A+B Load R1,A Load R2,B Add R3,R1,R2 Store R3,C
Virtually every new architecture design after 1980 uses load-store register architecture!
ANOTHER EXAMPLE (Prob 2.4)
A = B + CB = A + CD = A – BAssumptions: Op Code is 8 bit represented by O,Address is 16-bit represented by A.All registers and data is 32-bit.
EXAMPLE: Accumulator
Instruc Comments Size of Operand CodeBytes
MemoryUsageBytes
Load B accumulator B O+A 3 4
Add C accumulator B + C O+A 3 4
Store A store B + C in [A] O+A 3 4
Add C accumulator A + C O+A 3 4
Store B store A + C in B O+A 3 4
Negate negate accumulator O 1
Add A accumulator B + A O+A 3 4
Store D store A – B in D O+A 3 4
Total = 22 28
Example: Mem to Mem
Instruction Comments Size of Operand CodeBytes
Memory Usage
add A, B, C ; MEM[A] = MEM[B] + MEM[C]
O+A+A+A 7 12
add B, A, C ; MEM[B] = MEM[A] + MEM[C]
O+A+A+A 7 12
sub D, A, B ; MEM[D] = MEM[A] – MEM[B]
O+A+A+A 7 12
Total = 21 36
Load-Store
Instruc Comments Size of OperandR= Reg Field (4-bit)
Code ≈ Bytes
Memory UsageBytes
LW R1, B R1 MEM[B] O+A+R = 28bits 4 4
LW R2, C R2 MEM[C] O+A+R = 28bits 4 4
ADD R3, R1, R2 R3 B + C O+R+R+R = 20bits 3
SW A, R3 MEM[A] = B + C O+A+R = 28bits 4 4
ADD R1, R3, R2 R1 A + C O+R+R+R = 20bits 3
SW B, R1 MEM[B] = A + C O+A+R = 28bits 4 4
SUB R4, R3, R1 R4 A – B O+R+R+R = 20bits 3
SW D, R4 MEM[D] = A – B O+A+R = 28bits 4 4
Total = 29 20
STACKInstruc Comments Size of Operand Code
BytesMemory UsageBytes
Push B ; push B onto stack O+A 3 4
Push C ; push C onto stack O+A 3 4
Add ; top <- B + C O 1
Pop A ; A = B + C O+A 3 4
Push A ; push A onto stack O+A 3 4
Push C ; push C onto stack O+A 3 4
Add ; top <- A + C O 1
Pop B ; B = A + C O+A 3 4
Push A ; push A onto stack O+A 3 4
Push B ; push B onto stack O+A 3 4
Sub ; top <- A – B O 1
Pop D ; D = A – B O+A 3 4
Total = 30 36
Example: Reg – Mem (Intel ISA-32)
Instruction Comments Size of OperandR = Reg Spec(1 Byte)
CodeBytes
Memory UsageBytes
Mov ECX, DWORD PTR [C] Mov C to ECX O+A+R 6 4
ADD EBX, DWORD PTR [B] B= B+C O+A+R 6 4
Mov EDX, EBX Temp Save O+R 2 0
Mov EAX,EBX A = B+C O+R 2 0
Mov DWORD PTR [A], EAX Save A O+A 6 4
ADD EAX, ECX A+C O+A 2 0
Mov EBX,EAX B = A+C O+A 2 0
Mov DWROD PTR [B], EBX Save B O+A+R 6 4
SUB EDX, EBX D = A - B O+A 2 0
Mov DWORD PTR [D], EDX Save D O+A+R 6 4
Total = 40 20
Conclusion
Architecture Instruction Memory Accesses(in bytes)
Data Memory Accesses(In bytes)
Total
Accumulator 22 28 50
Memory/Memory 21 36 57
Stack 30 36 66
Load/Store 29 20 49
Reg-Mem(Intel) 40 20 60
Pros & Cons…
Type Instruction
Encoding
Code Generatio
n
# of Clock
Cycles/Inst.
Code Size
Register-register
Fixed-length
Simple Similar Large
Register-memory
Variable Length
Moderate Different Medium
Memory-memory
Variable-length
Complex Large variation
Compact
Advantages DisadvantagesSource: Louisiana state University, ece
Common memory addressing mode in SPEC89 on VAX architecture
Displacement
10% 20% 30% 40% 50%
Frequency of the addressing mode
0%Tex
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1%
6%
1%
16%
6%
24%
3%11%
17%43%
39%
32%
55%
40%
Memory indirect
Scaled
Register Indirect
Immediate
Indirect, Immediate and Displacement Cover 75% to 99%
Size of Displacement – SPEC2000 FP
Number of Bits needed for Displacement
Perc
enta
ge o
f D
ispla
cem
ent
0%
5%
10%
15%
20%
25%
30%
35%
40%
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16-bit displacement covers 75% to 99%
Immediate Addressing Mode-Size of Immediate Operand
Number of Bits needed for Immediate Operand
Perc
enta
ge o
f Im
media
te
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16-bit Immediate covers 50% to 80% in SPEC2000
FP
Int
Popular Instructions
RANK 80x86 (SPECint92) % Total Executed
1 Load (Memory Read) 22%
2 Conditional Branch 20%
3 Compare 16%
4 Store 12%
5 Add 8%
6 And 6%
7 Sub 5%
8 Reg-Reg Move 4%
9 Call 1%
10 Return 1%
Total: 96%
Instructions for Control Flow
The Measurements of branch and jump behavior are fairly independent of other measurements and applications.
Four types of control flow change: Conditional branches Jumps Procedure calls Procedure returns
Control flow instructions –SPEC2000
Conditional Branch
100%
Call/return
Jump
25% 50%
8%
19%
10%
6%
82%
75%
Control Flow instructions into three classes
75%
Floating point average
Integer average
Flow control instructions – PC Relative also called Branches
Destination is specified by supplying a displacement that is added to the Program Counter (PC) This type of flow control instructions are called PC-relative. This way code can run independent of where it is loaded; this is called position independence
Conditional branch options
Conditional Code (CC) register E.g. 80x86,ARM etc. Tests special bit set by ALU operations Advantage
Sometimes condition is set free Disadvantage
CC is extra state. Condition codes constrain the ordering of instructions since they pass information from one instruction to a branch
Conditional branch options
Conditional Register E.g. Alpha, MIPS Tests arbitrary register with the result
of a comparison Advantage
Simple Disadvantage
Uses up register
Conditional branch options
Compare and branch E.g. PA-RISC, VAX Compare is part of the branch. Often
compare is limited to subset Advantage
One instruction rather than two for a branch
Disadvantage May be too much work per instruction for
pipelined execution
Control – Register Indirect
Implement returns and indirect jumps using a register when target address is not known at compile time.
These register indirect jumps are important for other features: Case or switch statements Virtual functions or methods High order functions Dynamically shared libraries
Types of compares in conditional branching
Less than
Greater than or equal
10% 50%
0%
0%
44%
33%
34%
35%
Frequency of comparison types in braches
Floating point average
Integer average
20% 30% 40%
Less than or equal
Equal
Not Equal 5%
2%
16%
18%
0%
11%
Greater than