3rd semester m tech cmos vlsi design (dec-2013) question papers

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USN 3'r # 8(*ut .._V*t t4r tzBC020 Max. Marks:100 (07 Marks) (08 Marks) (07 Marks) the problem of (08 Marks) (05 Marks) (06 Maiks) (10 Marks) (10 Marks) tlpes with necessary (10 Marks) (10 Marks) M.Tech. Degree Examination, Dec. 2013 I Jan 2014. GMOS RF Gircuit Design 5 ",.. 6 (.) o o () E () ! oX 69 oo ll troo .=N xao Yo otr -o -! ()= a: oO do o0c -o rc(6 .r? o OE o5- o..i o= 3o 9O JE >,h ca0 iu= =(! go tr> =o o U< -C\l o o 7 L Time: 3 hrs. Note: Answer any FIYE full questions. I\Vf!. nraJrvg, utaJr' , r7 DJ4aa l4eraavrao. I a. "'Wlren is a system considered linear? Discuss the effects of non - linearity w'ilh respect to i) :eross modulation ii) Intermodulation. (06 Marks) b. De'fiie available power gain and hence drive FRISS equation for noise frgure. (07 Marks) c. Det;it[ii"lr. the noise figure of the common source itug. shown with respect to source ., I A. t impedance"'R,. Neglect the capacitances and flicker noise of Ml',ahd assume 11 is ideal. Fig.Q1(c) ., --1 vin Voo LL 2a. b. A GSM receiver requires a minimum SNR of 12dB and has a channel bandwidth of 200KIlz. A wireless LAN receiver on the other hand, specifies a minimum SNR of 23dB and has a channel bandwidth of 20MHz. Compare the sensitivities of these two system if both have an NF of 7dB. ' ,"' " ,1,, (04 Marks) c. For the binary sequence 0111001101, obtain the differential encoding and decoding sequence.. Draw the encodei and decoder circuits. a. What is CDMA? Exphin direct sequence CDMA in detail, b. Explain Weaver fuChitecture of image reject receiver. Also explain secondary imag6ih weaver architecture. c. Explain the_,,qroblem of image in heterodyne receiver. :',, a. Explain the operation of Bipolar LNA and derive an expression for aoise figure. (08 Marks) b. Erplain the operation of passive and active CMOS mixers. (07 Marks) c. .Explain how input matching is achieved in LNA, considering any of the examples. ,"..",.., . (05 Marks) ,, fl*, Explai, i"y two basic LC oscillator topologies with necessary diagram. (08 Marks) ""''b. Explain the effect of phase noise in RF communication. (06 Marks) c. Explain injection pulling and load pulling of RF oscillators. a. b. a. 8a. b. Explain the working of charge pump PLLS. Explain the architecture of Integer - N synthesizer. Mention the classification of Power Amplifiers. Explain any two diagram. b. Explain feed back linearization technique used for power amplifiers. Explain the noise models of BJT and MOSFET. (10 Marks) What is monolithic inductor? Explain loss mechanism in monolithic inductors and give techniques to reduce the same. (10 Marks)

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3rd Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers

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Page 1: 3rd Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers

USN

3'r # 8(*ut

.._V*tt4r

tzBC020

Max. Marks:100

(07 Marks)

(08 Marks)

(07 Marks)the problem of

(08 Marks)(05 Marks)

(06 Maiks)

(10 Marks)(10 Marks)

tlpes with necessary(10 Marks)(10 Marks)

M.Tech. Degree Examination, Dec. 2013 I Jan 2014.

GMOS RF Gircuit Design

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Time: 3 hrs.

Note: Answer any FIYE full questions.I\Vf!. nraJrvg, utaJr' , r7 DJ4aa l4eraavrao.

I a. "'Wlren is a system considered linear? Discuss the effects of non - linearity w'ilh respect toi) :eross modulation ii) Intermodulation. (06 Marks)

b. De'fiie available power gain and hence drive FRISS equation for noise frgure. (07 Marks)

c. Det;it[ii"lr. the noise figure of the common source itug. shown with respect to source., I A. t

impedance"'R,. Neglect the capacitances and flicker noise of Ml',ahd assume 11 is ideal.

Fig.Q1(c)., --1vin

Voo

LL

2a.b. A GSM receiver requires a minimum SNR of 12dB and has a channel bandwidth of

200KIlz. A wireless LAN receiver on the other hand, specifies a minimum SNR of 23dBand has a channel bandwidth of 20MHz. Compare the sensitivities of these two system ifboth have an NF of 7dB. ' ,"' " ,1,, (04 Marks)

c. For the binary sequence 0111001101, obtain the differential encoding and decodingsequence.. Draw the encodei and decoder circuits.

a. What is CDMA? Exphin direct sequence CDMA in detail,b. Explain Weaver fuChitecture of image reject receiver. Also explain

secondary imag6ih weaver architecture.c. Explain the_,,qroblem of image in heterodyne receiver. :',,

a. Explain the operation of Bipolar LNA and derive an expression for aoise figure. (08 Marks)b. Erplain the operation of passive and active CMOS mixers. (07 Marks)c. .Explain how input matching is achieved in LNA, considering any of the examples.

,"..",.., . (05 Marks)

,, fl*, Explai, i"y two basic LC oscillator topologies with necessary diagram. (08 Marks)""''b. Explain the effect of phase noise in RF communication. (06 Marks)c. Explain injection pulling and load pulling of RF oscillators.

a.

b.

a.

8a.b.

Explain the working of charge pump PLLS.Explain the architecture of Integer - N synthesizer.

Mention the classification of Power Amplifiers. Explain any twodiagram.

b. Explain feed back linearization technique used for power amplifiers.

Explain the noise models of BJT and MOSFET. (10 Marks)What is monolithic inductor? Explain loss mechanism in monolithic inductors and givetechniques to reduce the same. (10 Marks)

Page 2: 3rd Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers

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(04 Marks)(08 Marks)(08 Marks)

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M.Tech. Degree Examination, Dec.2013 / Jan.2O14Automotive Electron ics

Time: 3 hrs. Max. Marks:100Note: Answer any FIVE full questions.

a. List the major components of 4-storke/cycle, gasoline fueled SI engine. ::,,, (04 Marks)b. With neat diagram, explain the four strokes of a typical modern Gasoline-Fueled SI engine.

(10 Marks)c. Explain in detail the intake manifold and fuel metering. (06 Marks)

2 a. What is spark pulse generation? Explain primary current waveform.b. What is ignition timing? With a neat sketch explain breaker point operation.c. What are drive train? With schematic explain planelary gear system.

3 a. With a block diagram, explain typical engine control system and list the

c. With a neat diagram. explain strain gauge MAP sensor. (06 Marks)

(08 Marks)(08 Marks)(04 Marks)

measured associated in an engine control configuxation. (08 Marks)b. What are mass Air flow rate (MAF) sensor? Write associated electronic signal conditioning

circuit and highlight the importanee of binary Counter. (06 Marks)

4 a. How do you measure crankshaft angular position? Explain magnetic reluctance crankshaftposition sensor.

b. What is hall effect? Explain hall effect position sensor.c. Explain throttle angel sensor.

5 a. Explain in detail ZTAzEGO sensor. Describe EGO mounling and structure and also describecharacteristics of FGO sensor. (10 Marks)

b. With a neat sehematic of a solenoid, explain fuel injector.c. Write a note ou idle speed control.

(06 Marks)(04 Marks)

6 a. Explain in brief digital engine control system and illustrate with aid of lookeep table enginecrank and engine warmup modes and write the expression for mass of fuel to.be delivered to

(12 Marks)(08 Marks)

7 ,.....,. a What is cruise control system? With aid of control block diagram explain cruise control;

cylinder.b. With aid of control flow diagram explain EGR control.

b. Explain antilock braking system.

8 Write short notes on the following:a. Sample and hold circuit.b. ON-Board and Otf-Board automotive diagnostics.c. Radio navigation.d. Electronic HUAC svstems.

(10 Marks)(10 Marks)

E****

(20 Marks)

Page 3: 3rd Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers

12EC009USN

Time: 3 hrs.

M.Tech. Degree Examination, Dec. 2013 I Jan 2014.

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a- Draw the transfer plot of CMOS invefter. Discusscurve, with suitable mathematical analysis.

assumptions made.c. Bring out the differences between BiCMOS and CMOS technology.

...::

a. Explain the basic principles of modulation doping with the help of band diagrams andexplain the operation of HEMT device structure formed using GaAs and A0GaAs.(10 Marks)

b. Derive an expression for the pinch off voltage in a MF.SFET. (04 Marks)c. Ann-channel S^i JFET hasZ:2! lr , L:4pm,d:7.2pmand, Nu:10lecm-3,

Na : 5 * 10rs cm-3 and prn = 1200cm' / 1VS.1. Assume the gate voltage is -3V. Determinei) the drain current at saturation ii) the drain voltage of saturation.

List the properties of ideal MIS system ooi., equilibrium.

\a)the elfect of aspect ratio on tlf

3a.b.

(06 Marks)

(04 Marks)Describe a typical Management Information System Structure. Also describe the energyband diagram for an ideal n * type MIS structure biases in accumulation, depletion andinversion. (10 Marks)Describe the small signal model for a MOSFET. Also calculate the trans conductance of aMOSFET. giventhat L = 5pm ,Z:5Op,m, VG:2V, V16,.rl,ora:0.98V, pr' : S0Ocm2/1VS;Ci : I 15 nF/cm:. ((16 Marks)

A p - channel standard Si MOSFET is doped with Nd : 10rs cm-3. The MOSFET has anoxide thickness of 8nm , ZIL :20, hole mobility : 450cr#l(VS) and Qr : 5 ,, 10rrq clcn].Given nr = 10l0cm-t , K, :3.9, Ksi : i1.8 and O,nr: -0.312. Determine i1 the thresholdvoltage of the device ii) the value of Vp, sat at V6 : -2Y iii.l the value of Vp, sat at V6: -7V iv) the magnitude of the saturation current for V6 : -lV. (08 Marks)

b. lxplain the sealing theory. (06 Marks)c' , E-xplain the two - dimensional potential profile for i) long channel MOSFET device and

ii) short - channel MOSFET device. (06 Marks)

a. With the help of neat sketch, explain the construction and working of Carbon Nano tubeFET. what are the advantages and disadvantages? (08 Marks)

b. Describe the defect tolerant computing. (08 Marks)c' Sketch the SOI and bulk MOSFET structures and show the differences between them.

(04 Marks)

a. What is the need for super buffers? Explain NMOS inverting and non - inverting superbuffers with the help of i) Schematic diagrams and ii) Stick diagrams for the same.

(10 Marks)b. Construct 2 input NAND and NOR gates using NMOS pass transistor logic. (04 Marks)

c.

a.

Advances in VLSI Design

Note: Answer any FIVE full questions.

b. Derive the expression for the drain to source current in MESFET below pinch off. State the(08 Marks)(0zl Marks)

(08 Marks)

Page 4: 3rd Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers

7

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c. What s a general function block? Implement 2 input EXOR gate using NMOS functionalblock. (06 Marks),

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Show the implementation of the following both in circuit diagram and in stick form : . ::"'::' '"

i) NAND - NAND implementation of Y: ab + cd (only stick form)

ii) Static CMOS AOI technology of Y : AB + CD . (04 Marks)Wtrat is tally circuit? Construct stick diagram of 3 input pass transistor tallv;,irfnitioo

rvru.L.y

Explain the implementation of 4 to 1 multiplexer using CMOS transmig$ion gates.(06 Marks)

a.

..:

b.,

c.

d.

a.

b.

Explainglobal routing and local routing.'ll"

'11'

Explain 16$l.ltrelnrs hierarchy , regularity , modularity andcircuit structuie,design.Write explanatory note on :

i) Programmable logie structure ii)" ,'

,,:":i

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logality'as applied to integrated

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(04 Marks)

(10 Marks)Gate anay stahdard cell design.

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2 of2