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TIBPAL22V10-10CHIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 D3972, FEBRUARY 1992

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Copyright 1992, Texas Instruments Incorporated

1

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Second-Generation PLD Architecture

High-Performance Operation:fmax (External Feedback) . . . 71 MHzPropagation Delay . . . 10 ns Max

Increased Logic Power Up to 22 Inputsand 10 Outputs

Increased Product Terms Average of 12Per Output

Variable Product Term DistributionAllows More Complex Functions to BeImplemented

Each Output Is User Programmable forRegistered or Combinational Operation,Polarity, and Output Enable Control

Power-Up Clear on Registered Outputs

TTL-Level Preload for Improved Testability

Extra Terms Provide Logical SynchronousSet and Asynchronous Reset Capability

Fast Programming, High ProgrammingYield, and Unsurpassed Reliability EnsuredUsing Ti-W Fuses

AC and DC Testing Done at the FactoryUtilizing Special Designed-In Test Features

Dependable Texas Instruments Quality andReliability

Package Options Include PlasticDual-In-Line and Chip Carrier Packages

description

The TIBPAL22V10-10C is a programmable array logic device featuring high speed and functional equivalencywhen compared to presently available devices. They are implemented with the familiar sum-of-products(AND-OR) logic structure featuring the new concept Programmable Output Logic Macrocell. TheseIMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.

These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining andprogramming the architecture of each output on an individual basis. Outputs may be registered or nonregisteredand inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs areenabled through the use of individual product terms.

Further advantages can be seen in the introduction of variable product term distribution. This techniqueallocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. Thisvariable allocation of terms allows far more complex functions to be implemented than in previously availabledevices.

This device is covered by U.S. Patent 4,410,987.IMPACT-X is a trademark of Texas Instruments Incorporated.

1

2

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45

6

7

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9

10

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12

24

23

22

2120

19

18

17

16

15

14

13

CLK/I

I

I

II

I

I

I

I

I

I

GND

VCCI/O/Q

I/O/Q

I/O/QI/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I

NT PACKAGE

(TOP VIEW)

3 2 1 28 27

12 13

5

6

7

8

9

10

11

25

24

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22

21

20

19

I/O/Q

I/O/Q

I/O/Q

NC

I/O/Q

I/O/Q

I/O/Q

I

I

I

NC

I

I

I

4 26

14 15 16 17 18

I I

GND

NC

I

I/O

/Q

I/O

/Q

I I CLK/

I

NC

I/O/Q

I/O/Q

FN PACKAGE

(TOP VIEW)

NCNo internal connectionPin assignments in operating mode

VCC

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TIBPAL22V10-10CHIGH-PERFORMANCE IMPACT-XPROGRAMMABLE ARRAY LOGIC CIRCUITSSRPS015 D3972, FEBRUARY 1992


DALLAS, TEXAS 752652

description (continued)

Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. Thesefunctions are common to all registers. When the synchronous set product term is a logic 1, the output registersare loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product termis a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on

the polarity selected during programming. Output registers can be preloaded to any desired state during testing.Preloading permits full logical verification during product testing.

With features such as programmable output logic macrocells and variable product term distribution, theTIBPAL22V10-10C offers quick design and development of custom LSI functions with complexities of 500 to800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either atemporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and10 outputs are possible.

A power-up clear function is supplied that forces all registered outputs to a predetermined state after power isapplied to the device. Registered outputs selected as active-low power up with their outputs high. Registeredoutputs selected as active-high power up with their outputs low.

A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Onceblown, the verification circuitry is disabled and all other fuses will appear to be open.

The TIBPAL22V10-10C is characterized for operation from 0C to 75C.

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TIBPAL22V10-10CHIGH-PERFORMANCE IMPACT-XPROGRAMMABLE ARRAY LOGIC CIRCUITS



DALLAS, TEXAS 75265 3

functional block diagram (positive logic)

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

10

12

14

EN

16

16

14

12

10

22

22

1

10

&

44 x 132

I/O/Q

I/O/Q

I/O/Q

I/O/Q

EN

EN

EN

EN

EN

EN

EN

EN

EN

10

10

8

8

10

11

CLK/I

I

Set

Reset1S

R

C1

denotes fused inputs

OutputLogic

Macrocell

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POSTOFFICEBOX655

303DALLAS,TEXAS75265

4

0 4 8 12 16 20 24 28

Increment

FirstFuseNumbers

32 36 40

Macro-cell

R = 5809P = 5808

R = 5811P = 5810

R = 5813P = 5812

R = 5815P = 5814

R = 5817P = 5816

logic diagram (positive logic)1

2

3

4

5

396

0

440

880

924

1452

1496

2112

2156

2860

I

I

I

I

CLK/I

Macro-cell

Macro-cell

Macro-cell

Macro-cell

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POSTOFFICEBOX655303DALLAS,TEXAS75265

5

Fuse number = First Fuse number + Increment

R = 5819P = 5818

R = 5821P = 5820

R = 5823P = 5822

R = 5825P = 5824

R = 5827P = 5826

6

7

8

9

10

11

Inside each MACROCELL the P fuse is the polarity fuse and the R fuse is the register fuse.

2904

3608

3652

4268

4312

4840

4884

5324

5368

5720

5764

I

I

I

I

I

I

Macro-cell

Macro-cell

Macro-

cell

Macro-cell

Macro-cell

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output logic macrocell diagram

C1

G0

30

1

1

0

3

2

MUX

I = 0

1S

1D

R

MUX

G1

1

1

SS

AR

From Clock Buffer

S1

S0

AR = asynchronous reset

SS = synchronous set

Output Logic Macrocell

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FEEDBACK AND OUTPUT CONFIGURATION





C1

1S

1D

R

S1 = 0

S0 = 0

C1

1S

1D

R

S1 = 0

S0 = 1

REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

S1 = 1

S0 = 0

S1 = 1

S0 = 1

I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT

MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE

FUSE SELECT

S1 S0

0 0 Register feedback Registered Active low

0 1 Register feedback Registered Active high

1 0 I/O feedback Combinational Active low

1 1 I/O feedback Combinational Active high

0 = unblown fuse, 1 = blown fuse

S1 and S0 are select-function fuses as shown in the output logic macrocell

diagram.

Figure 1. Resultant Macrocell Feedback and Output Logic After Programming

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nsPulse durationtw




absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input voltage (see Note 1) 1.2 V to VCC +0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Voltage range applied to disabled output (see Note 1) 0.5 V to VCC +0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .Operating free-air temperature range 0C to 75C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range 65C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

MIN NOM MAX UNIT

VCC Supply voltage 4.75 5 5.25 V

VIH High-level input voltage (see Note 2) 2 5.5 V

VIL Low-level input voltage (see Note 2) 0.8 V

IOH High-level output current 3.2 mA

IOL Low-level output current 16 mA

Clock high or low 5

Asynchronous reset high or low 10

Input 7Feedback 7

tsu Setup time before clock Synchronous preset (active) 9 ns

Synchronous preset (inactive) 8

Asynchronous reset (inactive) 8

th Hold time, input, set, or feedback after clock 0 ns

TA Operating free-air temperature 0 75 C

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and includes all overshoots due to system and/or tester

noise. Testing these parameters should not be attempted without suitable equipment.

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IIL VCC = 5.25 V, VI = 0.4 V mA

Ci f = 1 MHz, VI = 2 V pF





electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIK VCC = 4.75 V, II = 18 mA 1.2 V

VOH VCC = 4.75 V, IOH = 3.2 mA 2.4 V

VOL VCC = 4.75 V, IOL = 16 mA 0.35 0.5 V

IOZH

VCC = 5.25 V, VO = 2.7 V 0.1 mAIOZL

VCC = 5.25 V, VO = 0.4 V 0.1 mA

II VCC = 5.25 V, VI = 5.5 V 1 mA

IIH VCC = 5.25 V, VI = 2.7 V 25 A

CLK 0.25

All others 0.1

IOS VCC = 5.25 V, VO = 0.5 V 30 130 mA

ICC VCC = 5.25 V, VI = GND, Outputs open 210 mA

I 6

CLK 6

Co f = 1 MHz, VO = 2 V 8 pF

All typical values are at VCC = 5 V, TA = 25C.

I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to

avoid test problems caused by test equipment ground degradation.

switching characteristics over recommended ranges of supply voltage and operating free-airtemperature (unless otherwise noted)

PARAMETERFROM

(INPUT)TO

(OUTPUT)TEST CONDITION MIN MAX UNIT

Without feedback 100

fmax With internal feedback (counter configuration) 80 MHz

With external feedback 71

tpd I, I/O I/O R1 = 300 , 1 10 ns

tpd I, I/O (reset) Q R2 = 300 , 15 ns

tpd CLK Q See Figure 6 1 7 nstpd

# CLK Feedback 5.5 ns

ten I, I/O I/O, Q 11 ns

tdis I, I/O I/O, Q 9 ns

fmax (without feedback) =1

tw(low) ) tw(high)

fmax (with internal feedback) =1

tsu ) tpd(CLK to feedback)

fmax (with external feedback) =1

tsu ) tpd(CLK to Q)

# This parameter is calculated from the measured fmax with internal feedback in the counter configuration.

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preload procedure for registered outputs (see Notes 3 and 4)

The output registers can be preloaded to any desired state during device testing. This permits any state to betested without having to step through the entire state-machine sequence. Each register is preloaded individuallyby following the steps given below:

Step 1. With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH.

Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.Step 3. Pulse pin 1, clocking in preload data.Step 4. Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level

at the output pin.

td

tsutw

td

VIHH

VIL

VIL

VOL

VOH

VIH

Pin 13

Pin 1

Registered I/O Input OutputVIH

VIL

Figure 2. Preload Waveforms

NOTES: 3. Pin numbers shown are for the NT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly.

4. td = tsu = tw= 100 ns to 1000 ns. VIHH= 10.25 V to 10.75 V.

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power-up reset

Following power up, all registers are reset to zero. The output level depends on the polarity selected duringprogramming. This feature provides extra flexibility to the system designer and is especially valuable insimplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC bemonotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and

feedback setup times are met.

1.5 V

tsu

tpd

tw

VOL

VOH

VIL

VIH

5 VVCC

Active HighRegistered Output

Active LowRegistered Output

CLK

4 V

VOH

VOL

1.5 V

1.5 V

(600 ns typ, 1000 ns MAX)

State Unknown

1.5 V

State Unknown

This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback.

Figure 3. Power-Up Reset Waveforms

programming information

Texas Instruments programmable logic devices can be programmed using widely available software andinexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, andfirmware are available upon request. Information on programmers capable of programming Texas Instrumentsprogrammable logic is also available, upon request, from the nearest TI field sales office, local authorized TIdistributor, or by calling Texas Instruments at (214) 997-5666.

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THERMAL INFORMATION

thermal management of the TIBPAL22V10-10C

Thermal management of the TIBPAL22V10-10CNT and TIBPAL22V10-10CFN is necessary when operating atcertain conditions of frequency, output loading, and outputs switching simultaneously. The device and system

application will determine the appropriate level of management.

Determining the level of thermal management is based on factors such as power dissipation (PD), ambienttemperature (TA), and transverse airflow (FPM). Figures 4 (a) and 4 (b) show the relationship between ambienttemperature and transverse airflow at given power dissipation levels. The required transverse airflow can bedetermined at a particular ambient temperature and device power dissipation level in order to ensure the devicespecifications.

Figure 5 illustrates how power dissipation varies as a function of frequency and the number of outputs switchingsimultaneously. It should be noted that all outputs are fully loaded (CL = 50 pF). Since the condition of eight fullyloaded outputs represents the worst-case condition, each application must be evaluated accordingly.

(a) TIBPAL22V10-10CNT

40201000

200

400

600

60 70

Minimum

Transverse

AirFlow

ft/min

805030

MINIMUM TRANSVERSE AIR FLOW

vs

AMBIENT TEMPERATURE

TA Ambient Temperature C

PD = 1.6 WPD = 1.4 WPD = 1.2 W

PD

= 1 W

100

300

500

40201000

200

400

600

60 70

Minimum

Transverse

AirFlow

ft/min

MINIMUM TRANSVERSE AIR FLOW

vs

AMBIENT TEMPERATURE

805030

TA Ambient Temperature C

(b) TIBPAL22V10-10CFN

100

300

500

PD = 1.6 WPD = 1.4 WPD = 1.2 W

PD = 1 W

Figure 4

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THERMAL INFORMATION

1200

1000

800

1400

f Frequency MHz

1600

PD

Power

Diss

ipa

tionm

W

POWER DISSIPATION

vs

FREQUENCY

1800

2000

1 4 10 40 1002 20 200

VCC = 5 VTA = 25 CCL = 50 pF

10 Outputs Switching

1 Output Switching

Figure 5

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PARAMETER MEASUREMENT INFORMATION

tsu

S1

From OutputUnder Test

TestPoint

R2CL(see Note A)

LOAD CIRCUIT FOR3-STATE OUTPUTS

3 V

0

1.5 V

1.5 V

th

1.5 V

TimingInput

DataInput

Input

In-PhaseOutput

Out-of-PhaseOutput

(see Note D)

tpd

tpd

tpd

tpd

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

VOH

VOH

VOL

VOL

3 V

0

3 V

0(see Note B)

1.5 V 1.5 V

1.5 V 1.5 V

tw

High-LevelPulse

Low-LevelPulse

OutputControl

(low-levelenabling)

Waveform 1S1 Closed

(see Note C)

Waveform 2S1 Open

(see Note C)

1.5 V 1.5 V

3 V

0(see Note B)

2.7 V

VOL

VOH

VOH 0.5 V

0 V

ten

ten

tdis

tdis

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATIONS

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

1.5 V

R1

3 V

3 V

0(see Note B)

0

VOL+ 0.5 V

5 V

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.

B. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control.

D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.

E. Equivalent loads may be used for testing.

Figure 6. Load Circuit and Voltage Waveforms

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TYPICAL CHARACTERISTICS

210

200

190

1800 25 50

Figure 7

220

SUPPLY CURRENT

vs

FREE- AIR TEMPERATURE

75

TA Free-Air Temperature C

ICC

Supp

lyCurren

tm

A

VCC = 4.75 V

VCC = 5.25 V

VCC = 5 V

1

0

7

2

3

4

5

6

0 25 50

Figure 9

Propaga

tion

De

lay

Timens

75

PROPAGATION DELAY TIME

vs

FREE- AIR TEMPERATURE

VCC = 5 V

CL = 50 pFR1 = 300 R2 = 300

10 Output Switching

TA Free- Air Temperature C

1

04.75 5

Figure 8

Propaga

tion

De

lay

Timens

7


vs

SUPPLY VOLTAGE

5.25

VCC Supply Voltage V

TA = 25 CCL = 50 pF

R1 = 300 R2 = 300

10 Outputs Switching

CL Load Capacitance pF

8

4

2

0100 200 300 400

Figure 10

12

14

16

500

10

6


vs

LOAD CAPACITANCE

VCC = 5 VTA = 25 CR1 = 300 R2 = 300

1 Output Switching

0 600

2

3

4

5

6 tPLH (I, I/O to O, I/O)

tPHL (I, I/O to O, I/O)

tPLH (CLK to Q)

tPHL (CLK to Q)

tPHL (I, I/O to O, I/O)

tPLH (I, I/O to O, I/O)

tPLH (CLK to Q)

tPHL (CLK to Q)

tp

d

Propaga

tion

De

lay

Timens

tpd (CLK to Q)

tpd (I, I/O to O, I/O)

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TIBPAL22V10-10CHIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS



DALLAS, TEXAS 7526516 SRPS015

TYPICAL CHARACTERISTICS

1100

1050

10001 4 10 40 100

Figure 12

1150

f Frequency MHz

1200

2 20

PD

Power

Diss

ipa

tionm

W

POWER DISSIPATION

vs

FREQUENCY

10- BIT COUNTER MODE

VCC = 5 V

TA = 80C

TA = 0 C

TA = 25 C2

5

3

11 2 3 4 5

Figure 11

Propaga

tion

De

lay

Timens

7

6 7

6

4


vs

NUMBER OF OUTPUTS SWITCHING

VCC = 5 V

TA = 25 CCL = 50 pFR1 = 300 R2 = 300

Number of Outputs Switching

6 7 10

= tPLH (I, I/O to O, I/O)

= tPHL (I, I/O to O, I/O)

= tPLH (CLK to Q)

= tPHL (CLK to Q)

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL

APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMERS RISK.

In order to minimize risks associated with the customers applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TIs publication of information regarding any third

partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 1998, Texas Instruments Incorporated

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