3/15/2002cse 141 - final remarks concluding remarks soap

3/15/2002 CSE 141 - Final Remarks

Concluding Remarks

SOAP

CSE 141 - Final Remarks2

Computer Technologies• First Generation: Mid 40’s to late 50’s

– Vacuum Tube “switches”

– Acoustic or CRT memory (volatile)

• Second Generation: Late 50’s to mid 60’s– Individual transistors

– Core memory, magnetic disks (non-volatile)

• Third Generation: Mid 60’s to mid 70’s– Integrated circuits (up to 1000 transistors/chip)

– Complex instructions via microcode

• Fourth Generation: Mid 70’s and beyond– single-chip processors; semiconductor memory


Computer Taxonomy• Supercomputer

• Parallel or vector machine, fast memory, cost > $1 M

• Mainframe, Server• Typically serve 100’s of users; lots of I/O power

• Workstation• High performance; less I/O than mainframe

• 1-10 users, often UNIX operating system

• Personal Computer• Single user, < $3000, often Microsoft or MAC OS.

• Embedded computer or controller• Special-purpose interface: gameboys, microwaves, ...

The differencebetween these two

is disappearing


The computer pyramid

Servers

Super –computers

Workstations

Personal Computers

There are far more lower-layer computers than higher, more powerful ones.

Innovations move from topto bottom (usually).

But supercomputersare being replaced byinterconnected workstations & PC’s(and Playstations??). Embedded Controllers


What is all about?

1. Layers of Abstraction– ISA’s, bus standards (e.g. PCI, Ethernet, ...),

Virtual Memory

– Good (or popular) standards evolve and outlive individual machines• E.g. IBM 360, Intel x86

2. InterfacingWe’ve had to consider programming

languages, compilers, operating systems, networks, ...

3. Performance ...

this coursearchitecture


Memory Evolution

• Transistors get smaller, resulting in ...

• DRAM chip capacity doubles every 1.5 years

• Transistor count doubles every 2 years

• Clock speed doubles every 3 years

• Memory speeds increase a tiny bit

And then a miracle occurs ...

• Performance doubles every 1.5 years

Processor Evolution

A slide frombeginning of

course


Processor Architecture

Program CounterProgram CounterLoadLoad

StoreStore

Instruction Instruction RegisterRegister

ContrControlol

RegistersRegisters

ALU ALU


pipeline the ALU


StoreStore


ContrControlol

RegistersRegisters

Pipe-Pipe-

linedlined

ALU ALU

Pipe-Pipe-

linedlined

ALU ALU


separate fixed & float


StoreStore


ContrControlol

IntegerInteger

RegistersRegisters

IntegIntegerer

pipepipe

FloatFloat

RegistersRegisters

FloatFloat

RegistersRegisters

FloatinFloatingg

PointPoint

pipe pipe

FloatinFloatingg

PointPoint

pipe pipe


add branch prediction

LoadLoad

StoreStore


Control +Control +

Branch Branch PredictionPrediction

Control +Control +

Branch Branch PredictionPrediction

IntegerInteger

RegistersRegisters

IntegIntegerer

pipepipe

FloatFloat

RegistersRegisters

FloatinFloatingg

PointPoint

pipe pipe

Program CounterProgram Counter


out-of-order execution


StoreStore

InstructionInstruction

RegisterRegister

FileFile

Control,Control,

Branch Branch Prediction,Prediction,

OutOfOrderOutOfOrder

Control,Control,



IntegerInteger

RegistersRegisters

+ shadow + shadow

registersregisters

IntegIntegerer

pipepipe

FloatFloat

RegistersRegisters

+ shadow + shadow

registersregisters

FloatinFloatingg

PointPoint

pipe pipe


more functional units

LoadLoad

StoreStore


RegisterRegister

FileFile

Control,Control,



IntegerInteger

RegistersRegisters

+ shadow + shadow

registersregisters

IntegIntegerer

pipepipe

FloatFloat

RegistersRegisters

+ shadow + shadow

registersregisters

FloatinFloatingg

PointPoint

pipe pipe

LoadLoad

StoreStore

LoadLoad

StoreStoreLoadLoad

StoreStore

LoadLoad

StoreStore

IntegIntegerer

pipepipe

IntegIntegerer

pipepipe

FloatinFloatingg

PointPoint

pipe pipe

FloatinFloatingg

PointPoint

pipe pipe

Program Program CounterCounter


on-chip memory caches

ProgramProgram CounterCounterLoadLoad

StoreStore


RegisterRegister

FileFile

Control,Control,



IntegerInteger

RegistersRegisters

+ shadow + shadow

registersregisters

IntegIntegerer

pipepipe

FloatFloat

RegistersRegisters

+ shadow + shadow

registersregisters

FloatinFloatingg

PointPoint

pipe pipe

LoadLoad

StoreStoreLoadLoad

StoreStore

IntegIntegerer

pipepipe

FloatinFloatingg

PointPoint

pipe pipe

InstructioInstructionn

CacheCache

InstructioInstructionn

CacheCache

DataData

CacheCache

DataData

CacheCacheLevelLevel 22

CacheCache

TLBTLB


Speculation

What has changed?

Amount of on-chip concurrency

What hasn’t changed (yet)? The program counterComing to your computer soon ... Multithreaded Architectures Small changes to microprocessor:

- add 3 - 7 program counters and register sets


The Final

• Tuesday, March 19, 11:30 – 2:29– Last names A – M : Center 113 (classroom)

– Last names N – Z : CSB 001 (section room)

• You may bring:– 3 pages of handwritten notes

– Calculators (though I still don’t understand how they help!)

– A little odorless food


What’s on the Final ??

• Entire course– Including things that weren’t on quizzes:

• E.g. branch hazards, superscalar scheduling

• Similar to quizzes:– Some easier questions, some harder

– Vocabulary, details (control lines, cache operation, ...), reasons for various choices, calculations.

– Including a BotEE (Back of the Envelope Estimate)

Note: For other problems, don’t round off answers


Quiz 3, last question• Data moves from Ethernet Controller to Memory on System

Bus.– Only one pair of devices can use a bus at a time.– So, processor-memory communication is disrupted.

• Total amount of data moved on System Bus per image1 MByte: Ethernet Controller to Memory1 MByte: Memory into Cache first time (compulsory misses)2 MByte: Extra trips of data into cache (it keeps getting kicked out) 4 MByte total

Total system speed is limited by:With Fast Ethernet, getting data from cameras to Ethernet

ControllerWith Gigabit Ethernet, the System Bus limits performance

Processor

and Caches

Ethernet

Controller

Memory

remote sensors

Ethernet #2

System bus

remote sensors

Ethernet #1


Grading

Quiz 1 Hi 27.5 (out of 30)Top quartile: 21.5Median: 18Third Quartile: 15

Quiz 2 High 38 (out of 40)Top quartile: 34Median: 31.5Third quartile: 27.5

Quiz 3 Hi 28 (out of 29)Top quartile: 20Median: 17.5Third quartile: 15

Add 10 to Quiz 1 score

Add 11 to Quiz 1 score

30 is “B” (and closer to B+ than B-)

3/15/2002cse 141 - final remarks concluding remarks soap

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