3-vrms cap-less line driver with adjustable gain · the ad22650b is a 3-vrms cap-less stereo line...

ESMT Preliminary AD22650B

Elite Semiconductor Memory Technology Inc. Publication Date: Feb. 2016 Revision: 0.2 1/23

3-Vrms Cap-Less Line Driver with Adjustable Gain Features

Operation Voltage: 3V to 5.5V Cap-less Output

- Eliminates Output Capacitors - Improves Low Frequency Response - Reduces POP/Clicks Low Noise and THD at 2.5k Load

- SNR > 102dB - Typical Vn < 12uVrms - THD+N < 0.02%

Maximum Output Voltage Swing into 2.5k Load - 2Vrms at 3.3V Supply Voltage

- 3Vrms at 5V Supply Voltage Differential Input External Gain Setting from 1V/V to 10V/V Fast Start-up Time : 2ms Integrated De-Pop Control External Under Voltage Protection Thermal Protection Less External Components Required +/-8kV IEC ESD Protection at line outputs

Ordering Information

Applications LCD / PDP TVs CD / DVD players Set-Top Boxes Home Theater in Box

Description

The AD22650B is a 3-Vrms cap-less stereo line driver. The device is ideal for single supply electronics. Cap-less design can eliminate output dc-blocking capacitors for better low frequency response and save cost.

The AD22650B is capable of delivering 3-Vrms output into a 2.5kΩ　load with 5V supply. The gain settings can be set by users from 1V/V to 10V/V externally. The AD22650B has internal and external under voltage protection to prevent POP noise. Build-in shutdown control and de-pop control sequence also help AD22650B to be a pop-less device.

The AD22650B is available in a 14-pin TSSOP package.

Product ID Package Packing Comments

AD22650B-QH14NAT TSSOP-14L

96 Units / Tube 100 Tubes / Small Box Green(HF)

AD22650B-QH14NAR 2.5k Units Tape & Reel

Simplified Application Circuit



Pin Assignments

Pin Description No. Name Type (1) Pin Description

1 LINP I Left channel OP positive input

2 LINN I Left channel OP negative input

3 OUTL O Left channel OP output

4 SGND P Signal ground

5 EN I Enable input, active high

6 PVSS P Supply voltage

7 CN I/O Charge-pump flying capacitor negative terminal

8 CP I/O Charge-pump flying capacitor positive terminal

9 PVDD P Positive supply

10 PGND P Power ground

11 UVP I Under-voltage protection input, internally pulled high

12 OUTR O Right channel OP output

13 RINN I Right channel OP negative input

14 RINP I Right channel OP positive input (1) I=input, O=output, P=power



Functional Block Diagram

Available Package Package Type Device No. Θja (/W)(1) Θjt (/W)(2)

TSSOP-14L AD22650B 100 32 (1) Θja is measured at room temperature (TA=25), natural convection environment test board, which is constructed with a thermal efficient,

2-layers PCB. The measurement is tested using the JEDEC51-3 thermal measurement standard.

(2) Θjt represents the heat resistance for the heat flow between the chip and package’s top surface.

Marking Information AD22650B Line 1 : LOGO Line 2 : Product No. Line 3 : Tracking Code



Absolute Maximum Ratings(1)

SYMBOL PARAMETER VALUE UNIT Supply Voltage, VDD to GND -0.3 to 6.5 V

VI Input Voltage VSS -0.3 to VDD+0.3 V

RL Minimum load impedance 16 Ω

EN to GND -0.3 to VDD+0.3 V

Tstg Storage temperature range -65 to 150

TJ Maximum operating junction temperature range -40 to 150

(1) The absolute maximum ratings are limiting values of operation, safety of the device cannot be guaranteed if beyond those values.

Recommended Operating Conditions

SYMBOL PARAMETER Min NOM Max UNIT

VDD Supply Voltage 3.0 5.5 V

VIH High Level Input Voltage EN 60 % of VDD

VIL Low Level Input Voltage EN 40 % of VDD

TA Operating Ambient Temperature Range -40 85

RL Load Resistance 16 Ω

Electrical Characteristics PVDD=3.3V, TA=25, RL=2.5kΩ, CFLY=CPVSS=1μF, CIN=1μF, RI=10kΩ, RF=20kΩ (unless otherwise noted)

SYMBOL PARAMETER TEST CONDITIONS Min NOM Max UNIT

IDD VDD Supply Current EN=VDD 6 15 mA

ISD VDD Shutdown Current EN=0V, VDD =5.5V <1 5 μA

II Input Current EN pin 1 μA

VO Output Voltage (Outputs In Phase)

THD+N=1%, VDD=3.3V, fIN=1kHz

2.2

Vrms THD+N=1%, VDD=5V, fIN=1kHz 3.4

THD+N=1%, VDD=5V, fIN=1kHz, RL=100k

3.5

Po Output Power (Outputs In Phase)

THD+N=1%, VDD=3.3V, fIN=1kHz, RL=32Ω

23

mW

THD+N=1%, VDD=5V, fIN=1kHz, RL=32Ω

63

THD+N=1%, VDD=3.3V, fIN=1kHz, RL=16Ω

15

THD+N=1%, VDD=5V, fIN=1kHz, RL=16Ω

45

THD+N Total Harmonic Distortion Plus Noise

VO=2Vrms, fIN=1kHz 0.001 %

Po=10mW, fIN=1kHz, RL=32Ω 0.02



Electrical Characteristics (Con’t) PVDD=3.3V, TA=25, RL=2.5kΩ, CFLY=CPVSS=1μF, CIN=1μF, RI=10kΩ, RF=20kΩ (unless otherwise noted)

SYMBOL PARAMETER TEST CONDITIONS Min NOM Max UNIT

THD+N Total Harmonic Distortion Plus Noise

Po=10mW, fIN=1kHz, RL=16Ω 0.04 %

Crosstalk Channel Separation VO=2Vrms, fIN=1kHz -120

dB Po=20mW, fIN=1kHz, RL=32Ω -97

VN Output Noise RI=10k, RF=10k 4 15 μVrms

VOS Output Offset Voltage VDD=3V to 5.5V, Input Grounded -1 1 mV

PSRR Power Supply Rejection Ratio

VDD=3V to 5.5V, Vrr=200mVrms, fIN=1kHz

-80 -60 dB

RI Input Resistor Range 1 10 47 kΩ

RF Feedback Resistor Range

4.7 20 100 kΩ

fCP Charge-Pump Frequency

400 500 600 kHz

Maximum capacitive Load

220 pF

VUVP External Under Voltage Detection

1.25 V

IHYS External Under Voltage Detection Hysteresis Current

5 μA

TSD Over Temperature Protection Level

150

Tstart-up Start-up Time 2 ms



Typical Characteristics PVDD=3.3V, TA=25, RL=2.5kΩ, CFLY=CPVSS=1μF, CIN=1μF, RI=10kΩ, RF=20kΩ,(unless otherwise noted)

Total Harmonic Distortion + Noise (THD+N) vs. Output Power (2.5Kohm)

PVDD=3.3V,RL=2.5Kohm,Fin=1KHz

0.0006

20

0.002

0.005 0.01 0.02

0.05 0.1 0.2

0.5 1 2

5 10

THD

+N(%

)

100m 5 200m 300m 400m 500m 600m 700m 900m 1 2 3 4 Vo - Output Voltage per channel(V)

20

0.002

0.005 0.01 0.02

0.05 0.1 0.2

0.5 1 2

5 10

THD

+N(%

)

PVDD=5.0V,RL=2.5Kohm,Fin=1KHz

0.0006 100m 5 200m 300m 400m 500m 600m 700m 900m 1 2 3 4

Vo - Output Voltage per channel(V)



Total Harmonic Distortion + Noise (THD+N) vs. Output Power (32ohm)

0.0006

20

0.002

0.005 0.01 0.02

0.05 0.1 0.2

0.5 1 2

5 10

100u 200m 200u 500u 1m 2m 5m 10m 20m 50m 100m

THD

+N(%

)

PVDD=3.3V,RL=32ohm,Fin=1KHz

Po - Output Voltage per channel(W)

100u 200m 200u 500u 1m 2m 5m 10m 20m 50m 100m


0.0006

20

0.002

0.005 0.01 0.02

0.05 0.1 0.2

0.5 1 2

5 10

THD

+N(%

)




Total Harmonic Distortion + Noise (THD+N) vs. Output Power (16ohm)

200m

20

0.002

0.005 0.01 0.02

0.05 0.1 0.2

0.5 1 2

5 10

THD

+N(%

)

0.0006 100u 200m 200u 500u 1m 2m 5m 10m 20m 50m 100m



100u 200m 200u 500u 1m 2m 5m 10m 20m 50m 100m


20

0.002

0.005 0.01 0.02

0.05 0.1 0.2

0.5 1 2

5 10

THD

+N(%

)

0.0006




Total Harmonic Distortion + Noise (THD+N) vs. Signal Frequency

30

0.001

0.01

0.1

1

10

THD

+N(%

)

20 20k 50 100 200 500 1k 2k 5k 10k

Fin - Input frequency(Hz)

0.0001

PVDD=3.3V,Cin=1uF,RL=2.5Kohm,Fin=1KHz,Vo=2Vrms

30

0.001

0.01

0.1

1

10

THD

+N(%

)

20 20k 50 100 200 500 1k 2k 5k 10k


0.0001




Phase vs. Signal Frequency

+30

+330

+80

+130

+180

+230

+280

20 20k 50 100 200 500 1k 2k 5k 10k

Phas

e (d

eg)



+330

+80

+130

+180

+230

+280

Pha

se (d

eg)

+30 20 20k 50 100 200 500 1k 2k 5k 10k





Gain vs. Signal Frequency PVDD=3.3V,Cin=1uF,RL=2.5Kohm,Fin=1KHz,Vo=2Vrms

-4

-3

-2

-1

+1

+2

+3

+4

+5

-5 20 20k 50 100 200 500 1k 2k 5k 10k


+0

Gai

n (d

BV)

-5

-4

-3

-2

-1

+0

+1

+2

+3

+4

20 20k 50 100 200 500 1k 2k 5k 10k

+5


Gai

n (d

BV)




Application Information

Line Driver Amplifiers Operation A conventional inverting line-driver amplifier always requires an output dc-blocking capacitor and a bypass capacitor, see Figure 1. DC blocking capacitors are large in size and cost a lot. It also restricts the output low frequency response. POP will occur if the charge and discharge processes on output capacitors are not carefully take cared. Besides, it needs to wait for a long time to charge VOUT from 0V to PVDD/2. For a cap-less line driver, see figure 2, a negative supply voltage (PVSS) is produced by the integrated charge-pump, and feeds to line driver’s negative supply instead of ground. The positive input can directly connect to ground without a CBYPASS, and VOUT is biased at ground which can eliminate the output dc-blocking capacitors. The output voltage swing is doubled compared to conventional amplifiers.

Figure 1. Conventional Line Driver Amplifier

Figure 2. Cap-less Line Driver Amplifier



External Under-Voltage Protection The external under-voltage protection is used to mute the line-driver before any input voltage change to generate a POP. The threshold of UVP pin is designed to 1.25V. By using a resistor divider, users can decide the UVP level and hysteresis level. The levels can be obtained by following equations:

( ) ( )( ) 12/1211135

12/121113625.1RRRRAHysteresis

RRRRAVVUVP

+××=+××−=

μμ

With the condition R13 >> (R11 // R12). For example, to obtain VUVP=2.67V, Hysteresis=0.37V, R11=1.5kΩ, R12=1kΩ, R13=30kΩ.

Figure 3. Application Circuit of UVP Pin

The UVP pin voltage ripple needs to take care during power up state within 2mS. The UVP pin ripple lower 1.25V by 2~4 times will trigger test mode in Line Driver. To put a capacitor parallel with UVP pin can improve test mode mis-operating triggered while VSTSTEM is not stable during power up initially. That’s recommended 2mS timing delay to enable the Line Driver after PVDD power up ready.

UVP pin is pulled high internally, and therefore it can be floated to disable the external under-voltage protection feature.



Charge-Pump Operation The charge-pump is used to generate a negative supply voltage to supply to line-driver. It needs two external capacitors, CFLY and CPVSS, for normal operation, see figure 4 (a). The operation can be analyzed with two phase. In phase I, see figure 4 (b), CFLY is charged to PVDD, and in phase II, see figure 4 (c), the charges on CFLY are shared with CPVSS, that makes PVSS a negative voltage. After an adequate clock cycles, PVSS will be equaled to –PVDD. Low ESR capacitors are recommended, and the typical value of CFLY and CPVSS is 1μF. A smaller capacitance can be used, but the maximum output voltage may be reduced.

+-

PV

DD

Figure 4. Charge-Pump Operation Enable Function

The enable function is used to reduce power consumption while the device is not in use. When a logic low is applied to this pin, the overall circuits are turned off. Line driver output and PVSS are pulled to ground. When a logic high is applied to enable pin, the PVSS is started to build-up and line driver output signal is released after about 0.5ms typically.

Decoupling Capacitors A low ESR power supply decoupling capacitor is required for better performance. The capacitor should place as close to chip as possible, the value is typically 1μF. For filtering low frequency noise signals, a 10μF or greater capacitor placed near the chip is recommended.

Input Blocking Capacitors (CIN) An input blocking capacitor is required to block the dc voltage of the audio source and allows the input to bias at a proper dc level for optimum operation. The input capacitor and input resistor (RI) form a high-pass filter with the corner frequency determined as following equation:

INIC CR

fπ2

1=

Gain Setting Resistors (RI and RF)



The line driver’s gain is determined by RI and RF. The typical configurations of the amplifier are inverting, non-inverting, and differential input, see figure 5. The gain equations are listed as follows:

(a) Inverting configuration : I

FV R

RA −=

(b) Non-inverting configuration : I

FV R

RA +=1

© Differential-input configuration : I

FV R

RA =

Figure 5. Line Driver Amplifier Configurations



The values of RI and RF must be chosen with consideration of stability, frequency response and noise. The recommended value of RI is in the range from 1kΩ to 47kΩ, and RF is from 4.7kΩ to 100kΩ for. The gain is in the range from -1V/V to -10V/V for inverting configuration. Table 1 lists the recommended resistor values for different configurations.

RI (kΩ) RF (kΩ) Inverting Input

Gain (V/V) Non-inverting

Input Gain (V/V) Differential Input

Gain (V/V) 22 22 -1 2 1

15 30 -2 3 2

33 68 -2.1 3.1 2.1

10 100 -10 11 10

Table 1. Recommended Resistor Values

Second-Order Filter Configuration

AD22650B can be used like a standard OPAMP. Several filter topologies can be implemented by using AD22650B, both single-ended and differential input configuration, see figure 6. For inverting input

configuration, the overall gain is 12

RR

− , the high-pass filter’s cutoff frequency is 312

1CRπ

, the

low-pass filter’s cutoff frequency is 21322

1CCRRπ

, The detail component values are listed on table

2.

R2

R3C3

INOUT

(a) Inverting Input

R1

C1

C2

R2

R3C3IN-

OUT

(b) Differential Input

R1C1

C2

C3IN+ R1C1R2

R3

Figure 6. Second-order Active Low-Pass Filter



Gain (V/V)

High Pass (Hz)

Low Pass (kHz)

C1 (pF) C2 (pF) C3 (μF) R1 (kΩ) R2 (kΩ) R3 (kΩ)

-1 1.6 40 100 680 10 10 10 24

-1.5 1.3 40 68 680 15 8.2 12 30

-2 1.6 60 33 150 6.8 15 30 47

-2 1.6 30 47 470 6.8 15 30 43

-3.33 1.2 30 33 470 10 13 43 43

-10 1.5 30 22 1000 22 4.7 47 27

Table 2. Second-order Low-Pass Filter Specifications

Over-Temperature Protection AD22650B provide an over-temperature protection to limit the junction temperature to 150. As junction temperature exceeds 150, internal thermal sensor will turn off the drivers immediately. The drivers will turn on again if the junction temperature is smaller than 130. A 20 hysteresis is designed

to lower the average junction temperature during continuous thermal overload conditions, increasing lifetime of the chip.



Typical Application Circuit Inverting Input Line Driver Amplifier

LIN

P

LIN

N

OU

TL

EN PVSS

CN

SGN

D

RIN

P

RIN

N

OU

TR

UVP

PVD

D

CP

PGN

D

Cha

rge

Pum

p

Und

er

Volta

ge

Prot

ectio

n

Dep

op

Circ

uit

Ove

r Te

mpe

ratu

re

Prot

ectio

n

RF

RICIN1μF 10kΩ

20kΩ

RL2.5kΩ

RF

RICIN

1μF 10kΩ

20kΩ

RL

2.5kΩ

CFLY1μF

CPVSS1μF

Enable Control

L-ch Input

R-ch Input

R-ch Output

L-ch Output

LDO

1μF

R111.5kΩ R12

1kΩ

R1330kΩ

VSYSTEM

10μF

Non-inverting Input Line Driver Amplifier

LIN

P

LIN

N

OU

TL

EN PVSS

CN

SGN

D

RIN

P

RIN

N

OU

TR

UVP

PVD

D

CP

PGN

D

Cha

rge

Pum

p

Und

er

Volta

ge

Prot

ectio

n

Dep

op

Circ

uit

Ove

r Te

mpe

ratu

re

Prot

ectio

n

RF

RICIN1μF 10kΩ

20kΩ

RL2.5kΩ

CFLY1μF

CPVSS1μF

Enable Control

R-ch Output

LDO

1μF

R111.5kΩ R12

1kΩ

R1330kΩ

VSYSTEM

10μF

CIN1μF

R-ch Input

RX

RF

RICIN

1μF 10kΩ

20kΩ

RL

2.5kΩ

L-ch Output

CIN

1μF

L-ch Input

RX



Differential Input Line Driver Amplifier

LIN

P

LIN

N

OU

TL

EN PVSS

CN

SGN

D

RIN

P

RIN

N

OU

TR

UVP

PVD

D

CP

PGN

D

Cha

rge

Pum

p

Und

er

Volta

ge

Prot

ectio

n

Dep

op

Circ

uit

Ove

r Te

mpe

ratu

re

Prot

ectio

n

Inverting Input Second-Order Active Low-Pass Filter



Differential Input Second-Order Active Low-Pass Filter

LIN

P

LIN

N

OU

TL

EN PVSS

CN

SGN

D

RIN

P

RIN

N

OU

TR

UVP

PVD

D

CP

PGN

D

Cha

rge

Pum

p

Und

er

Volta

ge

Prot

ectio

n

Dep

op

Circ

uit

Ove

r Te

mpe

ratu

re

Prot

ectio

n

R2

R1C315kΩ

30kΩ

CFLY1μF

CPVSS1μF

Enable Control

R-ch Output

LDO

1μF

R111.5kΩ R12

1kΩ

R1330kΩ

VSYSTEM

10μFC147pFR3

43kΩ

C2470pF

6.8uF

R1C315kΩ

R-ch Input

R343kΩ

6.8uFC1

47pFR2

30kΩ

R2

R1C315kΩ

30kΩ

L-ch Output

C147pFR3

43kΩ

C2470pF

6.8uF

R1C315kΩ

L-ch Input R3

43kΩ

6.8uFC1

47pFR2

30kΩ



Package Outline Drawing TSSOP-14L

Min Max

A -- 1.20

A1 0.05 0.15

b 0.19 0.30

c 0.09 0.16

D 4.90 5.10

E 4.30 4.50

E1 6.30 6.50

e

L 0.45 0.75

0.65 BSC

SymbolDimension in mm



Revision History

Revision Date Description

0.1 2015.05.29 Initial version.

0.2 2016.02.24 Added UVP description into datasheet.



Important Notice

All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

3-vrms cap-less line driver with adjustable gain · the ad22650b is a 3-vrms cap-less stereo line...

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