3. asic and soc design methods: structured vlsi design spring 2009 rajesh k. gupta

3. ASIC and SOC Design Methods:Structured VLSI Design

Spring 2009

Rajesh K. Gupta

Outline

Circuit Styles The evolving ASIC Design Methodology

References: Basic Logic Families, Kerry Bernstein, Ch. 7, of A.

Chandrakasan et. al. book Chapter 11 of Rabaey book

Basic Logic Families

Circuit Styles Different possible circuit topologies for a given logic function (from

the same set of basic transistor devices) even within CMOS: compatible CMOS styles

Choice determined by design criteria: performance, power consumption, testability, ease of design (analysis)

Available styles Nonclocked logic (clocked logic discussed after clocking)

example: static combinatorial CMOS, differential cascode voltage-switch logic, pass-transistor logic

generally: low power, ease of automated synthesis, easy timing analysis, reliability and noise immunity, defect tolerance, migration across process.

Reliability because nodes maintain values (never left to float), direct control of nodal values (noise immunity), switch points can be varied.

Nonclocked: Static Combinatorial CMOS

Operate under “push-pull” action Transfer function

similar to the inverter transfer function unity gain point (UGP)

point on the transfer function where slope is -1 a circuit will attenuate inputs less than the lower UGP and amplify

inputs higher than the lower UGP switch point (SWP)

where Vin = Vout can be skewed by the effective device sizing by hastening transition

in a given direction noise margin

is the difference between the least positive up level of the preceding stage and the upper UGP of the given stage

or the most positive down level of the previous stage and the lower UGP of the given stage.

Static CMOS Delay variations

by the input pattern, by switching history by the active fanout load

depending upon the channel state, gate-substrate capacitance changes (towards inversion gate-substrate capacitance drops)

signal coupling in interconnect changes fanout load false switching (consumes about 15% of the total power)

Design rules Alpha ratio:

ratio of the total output capacitance on a given stage divided by its total input capacitance; (2.7 produces minimum PDP)

Beta ratio: ratio of a given stage’s PFET W/L to its NFET W/L

NAND n-stack design: body effect on the top device decreases its drive device tapering and signal positioning.

Domino CMOS

Domino logic is evaluated through single-sided transitions no need for complimentary logic implementations generally N-FET evaluation trees (smaller area)

To ensure single transitions, all outputs are inverted so that the inputs only make a transition from low to high

several issues related to capacitive coupling, noise immunity and false discharges

Pass-Gate Logic

Logic evaluation by signal coupling rather than by signal evaluation and redriving

Generally lower capacitive loads However, many liabilities

limited fan-in capability current discharge to ground through a pass-gate must be limited to

achieve acceptable low levels at the receiver excessive fan-out

the driver to pass gates (for example, output inverter driving subsequent pass gates) must be sized for all the paths its serves

noise vulnerability interconnect coupling can be propagated through a pass-gate

Body bias effects reduce available drive Path protection need for decoders: when used as mux, gate inputs are

needed to ensure paths are maintained. Improved by complementary pass-gate logic (CPL)

Structured VLSI Design

Four Phases in Creating a Chip

The Design Problem

Source: sematech97

A growing gap between design complexity and design productivity[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

VLSI-design Tools & Methodologies

Goal is to reduce complexity, increase productivity, and increase chances of a working chip

Key is the use of Constraints and Abstractions Constraints

help automate the procedure by simplifying the problem Abstractions

collapse detail and arrive at a simpler problem to deal with Different design methodologies

different types of constraints and trade-offs choice driven by economics!

Design Domains

Behavioral what a system does

Structural how entities are connected together to perform the behavior

Physical (geometrical) how to build a structure that has the required connectivity to

implement the prescribed behavior

Levels of Design Abstractions for Each Design Domain

Architectural Algorithmic Module or functional block Logical Switch Circuit Device etc.

Design Abstraction Levels

SYSTEM

GATE

CIRCUIT

VoutVin

CIRCUIT

VoutVin

MODULE

+

DEVICE

n+S D

n+

G

Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."

Design Methodology

Design process traverses iteratively between behavior, structure, and geometry abstractions

CAD tools providing more and more automation

Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

A Simplified Flow


Implementation Choices

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches


Transition to Automation and Regular Structures

Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy IntelAdapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Cell-based Design (or standard cells)

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cellR

ow

s o

f ce

lls


Standard Cell - Example

3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time


Automatic Cell Generation

Courtesy Acadabra

Initial transistorgeometries

Placedtransistors

Routedcell

Compactedcell

Finishedcell


MacroModules

25632 (or 8192 bit) SRAMGenerated by hard-macro module generator


“Soft” MacroModules

Synopsys DesignCompilerAdapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

“Intellectual Property”

A Protocol Processor for Wireless


Semicustom Design Flow

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

Des

ign

Iter

atio

nD

esig

n It

erat

ion


The “Design Closure” Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)


Integrating Synthesis with Physical Design

Physical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Place-and-RouteOptimization

Artwork

Netlist with Place-and-Route Info

MacromodulesFixed netlists



Pre-wired(FPGA's)

Array-based

Late-Binding Implementation

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based


Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches


Gate Array — Sea-of-gates

rows of

cells

routing channel

uncommitted

VD D

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)


Sea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation


Prewired Arrays

Classification of prewired arrays (or field-programmable devices):

Based on Programming Technique Fuse-based (program-once) Non-volatile EPROM based RAM based

Programmable Logic Style Array-Based Look-up Table

Programmable Interconnect Style Channel-routing Mesh networks


Antifuse

Normally high resistance (> 100 M)

on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (200-500)

Array-Based Programmable Logic

PLA PROM PAL

I 5 I 4

O0

I 3 I 2 I 1 I 0

O1O2O3

Programmable AND array

ProgrammableOR array I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O0

I3 I2 I1 I0

O1O2O3

Fixed AND array

ProgrammableOR array


Programming a PROM

f0

1 X 2 X 1 X 0

f1NANA

: programmed node


2-input mux as programmable logic block

FA 0

B

S

1

Configuration

A B S F=

0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X 1 Y1 0 X1 0 Y1 1 1 1

XYXY

XY


Logic Cell of Actel Fuse-Based FPGA

A

B

SA Y

1

C

D

SB

1

S0S1

1


Look-up Table Based Logic Cell

Out

ln1 ln2

Me

mory In Out

00 00

01 1

10 1

11 0


LUT-Based Logic Cell

Courtesy Xilinx

D4

C1....C4

xxxxxx

D3

D2

D1

F4

F3

F2

F1

Logicfunction

ofxxx

Logicfunction

ofxxx

Logicfunction

ofxxx

xx

xx

4

xxxxxx

xxxxxxxx

xxx

xxxx xxxx xxxx

HP

Bitscontrol

Bitscontrol

Multiplexer Controlledby Configuration Program

x

xx

x

xx

xxx xx

xxxx

x

xxxxxx

xx

x

xx

xxx

xx

Xilinx 4000 Series


Array-Based Programmable Wiring

Input/output pinProgrammed interconnection

InterconnectPoint

Horizontaltracks

Vertical tracks

Cell

M


Mesh-based Interconnect Network

Switch Box

Connect Box

InterconnectPoint

Courtesy Dehon and WawrzyniekAdapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Transistor Implementation of Mesh


Hierarchical Mesh Network

Use overlayed meshto support longer connections

Reduced fanout and reduced resistance


EPLD Block Diagram

MacrocellPrimary inputs

Courtesy AlteraAdapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Altera MAX

From Smith97Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Altera MAX Interconnect Architecture

LAB2

PIA

LAB1

LAB6

tPIA

tPIA

row channelcolumn channel

LAB

Courtesy Altera

Array-based(MAX 3000-7000)

Mesh-based(MAX 9000)


Field-Programmable Gate ArraysFuse-based

I/O Buffers

P rogram/Test/Diag nostics

I/O Buffers

I/O B

uffe

rs

I/O B

uffe

rs

Vertical ro utes

Rows o f logic m odule s

Routing channels

Standard-cell likefloorplan


Xilinx 4000 Interconnect Architecture

2

12

8

4

3

2

3

CLB

8 4 8 4

Quad

Single

Double

Long

DirectConnect

DirectConnect

Quad Long GlobalClock

Long Double Single GlobalClock

CarryChain

Long

12 4 4

Courtesy XilinxAdapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

RAM-based FPGA

Xilinx XC4000ex

Courtesy XilinxAdapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Architecture ReUse

Silicon System Platform Flexible architecture for hardware and software Specific (programmable) components Network architecture Software modules Rules and guidelines for design of HW and SW

Has been successful in PC’s Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints) Speed (compute power) Dissipation Costs Real / non-real time data


Source:R.Newton

Platform-Based Design

A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer

New platforms will be defined at the architecture-micro-architecture boundary

They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations

Key to such approaches is the representation of communication in the platform model


Heterogeneous Programmable Platforms

Xilinx Vertex-II Pro

Courtesy Xilinx

High-speed I/O

Embedded PowerPcEmbedded memories

Hardwired multipliers

FPGA Fabric


Principles of Structured Design Techniques

Hierarchy

Regularity

Modularity

Locality

Source: Mani Srivastava, UCLA

Hierarchy

Divide and conquer compose system from simpler widgets

Analogy with software break large programs into threads and subroutines

Hierarchy can be there in all domains behavior, structural, physical

The hierarchy in different domains may not correspond

e.g. a structural hierarchy may not map well to physical


Example of Structural Hierarchy


Example of Physical Hierarchy


Example of Structural Hierarchy


Example of Physical Hierarchy


Repartitioning Structural Hierarchy to Fit Physical Hierarchy


Regularity

Hierarchy breaks a system into submodules but this may not solve the complexity problem there may not be any regularity in the subdivision

we just end up with a large # of different submodules

Regularity as a guide subdivide into a set of similar building blocks

e.g. RAM composed of identical cells

Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible


Regularity (contd.)

Regularity can be at all levels circuit: use identically sized transistors gate: similar gate structures higher level: architectures with identical processors

Regularity helps in many ways correct by construction reuse of design simplify verification of correctness


Circuit-level Regularity Example

A 2-1 Mux D-type edge triggered

flipflop One-bit full add

All designed using inverter and tristate buffer


Modularity

Condition that submodules have “well-defined” functions and interfaces

in addition to regularity and hierarchy ‘Well-formed” modules allow their interaction with

others to be “well-characterized” Depends on the situation

e.g. in s/w a subroutine has a well-defined interface argument list with typed variables

e.g. in IC a well-defined physical, structural, and behavioral interface

pin position, layer, size, signal type, electrical characteristics, logic function


Why Modularity?

Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combined

Allows team design by a number of designers Examples:

bad use: use of transmission gates as inputs internal signals now depend on source impedance

bad use: use dynamic CMOS logic but fail to latch or register the inputs

timing of each module will have to be checked


Locality

Modularity provided “well-characterized” interfaces internals of modules unimportant to exterior interface

internal details remain at the local level a form of “information hiding”

reduces apparent complexity of the module

Locality ensures that connections are between neighboring modules, avoiding long-distance connections

Example: timing locality so that time critical operations are local clock generation and distribution network entire clock cycle for global signals to traverse chip placement so that global wiring is minimized

Analogy with software global variables are to be avoided


Parallels between H/W & S/W Design

Strong parallels in the way VLSIs are designed and the way complex software is

HDLs used to describe hardware systems in essence merge these two disciplines

software methods used to define hardware Hardware-software Co-design But, can’t ignore hardware aspects entirely

important since a physical chip is the end product


3. asic and soc design methods: structured vlsi design spring 2009 rajesh k. gupta

Documents

design complexity

design productivity

structured vlsi design

design criteria

chip slide

gupta slide

ucb slide

levels of design abstractions