2016/1/30 jackie kan - 2007 12016/1/30ntu dsd (digital system

112/05/03 Jackie Kan - 2007 ([email protected]/[email protected])http://linton.1d24h.com/~jackiekan/ 1112/05/03 NTU DSD (Digital System Design)

20071

Digital System Design 2007

Jackie Kan

112/05/03 Jackie Kan - 2007 ([email protected]/[email protected])http://linton.1d24h.com/~jackiekan/ 2

Computer


Basic CPU Block Diagram


Digital Systems A collection of interconnected digital modules designed to

perform a particular service or functions Applications

Computers Microprocessors Embedded Systems Special Purpose Systems


Digital Systems Hardware Design Modules High Level Digital Design Module

Microprocessor Microcontroller PLD ASIC FPGA

Low Level Digital Design Module Logic Gates

AND, OR, NOT, NAND, NOR, XOR, … Block Diagrams

Adder, Subtractor, Shifter, Counter, … Implementation Method

PCB - Printed Circuit Board FPGA - Field Programmable Gate Array


PCB - Printed Circuit BoardSource: http://home.cogeco.ca, http://www.chinaforge.com/, http://www.unitechelectronics.com/


Example PCB Layout


Example PCB Board


FPGA - Field Programmable Gate ArraySource: http://www.entegra.co.uk, http://www.beis.de


Byte Blaster - FPGA Download Cable (1/5)Source: http://www.serielectronique.com, http://perso.orange.fr


Byte Blaster - FPGA Download Cable (3/5)Source: http://perso.orange.fr, http://www.mcu123.com


Byte Blaster - FPGA Download Cable (4/5)Source: http://opencollector.org


Byte Blaster II - FPGA Download Cable (1/11)Source: ALTERA


Byte Blaster II - FPGA Download Cable (3/11)Source: ALTERA


Byte Blaster II - FPGA Download Cable (4/11) Programming Modes

Joint Test Action Group (JTAG) Mode Programs or configures all Altera devices supported by the Quartus II

software Excluding FLEX 6000 devices

In-Socket Programming Mode Not supported by the ByteBlaster II cable

Passive Serial (PS) Programming Mode Configures all Altera devices supported by the Quartus II software Excluding MAX 3000 and MAX 7000 devices

Active Serial (AS) Programming Mode Programs a single EPCS1, EPCS4, EPCS16, or EPCS64 serial configuration

device

Source: ALTERA


Digital System Design Related Course 數位電子學 (Digital Electronics)

主要在學習基本電路的特性，各種電路元件如電阻、電容、電晶體等，基本邏輯運算概念，和其與電晶體的關係。離散數學 (Discrete Mathematics)

為許多學科的基礎數學知識，如演算法、線性代數、邏輯設計等等。包括了代數、組合數學、圖論等。對電腦的很多領域關係都相當密切、重要。計算機組織與組合語言 (Computer Organization and Assembly Languages)

組合語言可說是一種按照電腦行事方式設計的一種語言，與先前所學的程式語言不同，這種語言是機器較能看得懂的語言。所以熟悉組合語言後，對於電腦這種機器裡面是如何做事，會有更清楚的概念。數位電路實驗 (Digital Circuit Lab.)

等於是將大二的數位電子學做個實際的應用。運用以前所習知識，利用各種晶片及其他電路裝置，根據邏輯與晶片特性來組合製造出一些成品，如加法器、平交道紅綠燈等。數位系統設計 (Digital System Design)

利用數位電子學所學到的元件，以及離散數學裡代數的觀念，達到我們想要的功能，如加法器等。計算機結構 (Computer Architecture)

電腦核心的製造原理，軟體與硬體的介面設計，硬體效率的提昇等等方面加以介紹。


Computer Organization & Computer Architecture Computer architecture ( 計算機結構 )

計算機結構是指程式師能看到的計算機時什麼樣子 Refers to those attributes of a system visible to a programmer or,

put another way, those attributes that have a direct impact on the logical execution of a program.

Computer organization ( 計算機組織 ) 計算機組織是指計算機的邏輯組成與其交互連接 Refers to the operational units and their interconnections that

realize the architectural specifications. Example:

Architecture Multiply instruction ( 乘法指令 )

Organization 指實作之方式 Implement by Multiply-Unit ( 乘法器單元 ) Implement by Adder-Unit ( 加法器單元 )


Two Major Hardware Description Languages Verilog

Slightly better at gate/transistor level Language style close to C/C++ Pre-defined data type, easy to use

VHDL Slightly better at system level Language style close to Pascal User-defined data type, more flexible

Equally effective, personal preference


Taste of Verilog

Module portsModule name

Verilog keywords

module Add_half ( sum, c_out, a, b ); input a, b;

output sum, c_out;wire c_out_bar;

xor (sum, a, b);nand (c_out_bar, a, b);not (c_out, c_out_bar);

endmodule

Declaration of port modes

Declaration of internal signalInstantiation of primitive gates

c_out

ab sum

c_out_bar


Example of Flip-flop in Verilogmodule Flip_flop ( q, data_in, clk, rst );input data_in, clk, rst;output q;reg q;

always @ ( posedge clk ) begin

if ( rst == 1) q = 0;else q = data_in;

endendmodule

data_in

q

rst

clk

Declaration of synchronous behavior

Procedural statement

2016/1/30 jackie kan - 2007 12016/1/30ntu dsd (digital system

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