2005 itrs work in progress – do not publish 1 international technology roadmap for semiconductors...
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2005 ITRS Work in Progress – Do Not Publish
1
International Technology Roadmap for Semiconductors
2005 ITRS/ORTC Product ModelsFor Public 12/13/05 Conference
Seoul, Korea
(Rev 1, 12/12/05)
2005 ITRS Work in Progress – Do Not Publish
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ORTC Overview - 2005 ITRS Proposals• Recommendation for one standard TWG table technology trend header
– Presently continue to use DRAM stagger-contacted M1 as typical industry lithography driver – UNCHANGED from the 2003/2004 Roadmap Update
– Remove ITRS single-product “node” label emphasis, to minimize industry guidance confusion; as we transition to product-oriented technology trend drivers and cycles*
• ORTC Table 1a,b - adjusted to Proposed Japan (STRJ) MPU/ASIC M1 Half-Pitch Trend
– Stagger-contacted, same as DRAM– 2.5-year Technology Cycle* (.5x/5yrs) – 180nm/2000; 90nm/2005; 45nm/2010(equal DRAM)– Then continue on a 3-year Technology Cycle*, equal to DRAM 2010-2020
• ORTC Table 1a,b - added Proposed STRJ Flash Poly (Un-contacted dense lines)– 2-year Technology Cycle* (0.5x/4yrs)– 180nm/2000; 130nm/2002; 90nm/2004; 65nm/2006– Then 3-year Technology Cycle* 1 year ahead of DRAM ’06-’20
• ORTC Table 1a,b – adjusted MPU/ASIC Printed Gate Length to FEP and Litho TWG agreement for ratio relationship to Final Physical Gate Length, which remains UNCHANGED from the 2005 ITRS targets (3-year cycle* after 2005)
• TWG table Product-specific technology trend driver header items to be added to individual TWG tables from ORTC Table 1a&b
• Chip Size Models connected to proposals and historical trends, incl. new Flash Model
– Function Size [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)]– Functions/Chip [Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU]– Chip Size [hp MPU; cp MPU; DRAM; Flash]
*Note: Cycle = time to 0.5xlinear scaling every two
cycle periods ~ 0.71x/ cycle
2005 ITRS Work in Progress – Do Not Publish
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Source: 2003 ITRS - Exec. Summary Fig 4
2003/2004 ITRS Definition of the Half Pitch - WAS [DRAM half-pitch determines the 2003 ITRS “node”]
Metal Pitch
Typical DRAM Metal Bit Line
DRAM ½ Pitch = DRAM Metal Pitch/2
Poly Pitch
Typical MPU/ASIC Un-contacted Poly
MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2
Typical MPU/ASICContacted Metal 1
MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2
Metal 1 (M1) Pitch
2005 ITRS Work in Progress – Do Not Publish
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2005 Definition of the Half Pitch – IS[No single-product “node” designation; DRAM half-pitch still litho driver; however,
other product technology trends may be drivers on individual TWG tables]
Metal Pitch
Typical DRAM/MPU/ASIC Metal Bit Line
DRAM ½ Pitch = DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Poly
Pitch
Typical flash Un-contacted Poly
FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2
8-16 Lines
2005 ITRS Work in Progress – Do Not Publish
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Production Ramp-up Model and Technology NodeV
olu
me
(Par
ts/M
on
th)
1K
10K
100K
Months0-24
1M
10M
100M
Alpha
Tool
12 24-12
Development Production
Beta
Tool
Production
Tool
First
Conf.
Papers
First Two Companies
Reaching Production
Vo
lum
e (W
afer
s/M
on
th)
2
20
200
2K
20K
200K
Source: 2003 ITRS - Exec. Summary Fig 2
Fig 2 [UNCHANGED, except for “node” reference] IS: Cycle Timing
2005 ITRS Work in Progress – Do Not Publish
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hp22hp32hp45hp65hp90
20182016
20152013
20122010
20092007
20062004
20032002[Actual]
Year of Production
hp130Technology Node (nm)
WAS: 2003 ITRS Technology Nodes: 3-year cycle*
3-Year Technology Cycle2-Year Technology Cycle [1998-2002actual]
Note: Faster introduction of half-poly pitch from Flash is expected; and Doubling of transistors every 2 years from MPU/ASIC is expected.* Cycle Time = one-half of the time to reach a technology trend reduction to 0.5x
Source: 2003 ITRS - Exec. Summary
Past Future
DRAM hpXX “Node” designationWas added in 2003 ITRS
2005 ITRS Work in Progress – Do Not Publish
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Note: Faster introduction of half-poly pitch from Flash is expected; Doubling of transistors every 2 years from MPU/ASIC is expected
2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 1yr ahead of DRAM @65nm/’06
3-Year Technology Cycle2-Year Technology Cycle [’98-’06 ]
Year of Production
Technology -UncontactedPoly H-P (nm)
2003 20052001
65 223245 16
2008
20062002[Actual]
20042000[Actual]
90130180
76107151 5057 13
201520122009 2018
201620132010 2019 2020
2005 ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal DRAM @45nm/2010
Year of Production
Technology- ContactedM1 H-P (nm)
157 136 119 103 78 68 59 52
201620132010 2019[July’08][July’02] 20052000
201820152012 2020
[130]180 [ 65]90 2232 1645
2008200620032001 2002 2004 2007 2009
2.5-Year Technology Cycle3-2-Yr Cycle] 3-Year Technology Cycle
14
IS: 2005 (’05-’20) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle
3-Year Technology Cycle2-Year Technology Cycle [‘98-’04]
Year of Production
Technology - ContactedM1 H-P (nm)
201820152012 2020
201620132010 2019
2003 20052001
65 223245 16
20082006 2009
20072002[Actual]
20042000[Actual]
90130180
80107151 71 57 50 14
10
2005 ITRS Work in Progress – Do Not Publish
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Figure 7& 8 ITRS Product Technology TrendsFig 7&8 Simplified – Option 1
2005 ITRS Product Technology Trends - Half-Pitch, Gate-Length
1.0
10.0
100.0
1000.0
1995 2000 2005 2010 2015 2020
Year of Production
Pro
du
ct H
alf-
Pit
ch, G
ate-
Len
gth
(n
m)
DRAM M1 1/2 Pitch
MPU M1 1/2 Pitch(2.5-year cycle)
Flash Poly 1/2 Pitch
MPU Gate Length -Printed
MPUGate Length -Physical
MPU M1.71X/2.5YR
Nanotechnology (<100nm) Era Begins -1999
GLpr IS =1.6818 x GLph
2005 - 2020 ITRS Range
MPU & DRAM M1& Flash Poly
.71X/3YR
Flash Poly.71X/2YR
Gate Length.71X/3YR
Before 1998 .71X/3YR
After 1998.71X/2YR
2005 ITRS Work in Progress – Do Not Publish
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2005 ITRS Product Function Size Trends - Cell Size, Logic Gate(4t) Size
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
2000 2005 2010 2015 2020
Year of Production
Cel
l, L
og
ic G
ate
Siz
e(u
m2
)
DRAM Cell Size (u2)
Flash Cell Size (u2)SLC(NEW)
Flash Eqv.bit Size(u2)MLC(NEW)
MPU SRAM Cell Size(6t)(u2)
MPU Gate Size (4t)(u2)
Note for Flash: SLC = Single-Level-Cell Size
MLC =Multi-Level-Cell
(Electrical Equivalent) Cell Size
2005 - 2020 ITRS Range
Figure xx ITRS Product Function Size (NEW)Fig xx Simplified
(@ 2 MLC bits/physical cell area)
Flash: 4f2 LastDesign Physical AreaFactor Improvement
DRAM: 5f2 LastDesign Area
Factor Improvement
Logic Gate: NODesign Area
Factor Improvement(Only Scaling)
SRAM: GradualDesign Area
Factor Improvement
Flash: (MLC @ 2 bits/cell =
2f2 EquivalentArea Factor)
2005 ITRS Work in Progress – Do Not Publish
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Moore’s Law After 40 years (functions per chip)
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
10,000,000,000
1970 1980 1990 2000 2010
40048080
8086
8008
Pentium® Processor
486™ DX Processor386™ Processor
286
Pentium® II Processor
Pentium® III Processor
Itanium® Processor
Pentium® 4 Processor
Itanium® 2 Processor2X/2YR
2X/1YR
2X/2YR
Source: Intel® Corp.Past Future
2005 ITRS Work in Progress – Do Not Publish
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2005 ITRS Product Technology Trends Functions/Chip
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020
Year of Production
Pro
duct
Fun
ctio
ns/C
hip
(Gig
a (1
0^9)
- b
its, t
rans
isto
rs )
Flash Bits/Chip (Gbits) Single-Level-Cell(SLC )
Flash Bits/Chip (Gbits) Multi-Level-Cell(MLC)
MPU GTransistors/Chip - high-performance(hp)
MPU GTransistors/Chip - cost-performanc(cp)
DRAM Bits/Chip (Gbits)
Average Industry "Moores Law"
Chip Size Trends – 2005 ITRS Functions/Chip Model Proposal IS
Past Future2005 - 2020 ITRS Range
AverageIndustry 1970-2020
“Moore’s Law”2x Functions/chip
Per 2 years
(@Volume Production, Affordable Chip Size**)
** Affordable Production
Chip Size Targets:DRAM, Flash < 145mm2
hp MPU < 310mm2
cp MPU < 140mm2
** Example Chip Size Targets:1.1Gt P07h MPU
@ intro in 2004/620mm2
@ prod in 2007/310mm2
** Example Chip Size Targets:0.39Gt P07c MPU
@ intro in 2004/280mm2
@ prod in 2007/140mm2
MPU ahead or =“Moore’s Law”2x Xstors/chipPer 2 years Thru 2010
2005 ITRS Work in Progress – Do Not Publish
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2005 ITRS Product Technology Trends - Functions per Chip
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1995 2000 2005 2010 2015 2020
Year of Production
Pro
du
ct F
un
ctio
ns/
Ch
ip[
Gig
a (1
0^9)
- b
its,
tra
nsi
sto
rs ]
Flash Bits/Chip (Gbits)Single-Level-Cell (SLC )
Flash Bits/Chip (Gbits)Multi-Level-Cell (MLC)
MPU GTransistors/Chip -high-performance (hp)
MPU GTransistors/Chip -cost-performanc (cp)
DRAM Bits/Chip (Gbits)
Average Industry "Moores Law"
2005 - 2020 ITRS Range
AverageIndustry 1970-2020
“Moore’s Law”2x Functions/chip
Per 2 years
Figure yy ITRS Product Functions per Chip (NEW)
2005 ITRS Work in Progress – Do Not Publish
13Past Future 2005 - 2020 ITRS Range
Chip Size Trends – 2003/04 vs.2005 ITRS DRAM & Flash (NEW) Model IS
2005 Proposal ITRS DRAM Chip Size Model(Rev 1K, 06/23/05)
0
100
200
300
400
500
600
700
1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025
Year of Introduction and Production
(mm
2) DRAM Introduction Chip Size
Sawada Production Chip Size IS
4 chips per Litho Field @ 572mm2 = 143mm2
(22x6.5)
4G 8G 32G 64G16G
Bits/
chip: 128G64M
Bits/
chip:
256M
128G
1G 2G
4G
8G 32G 64G
16G
256G 1T
512M
Prod Cell Area Efficiency (CAE) = 63%-56%
Intro Cell Area Efficiency (CAE) = 73%-75%
90 64 45 22 1632 11 8
5 chips per Litho Field @ 704mm2 = 141mm2
(22x6.4)
WAS/IS: 128180255360
128M
32G
16G
4G
8G
2G
32G
16G
64G2G
8.0 6.011 8.0 8.0 8.0 6.0 6.0 6.06.0DRAM Des.
Factor: 11 6.0 6.0
DRAM
Max Litho Field 2005 ITRS (4x) : 834mm2 (26x32)
2 C
hip
s p
er
Ma
x L
itho
Fie
ld 2
00
5
ITR
S (
4x)
: 4
17
m2
(2
6x
16
)
2005 ITRS Work in Progress – Do Not Publish
14Past Future 2005 - 2020 ITRS Range
Chip Size Trends – 2003/04 vs.2005 ITRS Flash (NEW) Model IS2005 Proposal ITRS Flash chip Size (NEW) Model (Allan)
(Rev 1K, 06/23/05)
0
100
200
300
400
500
600
700
1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025
Year of Introduction and Production
(mm
2)
Flash SLC Production Chip Size
4 chips per Max Affordable Litho Field @
572mm2 = 143mm2 (22x6.5)
Flash Prod Cell Area Efficiency (CAE) = 67%
Flash Intro Cell Area Efficiency (CAE) =TBD -
no model
5 chips per Max Affordable Litho Field @
704mm2 = 141mm2 (22x6.4)
Flash
Bits/chip: 4G 8G 16G 32G 64G 128G256M 1G64M 2G
16 4.032 8.0 4.0 4.0 4.0 4.0 4.04.0 Flash SLC
Des.Factor: 4.0 4.0
128180255360Flash: 90 64 45 22 1632 11 8WAS/IS: 128180255360
8.0 6.011 8.0 8.0 8.0 6.0 6.0 6.06.011 6.0 6.0
90 64 45 22 1632 11 8
DRAM
HP
DRAM Des.
Factor:
2005 ITRS Work in Progress – Do Not Publish
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2005 Proposal ITRS MPU Chip Size Model (Rev 1K, 06/23/05)
0
100
200
300
400
500
600
700
1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025
Year of Introduction and Production
(mm
2)
MPU hp Production Chip Size
MPU cp Production Chip Size
MPU hp Introduction Chip Size
MPU cp Introduction Chip Size
DRAM
HP
8G
SRAM Cell Efficiency= 60%Logic Gate Efficiency = 50%
p13c1.5Bt
p16c3.1
p19c p22c
800
Max Litho Field 2005 ITRS (4x): 834mm2 (26x32)
2 C
hip
s p
er
Ma
x L
itho
Fie
ld
2
00
5 I
TR
S (
4x)
: 4
17
m2
(2
6x
16
)
Max Litho Field - Future ITRS? (8x): 208mm2 (13x16)?
p07h1.1Bt
p10h2.2Bt
p07h
1.1Bt
p16h p19h p22hp10h
2.2Bt
p13h
4.4Bt
p02h276Mt
p00h138Mt
p98h69Mt
p04h552Mt
p10c768Mt
hp MPU = 82% SRAM Transistors, 18% Core Logic Transistors
cp MPU = 58% SRAM Transistors, 42% Core Logic Transistors
p02h
276Mt
p04h
552Mt
26% / 2yrsChip Size Growth
p04c192Mt
p02c96Mt
p00c48Mt
p07c384Mt
p07c384Mt
p10c768Mt
p04c96Mt
p02c96Mt
p00c48Mt
p13c1.5Bt
Affordable hp MPU prod Target: 310mm2
Affordable cp MPU prod Target: 140mm2
90 64 45 22 1632 11 8WAS/IS: 12818025536090 68 45 22 1632 11 8
[2
MPU: 136180255360 [2.5yr Technology Cycle
2000- 2010]
Past Future 2005 - 2020 ITRS Range
Chip Size Trends – 2005 ITRS MPU Model Proposal IS
2005 ITRS Work in Progress – Do Not Publish
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Summary• DRAM Model stagger-contacted M1 is unchanged from
2003/2004 Update ITRS (single-“Node” reference removed)• MPU Revised M1 to stagger-contact half-pitch (same as
DRAM) and 2.5-year cycle* through 2010, then 3-year cycle* same as DRAM
• New Flash Model Added for un-contacted poly half-pitch and equal to DRAM contacted, but continues on 2-year cycle* to 1 year ahead of DRAM in 2006, then 3-year cycle* same as DRAM
• Printed MPU/ASIC Gate Length adjusted to new FEP and Litho TWGs ratio agreement, but Physical GL unchanged and on 3-year cycle* beginning 2005
• Historical chip size models “connected” to new Product model proposals, including design factors, function size, and array efficiencies
• Average industry product “Moore’s Law” met or exceeded throughout 2005-2020 ITRS timeframe
[* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
2005 ITRS Work in Progress – Do Not Publish
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Backup
Note: ITRS Table Colorization Code Reference:
Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known Interim solutions are known
Manufacturable solutions are NOT known
2005 ITRS Work in Progress – Do Not Publish
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ORTC Table 1a,b (Near, Long Term) (Draft 04 review 10/31/05):
Table 1a Product Generations and Chip Size Model Technology Trend Targets—Near-term Years Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013
DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 36 32
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 90 78 68 59 52 45 40 36 32
MPU Printed Gate Length (nm) †† 54 48 42 38 34 30 27 24 21
MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13 ASIC/Low Operating Power Printed Gate Length (nm) ††
76 64 54 48 42 38 34 30 27
ASIC/Low Operating Power Physical Gate Length (nm)
45 38 32 28 25 23 20 18 16
Flash ½ Pitch (nm) (un-contacted Poly)(f) 76 64 57 51 45 40 36 32 28
Table 1b Product Generations and Chip Size Model Technology Trend Targets—Long-term Years Year of Production 2014 2015 2016 2017 2018 2019 2020
DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 28 25 22 20 18 16 14
MPU Printed Gate Length (nm) †† 19 17 15 13 12 11 9
MPU Physical Gate Length (nm) 11 10 9 8 7 6 6
ASIC/Low Operating Power Printed Gate Length (nm) †† 24 21 19 17 15 13 12
ASIC/Low Operating Power Physical Gate Length (nm) 14 13 11 10 9 8 7
Flash ½ Pitch (nm) (un-contacted Poly)(f) 25 23 20 18 16 14 13
2005 ITRS Work in Progress – Do Not Publish
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ORTC DRAM & Flash Prod Table 1c (Near Term) (Draft 04 review 10/31/05):Table 1c DRAM & Flash Production Product Generations and Chip Size Model—Near-term Years
Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013
DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 36 32
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 90 78 68 59 52 45 40 36 32
MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13
DRAM Product Table
Cell area factor [a] 8 8 8 6 6 6 6 6 6
Cell area [Ca = af2] (mm2) 0.051 0.041 0.032 0.019 0.015 0.012 0.0096 0.0077 0.0061
Cell array area at production (% of chip size) § 63.00% 63.00% 63.00% 56.08% 56.08% 56.08% 56.08% 56.08% 56.08%
Generation at production § 1G 2G 2G 2G 4G 4G 4G 8G 8G
Functions per chip (Gbits) 1.07 2.15 2.15 2.15 4.29 4.29 4.29 8.59 8.59
Chip size at production (mm2)§ 88 139 110 74 117 93 74 117 93
Gbits/cm2 at production § 1.22 1.54 1.94 2.91 3.66 4.62 5.82 7.33 9.23
Flash Product Table Alternate STRJ Proposal (Cross-over DRAM) Flash ½ Pitch (nm) (un-contacted Poly)(f)
75.7 63.6 56.7 50.5 45.0 40.1 35.7 31.8 28.3
Alternate STRJ Proposal (Cross-over DRAM) Cell area factor [a]
4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0
Cell area [Ca = af2] (mm
2) 0.023 0.016 0.013 0.010 0.008 0.006 0.005 0.004 0.003
Cell array area at production (% of chip size) § 67.5% 67.5% 67.5% 67.5% 67.5% 67.5% 67.5% 67.5% 67.5%
Generation at production § SLC 4G 4G 4G 8G 8G 8G 16G 16G 16G
Generation at production § MLC 8G 8G 8G 16G 16G 16G 32G 32G 32G
Functions per chip (Gbits) SLC 4.29 4.29 4.29 8.59 8.59 8.59 17.18 17.18 17.18
Functions per chip (Gbits) MLC 8.59 8.59 8.59 17.18 17.18 17.18 34.36 34.36 34.36
Chip size at production (mm2)§ SLC 144 101.8 80.8 128.3 101.8 80.8 128.3 101.8 80.8
Chip size at production (mm2)§ MLC 144 101.8 80.8 128.3 101.8 80.8 128.3 101.8 80.8
Gbits/cm2 at production § SLC 3E+09 4.2E+09 5.3E+09 6.7E+09 8.4E+09 1.1E+10 1.3E+10 1.7E+10 2.1E+10
Gbits/cm2 at production § MLC 6E+09 8.4E+09 1.1E+10 1.3E+10 1.7E+10 2.1E+10 2.7E+10 3.4E+10 4.3E+10
2005 ITRS Work in Progress – Do Not Publish
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ORTC DRAM & Flash Prod Table 1d (Long Term) (Draft 04 review 10/31/05):Table 1d DRAM & Flash Production Product Generations and Chip Size Model—Long-term Years
Year of Production 2014 2015 2016 2017 2018 2019 2020
DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 28 25 22 20 18 16 14
MPU Physical Gate Length (nm) 11 10 9 8 7 6 6
DRAM Product Table
Cell area factor [a] 6 6 6 6 6 6 6
Cell area [Ca = af2] (mm2) 0.0048 0.0038 0.0030 0.0024 0.0019 0.0015 0.0012
Cell array area at production (% of chip size) § 56.08% 56.08% 56.08% 56.08% 56.08% 56.08% 56.08%
Generation at production § 8G 16G 16G 16G 32G 32G 32G
Functions per chip (Gbits) 8.59 17.18 17.18 17.18 34.36 34.36 34.36
Chip size at production (mm2)§ 74 117 93 74 117 93 74
Gbits/cm2 at production § 11.63 14.65 18.46 23.26 29.31 36.93 46.52
Flash Product Table Alternate STRJ Proposal (Cross-over DRAM) Flash ½ Pitch (nm) (un-contacted Poly)(f)
25.3 22.5 20.0 17.9 15.9 14.2 12.6
Alternate STRJ Proposal (Cross-over DRAM) Cell area factor [a] 4.0 4.0 4.0 4.0 4.0 4.0 4.0
Cell area [Ca = af2] (mm
2) 0.003 0.002 0.002 0.001 0.001 0.001 0.001
Cell array area at production (% of chip size) § 67.5% 67.5% 67.5% 67.5% 67.5% 67.5% 67.5%
Generation at production § SLC 32G 32G 32G 64G 64G 64G 128G
Generation at production § MLC 64G 64G 64G 128G 128G 128G 256G
Functions per chip (Gbits) SLC 34.36 34.36 34.36 68.72 68.72 68.72 137.44
Functions per chip (Gbits) MLC 68.72 68.72 68.72 137.44 137.44 137.44 274.88
Chip size at production (mm2)§ SLC 128.3 101.8 80.8 128.3 101.8 80.8 128.3
Chip size at production (mm2)§ MLC 128.3 101.8 80.8 128.3 101.8 80.8 128.3
Gbits/cm2 at production § SLC 2.7E+10 3.4E+10 4.3E+10 5.4E+10 6.7E+10 8.5E+10 1.1E+11
Gbits/cm2 at production § MLC 5.4E+10 6.7E+10 8.5E+10 1.1E+11 1.3E+11 1.7E+11 2.1E+11
2005 ITRS Work in Progress – Do Not Publish
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ORTC Table DRAM Intro 1e,f (Near, Long Term) (Draft 04 review 10/31/05):
Table 1e DRAM Introduction Product Generations and Chip Size Model—Near-term Years Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013
DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 36 32
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (f) 90 78 68 59 52 45 40 36 32
MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13
Cell area factor [a] 8 8 8 6 6 6 6 6 6
Cell area [Ca = af2] (mm2) 0.051 0.041 0.032 0.019 0.015 0.012 0.010 0.008 0.006
Cell array area at introduction (% of chip size) § 72.95% 73.25% 73.52% 73.76% 73.97% 74.16% 74.30% 74.47% 74.61%
Generation at introduction § 8G 8G 16G 16G 16G 32G 32G 32G 64G
Functions per chip (Gbits) 8.59 8.59 17.18 17.18 17.18 34.36 34.36 34.36 68.72
Chip size at introduction (mm2) § 606 479 757 449 356 563 446 353 560
Gbits/cm2 at introduction § 1.42 1.79 2.27 3.82 4.83 6.10 7.70 9.73 12.28
Table 1f DRAM Introduction Product Generations and Chip Size Model—Long-term Years Year of Production 2014 2015 2016 2017 2018 2019 2020
DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (f) 28 25 22 20 18 16 14
MPU Physical Gate Length (nm) 11 10 9 8 7 6 6
Cell area factor [a] 6 6 6 6 6 6 6
Cell area [Ca = af2] (mm2) 0.005 0.004 0.003 0.002 0.002 0.002 0.001
Cell array area at introduction (% of chip size) § 74.70% 74.83% 74.93% 75.00% 75.09% 75.18% 75.27%
Generation at introduction § 64G 64G 128G 128G 128G 256G 256G
Functions per chip (Gbits) 68.72 68.72 137.44 137.44 137.44 274.88 274.88
Chip size at introduction (mm2) § 444 351 557 442 350 555 440
Gbits/cm2 at introduction § 15.49 19.55 24.67 31.11 39.24 49.50 62.44
2005 ITRS Work in Progress – Do Not Publish
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ORTC MPU cp Table 1g (Near Term) (Draft 04 review 10/31/05):Table 1g MPU (High-volume Microprocessor) Cost-Performance Product Generations and
Chip Size Model—Near-term Years Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013
DRAM ½ Pitch (nm) (contacted) 80 70 65 57 51 45 40 36 32
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (f) 90 78 68 59 52 45 40 36 32
MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13
SRAM Cell (6-transistor) Area factor ++ 115.6 113.7 111.9 110.4 109.0 107.8 106.7 105.7 104.8
SRAM Cell (6-transistor) Area factor ++ 91.8 94.5 97.5 100.7 104.1 107.8 106.7 105.7 104.8
Logic Gate (4-transistor) Area factor ++ 320 320 320 320 320 320 320 320 320
Logic Gate (4-transistor) Area factor ++ 254 266 279 292 306 320 320 320 320
SRAM Cell (6-transistor) Area efficiency ++ 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63
Logic Gate (4-transistor) Area efficiency ++ 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50
SRAM Cell (6-transistor) Area ++ 0.74 0.58 0.45 0.35 0.28 0.22 0.17 0.13 0.11
SRAM Cell (6-transistor) Area w/overhead ++ 1.2 0.93 0.73 0.57 0.45 0.35 0.27 0.22 0.17
Logic Gate (4-transistor) Area ++ 2.06 1.63 1.30 1.03 0.82 0.65 0.51 0.41 0.32
Logic Gate (4-transistor) Area w/overhead ++ 4.1 3.3 2.6 2.1 1.6 1.3 1.03 0.82 0.65
Transistor density SRAM (Mtransistors/cm2) 504 646 827 1,057 1,348 1,718 2,187 2,781 3,532
Transistor density logic (Mtransistors/cm2) 97 122 154 194 245 309 389 490 617
Generation at introduction * p07c p10c p10c p10c p13c p13c p13c p16c p16c Functions per chip at introduction (million transistors [Mtransistors]) 386 386 386 773 773 773 1546 1546 1546
Chip size at introduction (mm2) ‡ 222 353 280 222 353 280 222 353 280
Cost performance MPU (Mtransistors/cm2 at
introduction) (including on-chip SRAM) ‡ 174 219 276 348 438 552 696 876 1,104
Generation at production * p04c p04c p07c p07c p07c p10c p10c p10c p13c Functions per chip at production (million transistors [Mtransistors])
193 193 386 386 386 773 773 773 1546
Chip size at production (mm2) §§ 111 88 140 111 88 140 111 88 140
Cost performance MPU (Mtransistors/cm2 at
production, including on-chip SRAM) ‡ 174 219 276 348 438 552 696 876 1,104
2005 ITRS Work in Progress – Do Not Publish
23
ORTC MPU cp Table 1h (Long Term) (Draft 04 review 10/31/05):
Table 1h MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model—Long-term Years
Year of Production 2014 2015 2016 2017 2018 2019 2020
DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (f) 28 25 22 20 18 16 14
MPU Physical Gate Length (nm) 11 10 9 8 7 6 6
SRAM Cell (6-transistor) Area factor ++ 104.1 103.4 102.8 102.2 101.7 101.3 100.9
SRAM Cell (6-transistor) Area factor ++ 104.1 103.4 102.8 102.2 101.7 101.3 100.9
Logic Gate (4-transistor) Area factor ++ 320 320 320 320 320 320 320
Logic Gate (4-transistor) Area factor ++ 320 320 320 320 320 320 320
SRAM Cell (6-transistor) Area efficiency ++ 0.63 0.63 0.63 0.63 0.63 0.63 0.63
Logic Gate (4-transistor) Area efficiency ++ 0.50 0.50 0.50 0.50 0.50 0.50 0.50
SRAM Cell (6-transistor) Area ++ 0.084 0.066 0.052 0.041 0.032 0.026 0.020
SRAM Cell (6-transistor) Area w/overhead ++ 0.13 0.106 0.083 0.066 0.052 0.041 0.032
Logic Gate (4-transistor) Area ++ 0.26 0.20 0.16 0.13 0.10 0.08 0.06
Logic Gate (4-transistor) Area w/overhead ++ 0.51 0.41 0.32 0.26 0.20 0.16 0.13
Transistor density SRAM (Mtransistors/cm2) 4,484 5,687 7,208 9,130 11,558 14,625 18,497
Transistor density logic (Mtransistors/cm2) 778 980 1,235 1,555 1,960 2,469 3,111
Generation at introduction * p16c p19c p19c p19c p22c p22c p22c
Functions per chip at introduction (million transistors [Mtransistors]) 3092 3092 3092 6184 6184 6184 12368
Chip size at introduction (mm2) ‡ 222 353 280 222 353 280 222
Cost performance MPU (Mtransistors/cm2 at introduction) (including on-
chip SRAM) ‡ 1,391 1,753 2,209 2,783 3,506 4,417 5,565
Generation at production * p13c p13c p16c p16c p16c p19c p19c
Functions per chip at production (million transistors [Mtransistors]) 1546 1546 3092 3092 3092 6184 6184
Chip size at production (mm2) §§ 111 88 140 111 88 140 111
Cost performance MPU (Mtransistors/cm2 at production, including on-
chip SRAM) ‡ 1,391 1,753 2,209 2,783 3,506 4,417 5,565
2005 ITRS Work in Progress – Do Not Publish
24
ORTC MPU hp Table 1i (Near Term) (Draft 04 review 10/31/05):
Table 1i High-Performance MPU and ASIC Product Generations and Chip Size Model—Near-term Years Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013
DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 36 32
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (f) 90 78 68 59 52 45 40 36 32
MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13 Logic (Low-volume Microprocessor) High-performance ‡
Generation at Introduction p07h p10h p10h p10h p13h p13h p13h p16h p16h Functions per chip at introduction (million transistors)
1106 2212 2212 2212 4424 4424 4424 8848 8848
Chip size at introduction (mm2) 492 781 620 492 781 620 492 781 620
Generation at production ** p04h p04h p07h p07h p07h p10h p10h p10h p13h
Functions per chip at production (million transistors)
553 553 1106 1106 1106 2212 2212 2212 4424
Chip size at production (mm2) §§ 246 195 310 246 195 310 246 195 310
High-performance MPU Mtransistors/cm2 at
introduction and production (including on-chip SRAM) ‡
225 283 357 449 566 714 899 1133 1427
ASIC
ASIC usable Mtransistors/cm2 (auto layout) 225 283 357 449 566 714 899 1,133 1,427
ASIC max chip size at production (mm2) (maximum
lithographic field size) 858 858 858 858 858 858 858 858 858
ASIC maximum functions per chip at production (Mtransistors/chip) (fit in maximum lithographic field size)
1,928 2,430 3,061 3,857 4,859 6,122 7,713 9,718 12,244
2005 ITRS Work in Progress – Do Not Publish
25
ORTC MPU hp Table 1j (Long Term) (Draft 04 review 10/31/05):
Table 1j High-Performance MPU and ASIC Product Generations and Chip Size Model—Long-term Years Year of Production 2014 2015 2016 2017 2018 2019 2020
DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (f) 28 25 22 20 18 16 14
MPU Physical Gate Length (nm) 11 10 9 8 7 6 6
Logic (Low-volume Microprocessor) High-performance ‡ Generation at Introduction p16h p19h p19h p19h p22h p22h p22h
Functions per chip at introduction (million transistors) 8848 17696 17696 17696 35391 35391 35391
Chip size at introduction (mm2) 492 781 620 492 781 620 492
Generation at production ** p13h p13h p16h p16h p16h p19h p19h
Functions per chip at production (million transistors) 4424 4424 8848 8848 8848 17696 17696
Chip size at production (mm2) §§ 246 195 310 246 195 310 246
High-performance MPU Mtransistors/cm2 at introduction
and production (including on-chip SRAM) ‡ 1798 2265 2854 3596 4531 5708 7192
ASIC ASIC usable Mtransistors/cm
2 (auto layout) 1,798 2,265 2,854 3,596 4,531 5,708 7,192
ASIC max chip size at production (mm2) (maximum
lithographic field size) 858 858 858 858 858 858 858
ASIC maximum functions per chip at production (Mtransistors/chip) (fit in maximum lithographic field size)
15,427 19,436 24,488 30,853 38,873 48,977 61,707