itrs 2001 renewal - work in progress - do not publish 1 [per irc approved proposals 3/27/01,...

ITRS 2001 Renewal - Work in Progress - Do Not Publish

1

[Per IRC Approved Proposals 3/27/01, Scenario 2.0/3.7]

ITRS IRC/ITWG Meeting

ORTC Proposal Review Grenoble - 4/25/2001

Draft Rev 10b, 04/19/01


2

MOS Transistor Scaling(1974 to present)

S=0.7[0.5x per 2 nodes]

Pitch Gate


3

Scaling Calculator

250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16

0.5x

0.7x

0.7x

N N+1

N+2


4

ITRS Approved Scenario Proposal (3/27/00 Telecon) Scenarios 2.0(DRAM), 3.7(MPU), 3.x (ASIC/Low

Power*)the DRAM Half-pitch (HP) should remain on a 3-year-cycle

trend after 130nm/2001 (Sc 2.0).

– the MPU HP may be on a 2-year-cycle trend until 90nm/2004, and then remain equal to DRAM HP Sc 2.0 on a 3-year cycle (Sc 3.7).

– the MPU (HP) Printed (PrGL) and Physical (PhGL) Gate Length will be on 2-year-cycle trends until 45nm and 32nm, respectively, at year 2005, and then parallel to the DRAM/MPU HP trends on a 3-year cycle (Sc 3.7).

– the ASIC/Low Power* HP/GL to be negotiated and added by Taiwan/Europe/Japan IRC/TWGs at Grenoble 4/26,27 ITRS meetings.

[*Note: ASIC/Low Power Half-pitch and Gate Lengths may lag “most aggressive” MPU High-Performance HPs/GLs by 1-2 years]


5

ITRS Roadmap Acceleration Continues...

1998/1999 DRAM Half-Pitch

500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

25

2000 Update, Sc 2.0

MPU/ASIC Gate “In Resist” 1999 ITRS

Technology Node (DRAM Half Pitch)

MPU/ASIC

Gate Length

Minimum

Feature Size

XX90XX65XX45XX32XX22

16

~.7x pertechnologynode (.5xper 2 nodes)

11

8.0

Scenario 2.0/DRAM 3.7/MPU

(2-yr cycle M/A HP & G.L. <2005; 3yr

>2005)

Sc 3.7 MPU Half-Pitch (1-year Lag Thru 2002, then equal to DRAM after 2004)

“Most Aggressive” Sc 3.7 = 2-yr<’05; 3-yr >’05 MPU Printed (PrGL) & Physical (PhGL) Gate Length

cycle

DRAM Sc 2.0 = 3-yr cycle after 2001

2-Year Node Cycle 1995-2001


6

2001 Renewal ORTC DRAM and MPU Technology Node Tables 1a,b [ITRS Typical Table Header Format ]

Table 1a Product Generations and Chip Size Model Technology Nodes—Near Term Years*

Year of Production 2001 2002 2003 2004 2005 2006 2007DRAM ½ Pitch (Sc. 2.0) 130 115 100 90 80 70 65MPU ½ Pitch (Sc. 3.7) 150 130 105 90 80 70 65MPU Printed Gate Length (Sc. 3.7) †† 90 75 65 53 45 40 35MPU Physical Gate Length (Sc. 3.7) 65 53 45 37 32 30 25

Table 1b Product Generations and Chip Size Model Technology Nodes—Long Term Years*

Year of Production 2010 2013 2016DRAM ½ Pitch (Sc. 2.0) 45 32 22MPU ½ Pitch (Sc. 3.7) 45 32 22MPU Printed Gate Length (Sc. 3.7) †† 25 18 13MPU Physical Gate Length (Sc. 3.7) 18 13 9

††

MPU and ASIC Gate-length (In Resist) node targets refer to most aggressive requirements, as printed in photoresist (which was by definition also “as etched in polysilicon”, in the 1999 ITRS).


7

2001 Renewal ORTC ASIC Technology Node Tables 1aa,ba [ITRS ASIC/Low Power Chapter Table Header Format ]

Table 1aa Product Generations and Chip Size Model Technology Nodes—Near Term Years*

Year of Production 2001 2002 2003 2004 2005 2006 2007DRAM ½ Pitch (Sc. 2.0) 130 115 100 90 80 70 65MPU ½ Pitch (Sc. 3.7) 150 130 105 90 80 70 65MPU Printed Gate Length (Sc. 3.7) †† 90 75 65 53 45 40 35MPU Physical Gate Length (Sc. 3.7) 65 53 45 37 32 30 25

ASIC/Low Power ½ Pitch (Sc. 3.x)ASIC/Low Power Printed Gate Length (Sc. 3.x) †† ASIC/Low Power Physical Gate Length (Sc. 3.x)

Table 1ba Product Generations and Chip Size Model Technology Nodes—Long Term Years*

Year of Production 2010 2013 2016DRAM ½ Pitch (Sc. 2.0) 45 32 22MPU ½ Pitch (Sc. 3.7) 45 32 22MPU Printed Gate Length (Sc. 3.7) †† 25 18 13MPU Physical Gate Length (Sc. 3.7) 18 13 9

ASIC/Low Power ½ Pitch (Sc. 3.x)ASIC/Low Power Printed Gate Length (Sc. 3.x) †† ASIC/Low Power Physical Gate Length (Sc. 3.x)

†† MPU and ASIC Gate-length (In Resist) node targets refer to most aggressive requirements, as printed in photoresist (which was by definition also “as etched in polysilicon”, in the 1999 ITRS).


8

DRAM Chip size - 2000 ITRS ORTC Update Proposal [Sc. 2.0]

10

100

1,000

10,000

1980 1990 2000 2010 2020

Ch

ip S

ize

(mm

2 )

@Introduction *

@Peak *

drmchrta3.xls

4 Mb

16 Mb

75mm2

38mm2

600mm2

150mm2

300mm2

1999 ITRS Period 1999-2014

256 Mb 1 Tb1 Gb 256 Gb4 Gb 16 Gb 64 Gb

* Constant-Chip-Size Targets

@ 4x bits/4-5 years:

64 Mb1 Mb

Historical Data,

Trends

Min Litho Field @5x: 22x26 = 572 mm2

Max DRAM Prod. Chip Size 11x26 = 286 mm2

(2 die/field)128G32G1G 16G4G 64G

2G

1G4G

16G

64G

8G

32G8G

2G

8x Cell Area

Factor

6x Cell Area

Factor

4x Cell Area

Factor

1999 ITRS: 2x bits/2yrs;1.2x / 4 years; no Cell Area Factor Reduction Limits

DRAM ISSCC Demo 4x bits/3 years (Historical)

Max Litho Field @4x: 800mm2

2001 ITRS Period 2001-2016

~1.1x/ / 4 years

2000 ITRS [Sc. 2.0]

~1.2x / 4 yearsProd: 2x bits/2yrs thru 32G

Intro: 2x bits/2yrs thru 8G

256M

ISSCC Demo

4G

16G

64G256G

1T

Technology Node (Dram half-pitch, nm):

180 90 45 23250 130 65 33

<-2-yrs / node-> <----------------3-yrs / node--------------->

512M

2000 Update [Sc. 2.0/3.7]

[Approved for use in 2001

Renewal w/MPU Sc.

3.7]

Samsung @ ISSCC/Feb2001: 4Gb DRAM, 645mm2, [0.15u2 ave cell area] (ITRS: 0.13u2/2001)


9

10

100

1,000

1980 1985 1990 1995 2000 2005 2010 2015 2020

MP

U C

hip

Siz

e (m

m2 )

LOGDA080a.XLS 11/00

Co. E =

Generational trendsIntragenerational trends

Co. A

Co. C

Co. B

I TRS 2000

Production

High- Performance MPU

[1.2x/4yrs (@ 2x t/chip/2yrs)]

I TRS 2000

I ntroduction ; Production

Cost- Performance MPU

[1.2x/4yrs (@ 2x t/chip/2yrs)]

P99c

P11c

Co. D

MPU Chip size - 2000 ITRS ORTC Update Proposal [ Sc. 2.0 vs 3.7 ]

572mm2 Litho Field Size

286mm2 2 per Field Size

800mm2 Litho Field Size

310mm2340mm2

170mm2

85mm2

42mm2

Sc 3.7: Flat Thru

2004


10

SRAM A-Factors for Simple 6T SRAM Cell using Microprocessor Logic CMOS Process Technology

020406080

100120140160180200

0.13micron (Intel, IEDM

2000.p.567))

0.13micron (M

otorola, IEDM2000,p.571))


1998,p.197)


1996,p.847)


1994)

0.3micron (M

otorola, IEDM1994)

A-F

ac

tor

for

SR

AM

Ce

ll S

ize

(s

qu

are

fe

atu

re s

ize

)Average A-Factor = 161.67

DRAM half-pitch (F) A-Factor (A*F2)0.13micron (Intel, IEDM2000.p.567)) 143.70.13micron (Motorola, IEDM2000,p.571)) 146.740.18micron (Intel, IEDM1998,p.197) 172.530.25micron (Intel, IEDM1996,p.847) 164.160.35micron (Intel, IEDM1994) 167.30.3micron (Motorola, IEDM1994) 175.6

‘94-’00 Historical A-factor Reduction Rate Ave =

0.967x = -3.3% CAGR [1999 ITRS

Target: -7%

CAGR**]‘98-’00

Historical A-factor

Reduction Rate Ave =

0.913x = -8.7% CAGR

** 1.2x/4yrs “affordable” MPU chip size growth; @ 2x/2yrs Transistors/chip Function Growth; @ 0.5x/3yrs Technology Node (f) Reduction

2.43 u2 2.48 u2

5.59 u2 10.3 u2 20.5 u2

15.8 u2

Cell Size (u2)


11

Chip Function Density Trend Chart - ITRS Proposal 3.7

0.001

0.01

0.1

1

10

100

1000

1980 1985 1990 1995 2000 2005 2010 2015 2020

Ave

Cel

l, Tr

ansi

stor

Are

a (s

quar

e m

icro

ns)

SRAM on-chip CellArea-Lo (member co.inputs, 6/95)

SRAM on-chip CellArea-Hi (member co.inputs, 6/95)

SRAM on-chipAVERAGE TransistorArea (u2) - ITRS2000 Update

SRAM on-chipAVERAGE Cell Area(@6t/cell) (u2) - ITRS2000 Update

SCELL050a.XLS 01/01

I TRS 2000 Update

SRAM Ave Cell Area

(@6t/cell)

I TRS 2000 Update

SRAM Ave Transistor

Area (@6t/cell)

= DRAM Ave Cell Area Trend (ITRS

2000)

0.1 (̂1/6.65yrs) =

- 29.3% CADR =

0.707x/yr

[HI STORI CAL DRAM

AVERAGE]

= (1.414x/4x)/3yrs

(2.83x/3yrs

Ave Density I ncrease)

0.1 (̂1/5yrs) =

- 47.0% CADR

= 0.63x/yr

[HI STORI CAL Accel.]

= (.82x/4x)/4yrs

(2.23x/2yrs, 3.33x/3yrs


0.1 (̂1/7.65yrs) =

- 28.0% CADR =

0.74x/yr

= (1.2x/4x)/4yrs

(2.47x/3yrs


"48G"/

.0055u2

256M/

.49u2

64M

1G

4G

16G

64G

1M

4M

16M

S

S

S

S

L

L

L

L

= ASIC Gate (4t) , eSRAM (6t) (Design TWG)

ITRS Chip Size Model Proposal:

Sc 2.0/DRAM [no

change];

Sc 3.7/MPU Proposal:

Li = MPU 4t Gate;

Ai = ASIC 4t Gate;

Si = 6t SRAM cell;

St = SRAM transistor

Li

Ai

SiSt

Ai

Ai

Ai

Ai

Ai

Ai

Ai

Ai

Li

Li

Li

Li

Li

Li

Li

Li

Si

Si

Si

Si

Si

Si

Si

Si

St

St

St

St

St

St

St

St


12

MPU Max Chip Frequency - ITRS GL Proposal Sc 3.7Lo

g F

req

uency

2023

25Ghz/4.2nm

2011

1999 ITRS

Sc 3.7 - w/Innovation* : 2x/2yrs

.6 Ghz/180nm

.3 Ghz/350nm

4.8Ghz/22nm

9.6Ghz/11nm

2.4Ghz/45nm

1999

2008

2003

2014

1997

1995

3.4Ghz/32nm

2005

1.2Ghz/90nm1.7Ghz/65nm

2001

Non-Gate-Length Performance Innovation*

Historical:

Freq = 2x/2yrs ;

GL = .71x/yr

Sc 3.7 w/o Innov.*: 1999- 2005

Freq = 2x/4yrs ;

GL = .71x/2yr

2005- 2016

Freq = 2x/6yrs ;

GL = .71x/3yr


13

ITRS Table Definitions/Guidelines - 2001 Proposal Rev0, 10/02/00 [As Presented in IRC/Taiwan 12/06/01]

• Technology Requirements Perspective- Near-Term Years : First Yr. Ref.+ 6 yrs F’cast (ex. 2001 through 2007), annually- Long-Term Years : Following 9 years (ex.: 2010, 2013, and 2016), every 3 years

• Technology Node : - General indices of technology development. - Approximately 70% of the preceding node, 50% of 2 preceding nodes. - Each step represents the creation of significant technology progress- Example: DRAM half pitches: 130, 90, 65, 45, 32, 22, 16 nm - Smallest 1/2 pitch among DRAM, ASIC, MPU, etc

• Year of Production: - The volume = 10K units (devices)/month. ASICs manufactured by same

process technology are granted as same devices- Beginning of manufacturing by a company and another company starts

production within 3 months

• Technology Requirements Color:- : Manufacturable Solutions are NOT known

- : Manufacturable Solutions are known

- : Manufacturable Solutions exist, and they are being optimized

- Red cannot exist in the next three years (2002, 2003, 2004) **- Yellow cannot exist the next year (2002) **

Red

Yellow

White

** Exception [By Review/Approval of IRC]: Solution NOT known, but does not prevent Production manufacturing


14

Backup:• DRAM Chip Size Model (Sc. 2.0)

• MPU Chip Size Model (Sc. 3.7)• Scenario Graphs

History; Sc 2.0; Sc 2.0’; Sc 3.0; Sc 4.0; Sc 3.5

• Fabless Semi Assoc. (FSA) Node Roadmap

• Backup Articles– UMC 130nm/70nm ;

– IEDM;

– EUV Consortium;

– Samsung 90nm Litho;

– Samsung 4Gb ISSCC

• Roadmap Definitions/Guidelines


15

DRAM - ORTC Chip Size Model Per IRC Technology Node Proposal Scenario 2.0 ["IS", 7/11/00; 3/27/01]:

Year 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 Technol ogy Node [ WAS, 1999] 180 130 100 70

Technol ogy Node [ I S, 3/ 27/ 01] 180 130 90 65F ( nm) [ r ounded, WAS] 180 165 150 130 120 110 100 70

F ( nm) [ r ounded, 3/ 27/ 01] 180 150 130 115 100 90 80 70 65 60F ( nm) [ act ual ****, 3/ 27/ 01] 180 151. 4 127. 3 113. 4 101. 0 90. 0 80. 2 71. 4 63. 6 56. 7

Cel l Ar ea Fact or , I S 8 8 8 8 8 8 6 6 6 6Cel l Ar ea ( um2) , I S 0. 259 0. 183 0. 130 0. 103 0. 082 0. 065 0. 039 0. 031 0. 024 0. 019DRAM @ Introduction, IS Var i abl e bi t / chi p gr owt h per schedul e bel ow**, i ncl udi ng annual i zi ng i nser t i on, as r equi r ed*Gbi t / Chi p ( var . **) 1. 07 1. 52 2. 15 3. 04 4. 29 6. 07 8. 59 11. 33 14. 96 19. 73

DRAM Pr oductCel l effi ci ency 69. 5% 70. 5% 71. 3% 71. 8% 72. 2% 72. 6% 72. 9% 73. 2% 73. 5% 73. 8%

Tot al Cel l Ar ea ( mm2) 278 278 278 312 351 394 331 347 363 381Chi p Si ze ( mm2) 400 395 390 435 485 542 454 474 494 516

Densi t y ( Gbi t s/ cm2) 0. 27 0. 38 0. 55 0. 70 0. 88 1. 12 1. 89 2. 39 3. 03 3. 82DRAM @ Production, IS Const ant bi t per / chi p gr owt h per schedul e bel ow***

Gbi t / Chi p ( const . ***) 0. 27 0. 38 0. 54 0. 76 1. 07 1. 52 2. 15 3. 04 4. 29 6. 07DRAM Pr oduct

Cel l effi ci ency 53. 0% 54. 0% 54. 8% 55. 3% 55. 7% 56. 1% 56. 4% 56. 7% 57. 0% 57. 3%Tot al Cel l Ar ea ( mm2) 70 70 70 78 88 98 83 93 104 117

Chi p Si ze ( mm2) 131 129 127 141 157 175 147 164 183 205Densi t y ( Gbi t s/ cm2) 0. 20 0. 29 0. 42 0. 54 0. 68 0. 87 1. 46 1. 85 2. 35 2. 97

Bi t / Chi p Gr owt h/ yr ( var . **) 1. 41421 For DRAM I nt r oduct i on t hr ough 8Gb and Pr oduct i on Thr ough 32Gb ( 4x/ 4year s)Bi t / Chi p Gr owt h/ yr ( var . **) 1. 31951 For DRAM I nt r oduct i on beyond 8Gb and Pr oduct i on beyond 32Gb ( 4x/ 5year s)

Gbi t / Chi p ( annual i ze*) 1. 07 1. 52 2. 15 3. 04 4. 29 6. 07 8. 59 12. 15 17. 18 24. 30DRAM Pr oduct 1G 2G 4G 8G 16G

Bi t / Chi p Gr owt h/ yr ( const . ***) 1. 41421 For I nt r oduct i on and Pr oduct i on DRAM up t o and beyond 2Gb ( 4x/ 4year s)

New Li t hogr aphy Fi el d Si ze Li mi t at i on beyond year 2005 i s 572mm2 ( 22mmX26mm) f or 5X r educt i on r et i cl e

**** "act ual " = cal cul at ed st ar t i ng f r om 180nm usi ng 0. 5 (̂ 1/ 6 yr s) Reduct i on r at e = 0. 8909/ year = 0. 7071/ 3yr s = "~0. 7x per year " I RC Defi ni t i on

Not e: = 1999 I TRS, 2000 Updat e Year Header s

= 2001 I TRS Year Header s

1G

256M 512M 1G 2G 4G

2G 4G 8G *

2009 2010 2011 2012 2013 2014 2015 201650 35

45 32 2250 35

50 45 40 35 32 30 25 2250. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5

6 6 4 4 4 4 4 40. 015 0. 012 0. 0064 0. 0051 0. 0041 0. 0032 0. 0026 0. 0020

Var i abl e bi t / chi p gr owt h per schedul e bel ow**, i ncl udi ng annual i zi ng i nser t i on, as r equi r ed*26. 04 34. 36 45. 34 59. 82 78. 94 104. 16 137. 44 181. 35

74. 0% 74. 2% 74. 3% 74. 5% 74. 6% 74. 7% 74. 8% 74. 9%399 417 291 305 320 335 351 367539 563 392 410 429 448 469 4904. 83 6. 10 11. 56 14. 60 18. 42 23. 25 29. 33 37. 00

8. 59 12. 15 17. 18 24. 30 34. 36 45. 34 59. 82 78. 94

57. 5% 57. 7% 57. 8% 58. 0% 58. 1% 58. 2% 58. 3% 58. 4%131 148 110 124 139 146 153 160229 256 191 214 239 250 262 2743. 75 4. 75 8. 99 11. 36 14. 35 18. 11 22. 86 28. 85

For DRAM I nt r oduct i on t hr ough 8Gb and Pr oduct i on Thr ough 32Gb ( 4x/ 4year s)For DRAM I nt r oduct i on beyond 8Gb and Pr oduct i on beyond 32Gb ( 4x/ 5year s)

34. 36 48. 59 68. 72 97. 18 137. 44 194. 37 274. 88 388. 7432G 64G 128G 256G

For I nt r oduct i on and Pr oduct i on DRAM up t o and beyond 2Gb ( 4x/ 4year s)


* 16G 32G 8G

128G 32G *


16

MPU ORTC Chip Size Model Per IRC Technology Node Proposal Scenario 3.7 ["IS", 3/27/01]:

Year 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 Technol ogy Node [ WAS, 1999] 180 0 0 130 0 0 100 0 0 70

Technol ogy Node [ I S, 3/ 27/ 01] 180 0 130 0 0 90 0 0 65 0F ( nm) [ r ounded, WAS] 180 165 150 130 120 110 100 0 0 70

F ( nm) [ r ounded, 3/ 27/ 01] 180 150 130 115 100 90 80 70 65 60F ( nm) [ act ual ****, 3/ 27/ 01] 180 151. 4 127. 3 113. 4 101. 0 90. 0 80. 2 71. 4 63. 6 56. 7

MPU [ r ounded] :MPU H- Pi t ch ( nm) [ WAS, 1999] 230 210 180 160 145 130 115 80

MPU H- Pi t ch ( nm) [ I S, 3/ 27/ 01] 215 180 150 130 105 90 80 70 65 60MPU Pr i nt ed G- Lengt h ( nm) [ WAS, 1999] 140 120 100 85- 90 80 70 65 45

MPU Pr i nt ed G- Lengt h ( nm) [ I S, 3/ 27/ 01] 130 105 90 75 65 53 45 40 35 32MPU Physi cal G- Lengt h ( nm) [ NEW, 3/ 27/ 01] 90 75 65 53 45 37 32 30 25 22

MPU [ act ual ****] :MPU H- Pi t ch ( nm) [ I S, 3/ 27/ 01] 214. 1 180. 0 151. 4 127. 3 107. 0 90. 0 80. 2 71. 4 63. 6 56. 7

MPU Pr i nt ed G- Lengt h ( nm) [ I S, 3/ 27/ 01] 127. 3 107. 0 90. 0 75. 7 63. 6 53. 5 45. 0 40. 1 35. 7 31. 8MPU Physi cal G- Lengt h ( nm) [ NEW, 3/ 27/ 01] 90. 0 75. 7 63. 6 53. 5 45. 0 37. 8 31. 8 28. 3 25. 3 22. 5

Densi t y Gr owt h Rat e [ ( t / cm2) / yr ] : 2x/ 2yr s 1999- 2001; t hen

[ 2x/ 2yr s/ 1. 2x/ 4yr s] 1. 414 1. 414 1. 414 1. 414 1. 414 1. 414 1. 351 1. 351 1. 351 1. 351Densi t y Gr owt h Rat e Cont r i but i on Due t o

Li t ho. Reduct i on 1. 414 1. 414 1. 414 1. 414 1. 414 1. 414 1. 260 1. 260 1. 260 1. 260Tr ansi st or Desi gn/ Pr ocess Annual

I mpr ovement Fact or Requi r ed 1. 00 1. 00 1. 00 1. 00 1. 00 1. 00 0. 93 0. 93 0. 93 0. 93SRAM Tr . Densi t y ( Mt / cm2) 71 101 143 202 286 404 546 738 998 1348Logi c Tr . Densi t y ( Mt / cm2) 5. 6 8. 0 11 16 23 32 43 58 79 106

Cost-Perf. MPU @ Introduction, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct

SRAM Mt / chi p 5. 0 7. 1 10. 0 14. 2 20. 0 28. 3 40. 0 56. 6 80. 1 113. 2Logi c Mt / chi p 18. 8 26. 6 37. 6 53. 2 75. 2 106. 3 150. 4 212. 6 300. 7 425. 3Tot al Mt / chi p 23. 8 33. 7 47. 6 67. 3 95. 2 135 190 269 381 539

SRAM Ar ea ( mm2) 7. 0 7. 0 7. 0 7. 0 7. 0 7. 0 7. 3 7. 7 8. 0 8. 4Logi c Ar ea ( mm2) 333. 0 333. 0 333. 0 333. 0 333. 0 333. 0 348. 5 364. 8 381. 8 399. 6

Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 340 340 340 340 340 340 356 372 390 408Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 7. 00 9. 90 14. 0 19. 8 28. 0 39. 6 53. 5 72. 3 97. 7 132. 0

Cost-Perf. MPU @ Production, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct

SRAM ( Level 1) Mt / chi p 2. 5 3. 5 5. 0 7. 1 10. 0 14. 2 20. 0 28. 3 40. 0 56. 6Logi c Mt / chi p 9. 4 13. 3 18. 8 26. 6 37. 6 53. 2 75. 2 106. 3 150. 4 212. 6Tot al Mt / chi p 12 17 24 34 48 67 95 135 190 269

SRAM Ar ea ( mm2) 3. 5 3. 5 3. 5 3. 5 3. 5 3. 5 3. 7 3. 8 4. 0 4. 2Logi c Ar ea ( mm2) 166. 5 166. 5 166. 5 166. 5 166. 5 166. 5 174. 3 182. 4 190. 9 199. 8

Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 170 170 170 170 170 170 178 186 195 204Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 7. 00 9. 90 14. 0 19. 8 28. 0 39. 6 53. 5 72. 3 97. 7 132. 0

High-Perf. MPU @ Production, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct

SRAM ( on- chi p Level 2) Mt / chi p 56. 6 80. 1 113. 2 160. 2 226. 5 320. 3 453. 0 640. 6 906. 0 1281Logi c ( Cor e, i ncl . L1 SRAM) Mt / chi p 11. 9 16. 8 23. 8 33. 7 47. 6 67. 3 95. 2 134. 6 190. 4 269. 3

Tot al Mt / chi p 69 97 137 194 274 388 548 775 1096 1551SRAM Ar ea ( mm2) 79. 2 79. 2 79. 2 79. 2 79. 2 79. 2 82. 9 86. 8 90. 8 95. 0Logi c Ar ea ( mm2) 170. 0 170. 0 170. 0 170. 0 170. 0 170. 0 177. 9 186. 2 194. 9 204. 0

Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 249 249 249 249 249 249 261 273 286 299Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 27. 5 38. 9 55. 0 77. 8 110. 0 155. 6 210 284 384 519

High-Perf. ASIC @ Production, ISTot al Mt / chi p 220 311 440 622 629 890 1202 1624 2195 2966

Chi p Si ze ( mm2) [ max. Li t ho Fi el d] 800 800 800 800 572 572 572 572 572 572Usabl e Tr ansi st or Densi t y ( Mt / cm2) 27. 5 38. 9 55. 0 77. 8 110. 0 155. 6 210 284 384 519

New Li t hogr aphy Fi el d Si ze Li mi t at i on beyond year 2005 i s 572mm2 ( 22mmX26mm) f or 5X r educt i on r et i cl e


Not e: = 1999 I TRS, 2000 Updat e Year Header s

= 2001 I TRS Year Header s

p05c p97c p99c

p07h p99h p01h p03h p05h

p01c p03c

p99c p01c p03c p05c p07c

2009 2010 2011 2012 2013 2014 2015 20160 0 50 0 0 35 0 00 45 0 0 32 0 0 220 0 50 0 0 35 0 050 45 40 35 32 30 25 22

50. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5

55 4050 45 40 35 32 30 25 22

30- 32 20- 2230 25 22 20 18 16 15 1320 18 16 15 13 11 10 9

50. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 528. 3 25. 3 22. 5 20. 0 17. 9 15. 9 14. 2 12. 620. 0 17. 9 15. 9 14. 2 12. 6 11. 3 10. 0 8. 9

1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351

1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260

0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 931822 2461 3326 4494 6072 8205 11086 14980144 194 263 355 479 648 875 1183

160. 2 226. 5 320. 3 453. 0 640. 6 906. 0 1281. 2 1811. 9601. 4 850. 6 1202. 9 1701. 1 2405. 8 3402. 3 4811. 6 6804. 6762 1077 1523 2154 3046 4308 6093 86178. 8 9. 2 9. 6 10. 1 10. 6 11. 0 11. 6 12. 1

418. 2 437. 7 458. 2 479. 5 501. 9 525. 3 549. 8 575. 4427 447 468 490 512 536 561 588

178. 3 241. 0 325. 6 440. 0 594. 5 803. 3 1085. 4 1466. 6

80. 1 113. 2 160. 2 226. 5 320. 3 453. 0 640. 6 906. 0300. 7 425. 3 601. 4 850. 6 1202. 9 1701. 1 2405. 8 3402. 3381 539 762 1077 1523 2154 3046 43084. 4 4. 6 4. 8 5. 0 5. 3 5. 5 5. 8 6. 0

209. 1 218. 9 229. 1 239. 8 250. 9 262. 6 274. 9 287. 7214 223 234 245 256 268 281 294

178. 3 241. 0 325. 6 440. 0 594. 5 803. 3 1085. 4 1466. 6

1812 2562 3624 5125 7248 10250 14496 20500380. 8 538. 5 761. 6 1077. 1 1523. 2 2154. 1 3046. 4 4308. 32193 3101 4385 6202 8771 12404 17542 2480899. 5 104. 1 109. 0 114. 0 119. 4 124. 9 130. 8 136. 9213. 5 223. 5 233. 9 244. 8 256. 2 268. 2 280. 7 293. 8313 328 343 359 376 393 411 431701 947 1279 1728 2335 3155 4264 5761

4007 5415 7317 9886 13358 18049 24388 32954572 572 572 572 572 572 572 572701 947 1279 1728 2335 3155 4264 5761

p07c p09c p11c

p09h

p15c

p11h p13h p15h

p13c

p09c p11c p13c


17

ITRS Roadmap Acceleration Continues...(Including MPU/ASIC “Physical Gate Length)

1994

1997

1998/1999

500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

2533

23

2000 Update, Sc 2.0


“ ”MPU/ASIC Gate “Physical” 2000 Update


XX90XX65XX45XX

XX

16

32

22

MPU/ASIC

Gate Length

Minimum

Feature Size


History, incl. 2000 Update Sc 2.0 and Node Corrections


18

(Including MPU/ASIC Physical Gate Length”) ITRS Roadmap Acceleration Continues...

“

1998/1999

500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

2533

23

2000 Update, Sc 2.0




XX90XX65XX45XX

XX

16

32

22

MPU/ASIC

Gate Length

Minimum

Feature Size

MPU/ASIC Gate “Physical” 2000 Update


Sc 2.0 (1-yr DRAM HP Node pull-in; .7x

Node Trend correction; 1-yr

PhG.L. Lead)

Samsung 01/30/01 Press Release: 90nm H.P./1G DRAM - 2002 ‘04


19


1998/1999

500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

2523

2000 Update, Sc 2.0



“ ”MPU/ASIC Gate “Physical” 2000 Update;“In Resist” Sc 2.0’

MPU/ASIC Gate “Physical” Sc 2.0’


16


MPU/ASIC

Gate Length

Minimum

Feature Size


Sc 2.0’ (PrG.L = .7 x DRAM

HP; 1-yr PhG.L. lead)


20


1998/1999

500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

25

2000 Update, Sc 2.0



MPU/ASIC

Gate Length

Minimum

Feature Size


Scenario 3.0 (2-yr G.L. Pull-in); 3-yr Node/G.L. cycle

Sc 3.0

2-yr G.L. pull-in Scenario 3.0

12/00 Press Releases: 130nm H.P./70nm G.L. - 2001 16


11


3-Year Node Cycle DRAM, M/A HP >

2001


21


1998/1999

500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

25

2000 Update, Sc 2.0



MPU/ASIC

Gate Length

Minimum

Feature Size


16


11

12/00 Press Releases: 130nm H.P./70nm G.L. - 2001

Scenario 4.0 (2-yr FSA* Node Goals), Sc 3.5 (1-yr lag M/A

HP, G.L.)

12/00 IEDM demo: 65nm H.P./32nm PrG.L. “2005 into mfg”

FSA* Feb ‘01 Presentation: “Fabless” Semiconductor / Foundry Goals for Nodes: 180nm/1999; 130nm/2001 90nm/2003; 65nm/2005

FSA* Node Goals

*FSA = “Fabless” Semiconductor Association

MPU/ASIC Half-Pitch (1-year Lag)

FSA* Feb ‘01 Presentation: “Fabless” Semiconductor / Foundry Goals for Logic H.P: 180nm/2000; 130nm/2002 90nm/2004; 65nm/2006



22



500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

25

2000 Update, Sc 2.0



MPU/ASIC

Gate Length

Minimum

Feature Size


16


11

8.0

5.5


Scenario 3.5 (1-yr Lag, 2-yr

cycle M/A HP, G.L.)


MPU/ASIC Half-Pitch (1-year Lag)

FSA* Feb ‘01 Presentation: “Fabless” Semiconductor / Foundry Goals for Logic H.P: 180nm/2000; 130nm/2002 90nm/2004; 65nm/2006

“Most Aggressive” Sc 3.5 = 2-yr; M/A H.P.;MPU Pr&Ph G.L. cycle

DRAM Sc 2.0/3.5 = 3-yr




23



500

350

250

180

130

100

70

50

35

25

Year of Production

Fe

atu

re S

ize

(n

m)

Tec

hn

olo

gy

No

de

- D

RA

M H

alf-

Pit

ch (

nm

)

95 97 99 01 04 07 10 13 162001 Renewal Period

95 97 99 01 04 07 10 13 16500

350

250

180

130

100

70

50

35

25

2000 Update, Sc 2.0



MPU/ASIC

Gate Length

Minimum

Feature Size


16


11

8.0


Scenario 2.0/DRAM 3.7/MPU

(2-yr cycle M/A HP & G.L. <2005; 3yr

>2005)

“Most Aggressive” Sc 3.7 = 2-yr<’05; 3-yr >’05 MPU H.P.; MPU PrG.L. & PhG.L. cycle

DRAM Sc 2.0/3.7 = 3-yr


MPU Half-Pitch (1-year Lag Through 2002, then equal to DRAM)

FSA* Feb ‘01 Presentation: “Fabless” Semiconductor / Foundry Goals for Logic H.P: 180nm/2000; 130nm/2002 90nm/2004; then 3-yr cycle

3-Year Node Cycle Sc 3.7 MPU HP >

2004




24

Technology Acceleration:Foundry Lead

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

19

95

19

96

19

97

19

98

19

99

20

00

20

01

20

02

20

03

20

04

20

05

SIA Roadmap

Foundry

Moving from 8 inch to 12 inch wafers gives you 125 percent more chips.

Source: “From Criticized to Respected to Preferred” Presentation, , 2/06/01 -Fabless Semiconductor Association (FSA) Website,Author: Jodi Shelton, FSA Executive Director

<<http://www.fsa.org/resources/history2.ppt>>


25


0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

19

95

19

96

19

97

19

98

19

99

20

00

20

01

20

02

20

03

20

04

20

05

SIA Roadmap

Foundry




2.0-yr cycle

continue?

2-yr cycle

1-yr cycle

3-yr cycle

2-yr cycle

1-yr cycle

‘07/65nm

ITRS Sc. 2.0:

“Fabless” Foundries:

Note: 2005

65nm Half Pitch Isol. Line =

35nm PrGL; 32nm PhGL

FSA “Node

Goals” - Sc 4.0:

2-yr cycle

continues


26


0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

19

95

19

96

19

97

19

98

19

99

20

00

20

01

20

02

20

03

20

04

20

05

SIA Roadmap

Foundry




“Logic HP LEAD”FSA Node Goals - Sc

4.0

“Actual” Logic Half-Pitch Forecast:

2002/130nm; 2006/65nm (2-yr cycle)

“Actual” Logic Half-Pitch (1-Year Lag) -

Sc 3.5


27

“UMC plans 70nm gates using phase-shifting and 248nm lithography”

Semiconductor Business News (01/18/01 15:09 p.m. PST)

“... UMC plans 70nm gates using phase-shifting and 248nm lithography

Semiconductor Business News (01/18/01 15:09 p.m. PST)

“...Plans to ramp production of 0.07µm (70-nanometer) physical gate-length transistors for processor-class products, using phase-shifting mask (PSM)

technology from Numerical Technologies with its 0.13µm logic process with existing 248nm deep UV lithography tools, starting later this year in 200mm fabs. Will use for processors with transistor switching speeds <9 picoseconds. Chose PSM route because 193nm litho tools would not be production ready for MPU-class gate lengths under 100 nm.

UMC WorldLogic 0.13µm process technologiesGate-length Application0.12µm 120nm very low leakage devices0.10µm 100nm low leakage devices0.09µm 90nm standard speed devices

0.07µm 70nm microprocessors (MPUs) ...”


28

“Chip makers under pressure to develop high-k dielectric”

- EE Times Article 12/15/00

<http://www.siliconstrategies.com/semibiznews/ OEG20001215S0001>

“...Semiconductor manufacturers may be years away from their coveted goal of developing a high-k gate dielectric that will replace silicon dioxide and meet future performance and power-consumption targets, even as SiO2 is reaching its limits, according to researchers at IEDM. Intel set the tone for the gate-oxide scaling debate - researcher Robert Chao said transistors with 30-nm[32] LG, and a gate oxide of just 8Å (0.8-nm), conceivably could be made in 2005, when the 70-nm[65] technology node moves into manufacturing….”


29

“10 gigahertz or bust”(Cnet - Feb 15, 2001)

“..Ultimately (in the 2005 time frame) we will manufacture microprocessors based on 30-nanometer [32] transistors, and EUV lithography will be a critical component of that manufacturing process. The processors that result from this will operate at around 10GHz…EUV lithography is scheduled to support IC manufacturing at the 70-nanometer [65]

technology node. This requires preproduction tools for process development in late 2003 or early 2004 and production tools in 2005…”(Cnet interview with Charles Gwyn, general manager and program director of the Extreme Ultraviolet LLC consortium)

*For more...http://news.cnet.com/news/0-1014-201-4822673-0.html


30

“Samsung targets 1-Gb DRAM production in '02 using new 193-nm resist”

( Semiconductor Business News -01/30/01)< http://www.siliconstrategies.com/story/OEG20010130S0011 >

“...Samsung said the photoresist enables mass production of 1-Gbit memories with 0.09-micron [02?] and below design rules

[‘04 per IRC, 2/26/01 telecon][Sc. 2.0 1G: ISSCC/Intro(180nm, 400mm2)/1999; Production(100nm, 157mm2)/2003]

.... The 193-nm resist is expected to enable device shrinks down to the 0.07-micron level, according to Samsung….

[Sc. 2.0: 130nm/01, 115nm/02; 100nm/03, 90nm/04; 70nm/06, 65nm/07; 50nm/09, 45nm/10; 35nm/12, 32nm/013; 25nm/15, 22nm/016]

… The company said it eventually plans to use the new compound and 193-nm scanners to produce 64-Gbit DRAMs with ArF lithography…”

[Sc. 2.0 64G: ISSCC(57nm-45nm, 1200-800mm2)/2008-10; Intro(35-32nm, 450-400mm2)/2012-13; Production(25-22nm, 300-250mm2)/2015-16]


31

“ISSCC: Samsung Reveals 4Gbit DDR SDRAM Prototype”

(Electronic News - Feb, 2001)

Samsung Electronics Co. Ltd. has busted the DRAM density barrier with a prototype DDR SDRAM chip that has four times as many transistors as anything ever made before, according to the Korea-based company. Samsung engineers have managed to squeeze more than 4 billion transistors onto a single chip, said Hongil Yoon, a senior Samsung engineer, today at the ISSCC in San Francisco. The chip uses a twisted open bitline architecture, and measures a whopping 645 square millimeters, or 1 square inch [25.4mm square, 0.150u2 ave cell area x .90 (est. cell area efficiency) = 0.135 cell area; using “0.10u design rule”* => a=15; versus ITRS 2000 Update: a=8, f=0.13u, af^2 = 0.135 in 2001].

*For more...http://www.electronicnews.com/enews/news/6222-38NewsDetail.asp


32

Rev 6 ITRS Scenario Proposal - Scenario 3.5 MPU/ASIC Half-pitch Correction

• Additional careful evaluation of the Fabless Semiconductor Association (FSA) Sc 4.0 Node goals suggests that the actual MPU/ASIC (M/A) half-pitch should lag the FSA Node goals by 1 year. This is more consistent historically [2-year lag, accelerating to a 1-year lag, crossing over in future (2005) per conclusions at the Taiwan ITRS meeting].

• Therefore, please review an attached proposal M/A Sc 3.5 table line items for a more correct proposal for the M/A half-pitch and the associated M/A Sc 3.5 Printed (PrGL) and Physical (PrGL Gate Lengths.

• For continuity, additional graphs are included to show the progression from Sc 2.0

-> Sc 2.0’ -> Sc 3.0 -> Sc 4.0(FSA Node Goals) -> M/A Sc 3.5• Also included are the FSA Node Roadmap w/ Sc 3.5 M/A half-pitch

analysis and the

• other collateral backup articles reviewed at the 2/26 (Asia) and 2/28 (Eur) IRC Teleconferences.


33

ITRS Table [2000 Update] Definitions/Guidelines,

Proposal Rev1, 7/11/00 [As Presented in 2000 Update/Taiwan 12/06/01]

• Technology Requirements Perspective- Near-Term Years : First Yr. Ref.+ 6 yrs F’cast (ex. 1999 through 2005), annually- Long-Term Years : Following 9 years (ex.: 2008, 2011, and 2014), every 3 years

• Technology Node : - General indices of technology development. - Approximately 70% of the preceding node, 50% of 2 preceding nodes. - Each step represents the creation of significant technology progress- Example: DRAM half pitches (2000 ITRS) of 180, 130, 90, 65, 45 and 33 nm*Year 2000 : Smallest 1/2 pitch among DRAM, ASIC, MPU, etc

• Year of Production: - The volume = *10K units (devices)/month. ASICs manufactured by same

process technology are granted as same devices- Beginning of manufacturing by *a company and another company starts

production within 3 months

• Technology Requirements Color :- : Manufacturable Solutions are NOT known

- : Manufacturable Solutions are known

- : Manufacturable Solutions exist, and they are being optimized

*Year 2000 : Red cannot exist in next 3 years (2000, 2001, 2002)***Year 2000 : Yellow cannot exist in next 1 year (2000)

Red

Yellow

White

** Exception: Solution NOT known, but does not prevent Production manufacturing


34

Sc 2.0/3.7: DRAM Will Continue to Lead Half-Pitch Nodes [DRAM 3-yr HP after 2001, MPU HP 2-yr-cycle through 2004, then 3-yr-cycle; MPU GL 2-yr-cycle GL through 2005;

ASIC/Lo-Power HP/GL Line Items to be developed and added at Grenoble 4/26,27/2001]

97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16

DR HP 1.5 250 180 130 100 90 70 65 50 45 35 32 25

DR HP 2.0 250 210180 150 130 115 100 90 80 70 65 60 50 45 40 35 32 30 25 22

FSA HP 4.0250 210180 150 130 105 90 75 65

M/A HP 1.5 350 180 130 100 90 70 65 50 45 35 32 25

M/A HP 2.0 350 230 160 130 100 90 70 65 50 45 35 32

M/A HP 3.0 350 280220 180 150 130 115 100 90 80 70 65 60 50 45 40 35 32 30 25

MPU HP 3.7 400 255 215 180 150 130 105 90 80 70 65 60 50 45 40 35 32 30 25 22

Sc 1.5 Pr 200 100 90 75 65 50 45 35 32 25 22 18 16

7/00 Ph 200 120 100 75 65 50 45 35 32 25 22 18 16 13

Sc 2.0 Pr 200 140 100 90 70 65 50 45 35 32 25 22 18

7/00 Ph 200 120 100 90 70 65 50 45 35 32 25 22 18 16

Sc 2.0’Pr 180 100 90 70 65 50 45 35 32 25 22 18 16

11/00 Ph 180 100 90 70 65 50 45 35 32 25 22 18 16

Sc 3.0 Pr 180 150120 100 90 75 65 60 50 45 40 35 32 30 25 22 20 18 16 15

12/00 Ph 180 135 100 90 75 65 60 50 45 40 35 32 30 25 22 20 18 16 15 13

Sc 3.7 Pr 180 150 130 105 90 75 65 53 45 40 35 32 30 25 22 20 18 16 15 13

MPU Ph 180 130 90 75 65 53 45 37 32 30 25 22 20 18 16 15 13 11 10 9.0

[Sc. 2.0/3.7]

Sc 2

.0/D

RA

M,

3.7

/MP

U A

pp

roved

3/2

7

Sc 2.0/DRAM, 3.0/MPU Approved @ 2/26 IRC Telecon; Sc 3.7 Approved by IRC Review 3/27/01

Rev 8, 3/27/01

itrs 2001 renewal - work in progress - do not publish 1 [per irc approved proposals 3/27/01,...

Documents

itrs sc

itrs meetings

itrs target

renewal work

renewal ortc dram

itrs ortc update proposal

dram hp sc

mpu proposal