19673886-slides-pech4-july05

© Ned Mohan, 2005

4- 1

Chapter 4 Designing Feedback Controllers in Switch-Mode DC Power Supplies

4-1 Objectives of Feedback Control

4-2 Review of the Linear Control Theory 4-3 Linearization of Various Transfer Function Blocks 4-4 Feedback Controller Design in Voltage-Mode Control 4-5 Peak-Current Mode Control 4-6 Feedback Controller Design in DCM

References Problems

Appendix 4A Bode Plots of Transfer Functions Appendix 4B Transfer Functions in CCM Appendix 4C Derivation of Controller Transfer Functions

© Ned Mohan, 2005

4- 2

OBJECTIVES OF FEEDBACK CONTROL

• zero steady state error

• fast response

• low overshoot

• low noise susceptibility.

Controller

inV oV

*oV

DC-DC Converter

Controller

inV oV

*oV

DC-DC Converter

Figure 4-1 Regulated dc power supply.

Controller

inV oV

*oV

DC-DC Converter

Controller

inV oV

*oV

DC-DC Converter

Figure 4-1 Regulated dc power supply.

© Ned Mohan, 2005

4- 3

The steps in designing the feedback controller:

• Linearize the system for small changes around the dc steady state operating point

• Design the feedback controller using linear control theory

• Confirm and evaluate the system response by simulations for large disturbances

© Ned Mohan, 2005

4- 4

REVIEW OF LINEAR CONTROL THEORY

( ) ( )

( ) ( )( ) ( )

o o o

c c c

v t V v t

d t D d tv t V v t

= +

= += +

−

+ ov*oV

PWM-IC

cv dControllerPulse Width Modulation

Power Stageand Load

FBk

∑−

+ ov*oV

PWM-IC


Power Stageand Load

FBk

∑

Figure 4-2 Feedback control.

−

+ ov*oV

PWM-IC


Power Stageand Load

FBk

∑−

+ ov*oV

PWM-IC


Power Stageand Load

FBk

∑

Figure 4-2 Feedback control.

−

+ ( )ov s( )cv s ( )d s

( )CG s ( )PWMG s ( )PSG s

*( ) 0ov s =

FBk

A

B

ControllerPulse-Width

Modulator

Power Stage+

Output Filter∑−

+ ( )ov s( )cv s ( )d s


*( ) 0ov s =

FBk

A

B


Modulator

Power Stage+

Output Filter∑

Figure 4-3 Small signal control system representation.

−

+ ( )ov s( )cv s ( )d s


*( ) 0ov s =

FBk

A

B


Modulator

Power Stage+

Output Filter∑−

+ ( )ov s( )cv s ( )d s


*( ) 0ov s =

FBk

A

B


Modulator

Power Stage+

Output Filter∑


Small signal representation:

© Ned Mohan, 2005

4- 5

( ) ( ) ( ) ( )L C PWM PS FBG s G s G s G s k=

Phase Margin: 0 0( 180 ) 180

c cPM L Lf fφ φ φ= − − = +

100 101 102 103 104-100

-50

0

50

Loop

Gai

n M

agni

tude

(dB

)Gain Margin

fc

100

101

102

103

104

-270

-180

-90

0

Frequency (Hz)

Loop

Gai

n P

hase

(o )

Phase Margin

cf

100 101 102 103 104-100

-50

0

50

Loop

Gai

n M

agni

tude

(dB

)Gain Margin

fc

100

101

102

103

104

-270

-180

-90

0

Frequency (Hz)

Loop

Gai

n P

hase

(o )

Phase Margin

100 101 102 103 104-100

-50

0

50

Loop

Gai

n M

agni

tude

(dB

)Gain Margin

fc

100

101

102

103

104

-270

-180

-90

0

Frequency (Hz)

Loop

Gai

n P

hase

(o )

Phase Margin

cf

Figure 4-4 Definitions of crossover frequency, gain margin and phase margin.

100 101 102 103 104-100

-50

0

50

Loop

Gai

n M

agni

tude

(dB

)Gain Margin

fc

100

101

102

103

104

-270

-180

-90

0

Frequency (Hz)

Loop

Gai

n P

hase

(o )

Phase Margin

cf

100 101 102 103 104-100

-50

0

50

Loop

Gai

n M

agni

tude

(dB

)Gain Margin

fc

100

101

102

103

104

-270

-180

-90

0

Frequency (Hz)

Loop

Gai

n P

hase

(o )

Phase Margin

100 101 102 103 104-100

-50

0

50

Loop

Gai

n M

agni

tude

(dB

)Gain Margin

fc

100

101

102

103

104

-270

-180

-90

0

Frequency (Hz)

Loop

Gai

n P

hase

(o )

Phase Margin

cf

Figure 4-4 Definitions of crossover frequency, gain margin and phase margin.

Loop Transfer Function:

© Ned Mohan, 2005

4- 6

LINEARIZATION OF VARIOUS TRANSFER FUNCTION BLOCKS

Linearizing the PWM Controller IC

( )( ) ˆc

r

v td tV

=

( )d s( )cv s 1

rV

PWM IC(c) (b)

rV( )cv t

( )q t

sdT

sT

rv0

0

1

cv

rv

( )q t

(a)

t

t

( )d s( )cv s 1

rV

PWM IC(c) (b)

rV( )cv t

( )q t

sdT

sT

rv0

0

1

cv

rv

( )q t

(a)

t

t

Figure 4-5 PWM waveforms.

( )d s( )cv s 1

rV

PWM IC(c) (b)

rV( )cv t

( )q t

sdT

sT

rv0

0

1

cv

rv

( )q t

(a)

t

t

( )d s( )cv s 1

rV

PWM IC(c) (b)

rV( )cv t

( )q t

sdT

sT

rv0

0

1

cv

rv

( )q t

(a)

t

t

Figure 4-5 PWM waveforms.

( ) 1( ) ˆ( )PWMc r

d sG sv s V

= =

( ) ( )c c cv t V v t= +

( )

( ) ( )( ) ˆ ˆc c

r rD d t

V t v td tV V

= +

© Ned Mohan, 2005

4- 7

Example 4-1 In PWM-ICs, there is usually a dc voltage offset in the ramp voltage, and instead of as shown in Fig. 4-5b, a typical Valley-to-Peak value of the ramp signal is defined. In the PWM-IC UC3824, this valley-to-peak value is 1.8 V. Calculate the linearized transfer function associated with this PWM-IC.

Solution The dc offset in the ramp signal does not change its small signal transferfunction. Hence, the peak-to-valley voltage can be treated as rV . Using Eq. 4-7

1 1( ) ˆ 1.8PWMr

G sV

= = =0.556 (4-8)

© Ned Mohan, 2005

4- 8

Linearizing the Power Stage of DC-DC Converters in CCM

( ) ( )( ) ( )

( ) ( )

( ) ( )

( ) ( )

vp vp vp

cp cp cp

vp vp vp

cp cp cp

d t D d tv t V v t

v t V v t

i t I i t

i t I i t

= += +

= +

= +

= +

( )vpi t ( )cpi t

( )vpv t ( )cpv t( )d t1

( )vpi t ( )cpi t

( )vpv t ( )cpv tD1

vpdV

cpdI

( )a ( )b

( )vpi t ( )cpi t


( )vpi t ( )cpi t

( )vpv t ( )cpv tD1

vpdV

cpdI

( )a ( )b

( )vpi t ( )cpi t


( )vpi t ( )cpi t

( )vpv t ( )cpv tD1

vpdV

cpdI

( )a ( )b

Figure 4-6 Linearizing the switching power-pole.

( )vpi t ( )cpi t


( )vpi t ( )cpi t

( )vpv t ( )cpv tD1

vpdV

cpdI

( )a ( )b

( )vpi t ( )cpi t


( )vpi t ( )cpi t

( )vpv t ( )cpv tD1

vpdV

cpdI

( )a ( )b

( )vpi t ( )cpi t


( )vpi t ( )cpi t

( )vpv t ( )cpv tD1

vpdV

cpdI

( )a ( )b

Figure 4-6 Linearizing the switching power-pole.

© Ned Mohan, 2005

4- 9Linearizing single-switch converters

1-1.1.1.1.1.1.1.1 Figure 4-7 Linearizing single-switch converters in CCM.

Li

inV

+

−ov+

−1: D

indV

LdI

vpi

vpv+

−cpv+

−

Li

ov+

−1: ( )d t

inV

+

−

ov

+

−(1 ) :1D−

odV

LdI

Li

vpv+

−cpv+

−ov+

−(1 ( )) :1d t−

(a) (b)

LiinV+

−

ov+

−

1: D

( )in od V V+

LdI

vpi

vpv+

−cpv+

−

Li

ov+

−1: ( )d t

Buck

Boost

Buck-Boost

0inv =

0inv =

0inv =

r

r

r

Li

Li

inV

+

−ov+

−ov+

−1: D

indV

LdI

vpi

vpv+

−cpv+

−

Li

ov+

−ov+

−1: ( )d t

inV

+

−

ov

+

−(1 ) :1D−

odV

LdI

Li

vpv+

−cpv+

−ov+

−ov+

−(1 ( )) :1d t−

(a) (b)

LiinV+

−

ov+

−ov+

−

1: D

( )in od V V+

LdI

vpi

vpv+

−cpv+

−

Li

ov+

−ov+

−1: ( )d t

Buck

Boost

Buck-Boost

0inv =

0inv =

0inv =

r

r

r

Li

© Ned Mohan, 2005

4- 10

2

11 1

o inv V srCrLCd s s

RC L LC

+=

+ + +

( )22

111 1 1

o in e

ee e

v V L srCsRd D rL C s s

RC L L C

+ = − −+ + +

Small signal equivalent circuit for Buck, Boost and Buck-Boost converters

(Buck)eL L=eqv

R

eL

+

−ov

+

−

1sC

reqv

R

eL

+

−ov

+

−

1sC

r

Figure 4-8 Small signal equivalent circuit for Buck, Boost and Buck-Boost converters.

eqvR

eL

+

−ov

+

−

1sC

reqv

R

eL

+

−ov

+

−

1sC

r

Figure 4-8 Small signal equivalent circuit for Buck, Boost and Buck-Boost converters.

( )22

111 1 1

o in e

ee e

v V DL srCsRd D rL C s s

RC L L C

+ = − −+ + +

2= (Boost and Buck-Boost)(1 )e

LLD−

(Boost)

(Buck)

(Buck-Boost)

© Ned Mohan, 2005

4- 11

Using Computer Simulation to Obtain the transfer function Bode Plots

Example 4-2 A Buck converter has the following parameters and is operating inCCM: 100L Hµ= , 697C Fµ= , 0.1r = Ω , 100sf kHz= , 30inV V= , and 36oP W= .

The duty-ratio D is adjusted to regulate the output voltage 12oV V= . Obtain both the

gain and the phase of the power stage ( )PSG s for the frequencies ranging from 1 Hz to

100 kHz.

Ideal Transformer

duty-ratio D

d

Ideal Transformer

duty-ratio D

d

Ideal Transformer

duty-ratio D

d

Figure 4-9 PSpice Circuit model for a Buck converter.

Ideal Transformer

duty-ratio D

d

Ideal Transformer

duty-ratio D

d

Ideal Transformer

duty-ratio D

d

Figure 4-9 PSpice Circuit model for a Buck converter.

© Ned Mohan, 2005

4- 12PSpice Modeling: C:\FirstCourse_PE_Book03\buck_conv_avg.sch

© Ned Mohan, 2005

4- 13

Frequency

1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHzP(V(V_out))

-150d

-100d

-50d

-0dDB(V(V_out))

-40

0

40

SEL>>

Simulation Results

© Ned Mohan, 2005

4- 14

.

Frequency

30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHzP(V(V_out))

-150d

-100d

-50d

0dDB(V(V_out))

-20

0

20

40

SEL>>

24.66dB

( )PS dBG s

( )PSG s∠0138−

Frequency


-150d

-100d

-50d

0dDB(V(V_out))

-20

0

20

40

SEL>>

24.66dB

( )PS dBG s

( )PSG s∠0138−

Figure 4-10 The gain and the phase of the power stage

Frequency


-150d

-100d

-50d

0dDB(V(V_out))

-20

0

20

40

SEL>>

24.66dB

( )PS dBG s

( )PSG s∠0138−

Frequency


-150d

-100d

-50d

0dDB(V(V_out))

-20

0

20

40

SEL>>

24.66dB

( )PS dBG s

( )PSG s∠0138−

Figure 4-10 The gain and the phase of the power stage

© Ned Mohan, 2005

4- 15FEEDBACK CONTROLLER DESIGN IN

VOLTAGE-MODE CONTROL

1. The crossover frequency cf of the open-loop gain is as high as possible to result

in a fast response of the closed-loop system. 2. The phase angle of the open-loop transfer function has the specified phase

margin, typically 060 at the crossover frequency so that the response in theclosed-loop system settles quickly without oscillations.

3. The phase angle of the open-loop transfer function should not drop below 0180−at frequencies below the crossover frequency.

Example 4-3 Design the feedback controller for the Buck converter described inExample 4-2. The PWM-IC is as described in Example 4-1. The output voltage-sensingnetwork in the feedback path has a gain 0.2FBk = . The steady state error is required to

be zero and the phase margin of the loop transfer function should be 060 at as high acrossover frequency as possible.

© Ned Mohan, 2005

4- 16

( )( )

2

2

1 /( )

1 /zc

c

p

phase boost

skG ss s

ω

ω−

+=

+

Figure 4-11 Bode plot of ( )CG s in Eq. 4-18.

Frequency

10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHzP(V(v_out)) -90

-100

-50

0

50

boostφ

( )C dBG s

( )CG s∠

090−

( )c

C fG s

zf cf pfFrequency


-100

-50

0

50

Frequency


-100

-50

0

50

boostφ

( )C dBG s

( )CG s∠

090−

( )c

C fG s

zf cf pf

© Ned Mohan, 2005

4- 17

Step 1: Choose the Crossover Frequency. Choose cf to be slightly beyond the L-C

resonance frequency 1/(2 )LCπ , which in this example is approximately 600 Hz.

Therefore, we will choose 1 kHzcf = . This ensures that the phase angle of the loop

remains greater than 0180− at all frequencies.

© Ned Mohan, 2005

4- 18

Step 2: Calculate the needed Phase Boost. The desired phase margin is specified as 060PMφ = .

The required phase boost boostφ at the crossover frequency is calculated as follows, noting that

PWMG and FBk produce zero phase shift:

( ) ( ) ( )c c c

L PS Cf f fG s G s G s∠ =∠ +∠ (from Eq. 4-2) (4-19)

( ) 180c

oL PMf

G s φ∠ = − + (from Eq. 4-3) (4-20)

( ) 90c

oC boostf

G s φ∠ = − + (from Fig. 4-11) (4-21)

Substituting Eqs. 4-20 and 4-21 into Eq. 4-19,

90 ( )c

oboost PM PS f

G sφ φ= − + −∠ (4-22)

In Fig. 4-10, 0( ) 138c

PS fG s∠ − , substituting which in Eq. 4-22 yields the required phase boost

108oboostφ = .

© Ned Mohan, 2005

4- 19

Step 3: Calculate the Controller Gain at the Crossover Frequency. From Eq. 4-2 at the crossover frequency cf

( ) ( ) ( ) ( ) 1c c c c

L C PWM PS FBf f f fG s G s G s G s k= × × × = (4-23)

In Fig. 4-10, at 1cf kHz= , 1

( ) 24.66 17.1c

PS f kHzG s dB

== = . Therefore in Eq. 4-23, using

the gain of the PWM block calculated in Example 4-1,

( ) ( )

( ) 0.556 17.1 0.2 1c

FBPWM PSf fc c

C fkG s G s

G s × × × = (4-24)

or ( ) 0.5263

cC f

G s = (4-25)

© Ned Mohan, 2005

4- 20

( )( )

2

2

1 /( )

1 /zc

c

p

phase boost

skG ss s

ω

ω−

+=

+

pboost

z

Kωω

= tan 454

o boostboostK φ = +

cz

boost

ffK

= p boost cf K f=

( )c

zc C f

boost

k G sKω

=

−

+ ( )ov s( )cv s ( )d s


*( ) 0ov s =

FBk

A

B


Modulator

Power Stage+

Output Filter∑−

+ ( )ov s( )cv s ( )d s


*( ) 0ov s =

FBk

A

B


Modulator

Power Stage+

Output Filter∑


−

+ ( )ov s( )cv s ( )d s


*( ) 0ov s =

FBk

A

B


Modulator

Power Stage+

Output Filter∑−

+ ( )ov s( )cv s ( )d s


*( ) 0ov s =

FBk

A

B


Modulator

Power Stage+

Output Filter∑


© Ned Mohan, 2005

4- 21Implementation of the controller by an op-amp

1R

3R 2R

2C

1C3C

*ov

ov

cv1R

3R 2R

2C

1C3C

*ov

ov

cv

Figure 4-12 Implementation of the controller by an op-amp.

1R

3R 2R

2C

1C3C

*ov

ov

cv1R

3R 2R

2C

1C3C

*ov

ov

cv

Figure 4-12 Implementation of the controller by an op-amp.

( )2 1

1 2

2 1

3 1

3 3

/( )

/ 1

1/( )/( / 1)

1/( )

z c p

p z

z

p z

p

C k R

C C

R CR R

C R

ω ω

ω ω

ωω ω

ω

=

= −

== −

=

( )( )

2

2

1 /( )

1 /zc

c

p

phase boost

skG ss s

ω

ω−

+=

+

© Ned Mohan, 2005

4- 22

In this numerical example with 1 kHzcf = , 108oboostφ = , and ( ) 0.5263

cC f

G s = , we can

calculate 3.078boostK = in Eq. 4-27. Using Eqs. 4-27 through 4-30, 324.9zf Hz= , 3078pf Hz= , and 349.1ck = . For the op-amp implementation, we will select

1 100R k= Ω . From Eq. 4-30, 2 3.0C nF= , 1 25.6C nF= , 2 19.1R k= Ω , 3 11.8R k= Ω , and 3 4.4C nF= .

© Ned Mohan, 2005

4- 23

PSpice model of the Buck converter with voltage-mode control

Figure 4-13 PSpice average model of the Buck converter with voltage-mode control.

Figure 4-14 Response to a step-change in load. Time

0s 5ms 10msV(V_out)

11.6V

11.8V

12.0V

12.2V

© Ned Mohan, 2005

4- 24PSpice Modeling: C:\FirstCourse_PE_Book03\buck_conv_avg_fb_ctrl_op.sch

© Ned Mohan, 2005

4- 25

Simulation Results

Time

0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms 5.5ms 6.0msV(V_out)

11.7V

11.8V

11.9V

12.0V

12.1V

© Ned Mohan, 2005

4- 26

PEAK-CURRENT MODE CONTROL

• Peak-Current-Mode Control, and • Average-Current-Mode Control.

Figure 4-15 Peak current mode control.

inV

ov

+

−

vpi

vpv

+

−

cpv

+

−

Li

Q S

R

Flip-flop

Slope Compensation

Controller*ovci

Clock

*Li

Comparator

+−

inV

ov

+

−

vpi

vpv

+

−

cpv

+

−

Li

Q S

R

S

R

Flip-flop

Slope Compensation

Controller*ovci

Clock

*Li

Comparator

+−

© Ned Mohan, 2005

4- 27

Figure 4-16 Peak-current-mode control with slope compensation.

Li

Clock

ci

1s

s

Tf

=

t

t

*Li

( )a

Peak Current Mode

Controller−

+ ( )ov s*( )Li s ( )Li s

( )CG s 1≈

* ( ) 0ov s =Power StageController

( )b

∑

0

slope compensation

Li

Clock

ci

1s

s

Tf

=

t

t

*Li

( )a

Peak Current Mode

Controller−

+ ( )ov s*( )Li s ( )Li s

( )CG s 1≈

* ( ) 0ov s =Power StageController

( )b

∑

0

slope compensation

© Ned Mohan, 2005

4- 28Example 4-4 In this example, we will design a peak-current-mode controller for a

Buck-Boost converter that has the following parameters and operating conditions:100 HL µ= , 697 FC µ= , 0.01r = Ω , 100 kHzsf = , 30VinV = . The output power

18WoP = in CCM and the duty-ratio D is adjusted to regulate the output voltage

12VoV = . The phase margin required for the voltage loop is 060 . Assume that in the

voltage feedback network, 1FBk = .

Figure 4-17 PSpice circuit for the Buck-Boost converter.

© Ned Mohan, 2005

4- 29

.

Figure 4-18 Bode plot of /o Lv i . Frequency

1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHzP(V(V_out)/ I(L1))

-100d

-50d

0d

SEL>>

DB(V(V_out)/I(L1))-40

-20

0

20

( )PS dBG s

deg( ) |PSG s∠

29.33dB−

090−

5cf kHz= Frequency

1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHzP(V(V_out)/ I(L1))

-100d

-50d

0d

SEL>>

DB(V(V_out)/I(L1))-40

-20

0

20

( )PS dBG s

deg( ) |PSG s∠

29.33dB−

090−

5cf kHz=

As shown in Fig. 4-18, the phase angle of the power-stage transfer function levels off atapproximately 090− at ~1kHz . The crossover frequency is chosen to be 5cf kHz= , at

which in Fig. 4-18, 0( ) 90c

PS fG s∠ − . As explained in the Appendix on the

accompanying CD, the power-stage transfer function ( ) / ( )o Lv s i s of Buck-Boost

converters contains a right-half-plane zero in CCM. The crossover frequency is chosen well below the frequency of the right-half-plane zero for reasons discussed in theAppendix.

© Ned Mohan, 2005

4- 30PSpice Modeling: C:\FirstCourse_PE_Book03\Buck-Boost_Freq_Analysis.sch

© Ned Mohan, 2005

4- 31

Simulation Results

Frequency

1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHzP(V(V_out)/I(L1))

-100d

-50d

0dDB(V(V_out)/I(L1))

-40

-20

0

20

SEL>>

© Ned Mohan, 2005

4- 32

( )( )1 /

( )1 /

zcc

p

phase boost

skG ss s

ωω

−

+=

+tan 45

2o boost

boostK φ = +

cz

boost

ffK

= p boost cf K f=

( )c

c z C fk G sω=

At the crossover frequency, as shown in Fig. 4-18, the power stage transfer function has again ( ) 29.33

cPS f

G s dB= − . Therefore, at the crossover frequency, by definition, in Fig.

4-16b

( ) ( ) 1c c

C PSf fG s G s× = (4-37)

Hence, ( ) 29.33 29.27

cC f

G s dB= = (4-38)

Using the equations above for 5cf kHz= , 060boostφ , and ( ) 29.27c

C fG s = ,

3.732boostK = in Eq. 4-32. Therefore, the parameters in the controller transfer function

of Eq. 4-31 are calculated as 1340zf Hz= , 18660pf Hz= , and 3246.4 10ck = × .

© Ned Mohan, 2005

4- 33

Figure 4-19 Implementation of controller in Eq. 4-32 by an op-amp circuit.

1R

2R

2C

1C

*ov

ov

cv

1R

2R

2C

1C

*ov

ov

cv

( )

21

1 2

2 1

30 F

/ 1 380 F

1/( ) 315

z

p c

p z

z

C pR k

C C p

R C k

ωω

ω ω

ω

= =

= − =

= = Ω

1 10R k= Ω

© Ned Mohan, 2005

4- 35

Figure 4-21 Peak current mode control: Output voltage waveform.

Time

2.50ms 2.75ms 3.00ms 3.25ms 3.50msAVGX(V(Vo),10u) V(Vo)

11.92

11.96

12.00

12.04

( )ov t

( )ov t

Time

2.50ms 2.75ms 3.00ms 3.25ms 3.50msAVGX(V(Vo),10u) V(Vo)

11.92

11.96

12.00

12.04

( )ov t

( )ov t

© Ned Mohan, 2005

4- 37

Time

1.40ms 1.45ms 1.50ms 1.55ms 1.60ms 1.65ms 1.70ms 1.75ms 1.80ms 1.85ms 1.90msV(Vo)

11.92V

11.94V

11.96V

11.98V

12.00V

12.02V

Simulation Results

© Ned Mohan, 2005

4- 40

Frequency

1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHzP(V(V_out))

-200d

-100d

0dDB(V(V_out))

-40

0

40

80

SEL>>

CCM

CCM

DCM

DCM

Simulation Results

© Ned Mohan, 2005

4- 41

APPENDIX 4A BODE PLOTS OF TRANSFER FUNCTIONS WITH POLES AND ZEROS

4A-1 A Pole in a Transfer Function 1( )1 / p

T ss ω

=+

1020 log ( )T s

0

10−

20−

0

45−

90−

pω10

pω 10 pω

10log ω

( )T s∠

1020 log ( )T s

0

10−

20−

0

45−

90−

0

45−

90−

pω10

pω 10 pω

10log ω

( )T s∠

Fig. 4A-1 Gain and phase plots of a pole.

© Ned Mohan, 2005

4- 42

4A-2 A Zero in a Transfer Function

( ) 1 / zT s s ω= +

1020 log ( )T s0

10

20

0

45

90

zω10

zω 10 zω 10log ω

( )T s∠

1020 log ( )T s0

10

20

0

45

90

zω10

zω 10 zω 10log ω

( )T s∠

Fig. 4A-2 Gain and phase plots of a zero.

© Ned Mohan, 2005

4- 43

4A-3 A Right-Hand-Plane (RHP) Zero in a Transfer Function

( ) 1z

sT sω

= −

0

45−

90−

1020 log ( )T s

0

10

20

zω10

zω 10 zω10log ω

( )T s∠

0

45−

90−

0

45−

90−

1020 log ( )T s

0

10

20

0

10

20

zω10

zω 10 zωzω10

zω 10 zω10log ω

( )T s∠

Fig. 4A-3 Gain and phase plots of a right-hand side zero.

© Ned Mohan, 2005

4- 44

4A-4 A Double Pole in a Transfer Function

21( )

1o

T sssαω

=

+ +

1 0 1 1 0 2 1 0 3 1 0 4 1 0 5- 8 0

- 6 0

- 4 0

- 2 0

0

2 0

1 0 1 1 0 2 1 0 3 1 0 4 1 0 5

- 1 8 0

- 9 0

0

0 . 0 5ζ =0 . 2 5ζ =0 . 5ζ =

0 . 8 0ζ =1 . 0 0ζ =

0 . 0 5ζ =0 . 2 5ζ =

0 . 5ζ =0 . 8 0ζ =

1 . 0 0ζ =

Fig.4A-4 Gain and phase plots of a double-pole.

19673886-slides-pech4-july05

Documents