18-bit, 2 msps, µmodule data acquisition solution data ......18-bit, 2 msps, µmodule data...

18-Bit, 2 MSPS, µModule Data Acquisition Solution

Data Sheet ADAQ4003

Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES Improved design journey

Fully differential ADC driver with selectable input range Input ranges with 5 V VREF: ±10 V, ±5 V, or ±2.5 V

Essential passive components included ±0.005% iPassives matched resistor array

Wide input common-mode voltage range High common-mode rejection ratio Single-ended to differential conversion

Increased signal chain density Small, 7 mm × 7 mm, 0.80 mm pitch, 49-ball CSP_BGA

4× footprint reduction vs. discrete solution On-board reference buffer with VCM generation

High performance Throughput: 2 MSPS, no pipeline delay Guaranteed 18-bit no missing codes INL: ±3 ppm typical, ±8 ppm guaranteed SINAD: 99 dB typical (G = 0.454) Offset error drift: 0.7 ppm/°C typical (G = 0.454) Gain error drift: ±0.5 ppm/°C typical

Low total power dissipation: 51.6 mW typical at 2 MSPS Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible

Versatile logic interface supply with 1.8 V, 2.5 V, 3 V, or 5 V

APPLICATIONS Automatic test equipment Machine automation Process controls Medical instrumentation Digital control loops

FUNCTIONAL BLOCK DIAGRAM

0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF

VS–VCMO MODE GND ADCIN+ ADCIN–

VDDREF_OUTREFVS+

PD_AMP

2.2µF

VIO

SDISCKSDOCNV

OUT+

PD_REF

R1K–R1K1–

IN–

IN+R1K1+

R1K+

OUT–

1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

ADCFDA

ADAQ4003

2165

7-00

1

Figure 1.

GENERAL DESCRIPTION The ADAQ4003 is a µModule® precision data acquisition (DAQ), signal chain solution that reduces the development cycle of a precision measurement system by transferring the signal chain design challenge of component selection, optimization, and layout from the designer to the device.

Using system-in-package (SIP) technology, the ADAQ4003 reduces end system component count by combining multiple common signal processing and conditioning blocks into a single device. These blocks include a high resolution 18-bit, 2 MSPS successive approximation register (SAR), analog-to-digital converter (ADC), a low noise, fully differential ADC driver amplifier (FDA), and a stable reference buffer.

Using Analog Devices, Inc., iPassives® technology, the ADAQ4003 also incorporates crucial passive components with superior matching and drift characteristics to minimize temperature dependent error sources and to offer optimized performance (see Figure 1). Housing this signal chain solution in a small, 7 mm × 7 mm, 0.80 mm pitch, 49-ball CSP_BGA enables compact form factor designs without sacrificing performance and simplifies end system bill of materials management. This level of system integration makes the ADAQ4003 much less sensitive to printed circuit board (PCB) layout while still providing flexibility to adapt to a wide range of signal levels.

The serial peripheral interface (SPI)-compatible, serial user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using a separate VIO supply. Specified operation of ADAQ4003 is from −40°C to +125°C.

Table 1. µModule Data Acquisition Solutions Type 500 kSPS ≥1000 kSPS 16-Bit ADAQ7988 ADAQ7980 18-Bit ADAQ4003

https://form.analog.com/Form_Pages/feedback/documentfeedback.aspx?doc=ADAQ4003.pdf&product=ADAQ4003&rev=0http://www.analog.com/en/content/technical_support_page/fca.htmlhttp://www.analog.com/http://www.analog.com/adaq4003https://www.analog.com/ADAQ7988?doc=ADAQ4003.pdfhttps://www.analog.com/ADAQ7980?doc=ADAQ4003.pdfhttps://www.analog.com/adaq4003?doc=ADAQ4003.pdfhttps://www.analog.com/?doc=ADAQ4003.pdfhttps://www.analog.com/ADAQ4003?doc=ADAQ4003.pdf

ADAQ4003 Data Sheet

Rev. 0 | Page 2 of 35

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ...................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications .................................................................................... 3

Timing Specifications .................................................................. 6 Absolute Maximum Ratings ........................................................... 8

Thermal Resistance ...................................................................... 8 Electrostatic Discharge (ESD) Ratings ...................................... 8 ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions ............................ 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18

Circuit Information ................................................................... 18 Transfer Functions ..................................................................... 18

Applications Information .............................................................. 19 Typical Application Diagrams.................................................. 19

Analog Inputs ............................................................................. 21 Ease of Drive Features ............................................................... 21 Voltage Reference Input ............................................................ 23 Power Supply (Power Tree) ...................................................... 23 Digital Interface .......................................................................... 23 Register Read and Write Functionality ................................... 24 Status Word ................................................................................ 26 CS Mode, 3-Wire Turbo Mode ................................................ 27

CS Mode, 3-Wire Without Busy Indicator............................. 28

CS Mode, 3-Wire with Busy Indicator .................................... 29

CS Mode, 4-Wire Turbo Mode ................................................ 30

CS Mode, 4-Wire Without Busy Indicator............................. 31

CS Mode, 4-Wire with Busy Indicator .................................... 32

Daisy-Chain Mode ..................................................................... 33 Layout Guidelines ...................................................................... 34

Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35

REVISION HISTORY 9/2020—Revision 0: Initial Version

https://www.analog.com/ADAQ4003?doc=ADAQ4003.pdf

Data Sheet ADAQ4003


SPECIFICATIONS VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.7 V to 5.5 V, reference voltage (VREF) = 5 V, sampling frequency (fS) = 2 MSPS, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled, unless otherwise noted. ADC driver configured in single-ended to differential configuration and fast mode, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 18 Bit ANALOG INPUTS IN+, IN−, R1K1+, R1K1−, R1K+, and R1K−

Input Impedance (ZIN) Single-ended to differential configuration G = 0.454, input voltage (VIN) = 22 V p-p 1.3 kΩ G = 0.909, VIN = 11 V p-p 1.44 kΩ G = 1, VIN = 10 V p-p 1.33 kΩ G = 1.9, VIN = 5.2 V p-p 778 Ω Fully differential configuration G = 0.454 and G = 0.909,

VIN = 22 V p-p and 11 V p-p 1.1 kΩ

G = 1, VIN = 10 V p-p 1 kΩ G = 1.9, VIN = 5.2 V p-p 523 Ω Differential Input Voltage Ranges1 G = 0.454, VIN = 22 V p-p −2.2 × VREF +2.2 × VREF V G = 0.909, VIN = 11 V p-p −1.1 × VREF +1.1 × VREF V G = 1, VIN = 10 V p-p −VREF +VREF V G = 1.9, VIN = 5.2 V p-p −0.526 × VREF +0.526 × VREF V Input Capacitance IN+ and IN− 12 pF

THROUGHPUT Complete Cycle 500 ns Conversion Time 290 320 ns Acquisition Phase2 290 ns Throughput Rate3 0 2 MSPS Transient Response4 40 μs

DC ACCURACY Single-ended to differential configuration No Missing Codes 18 Bits Integral Linearity Error (INL) All gains, VS− = −1 V −8 ±3 +8 ppm −2.1 ±0.8 +2.1 LSB5 Differential Linearity Error (DNL) All gains, VS− = −1 V −1 ±0.4 +1 LSB5 −3.8 ±2.66 +3.8 ppm Transition Noise All gains 0.93 LSB Gain Error All gains −0.05 ±0.005 +0.05 %FS Gain Error Drift All gains −3 ±0.5 +3 ppm/°C Offset Error G = 0.454 −1 ±0.1 +1 mV G = 0.909, G = 1 −0.9 ±0.06 +0.9 mV G = 1.9 −1.5 ±0.01 +1.5 mV Offset Error Drift G = 0.454 −8 +0.7 +8 ppm/°C G = 0.909 and G = 1 −10 +1.6 +10 ppm/°C G = 1.9 −15 +2.6 +15 ppm/°C Common-Mode Rejection Ratio (CMRR) Fully differential configuration, all gains 90 dB Power Supply Rejection Ratio (PSRR)

Positive VDD = 1.71 V to 1.89 V 72 dB VS+ = 5.225 V to 5.775 V, VS− = 0 V 110 dB Negative VS+ = +5.5 V, VS− = 0 V to −0.5 V 107 dB

1/f Noise6 Bandwidth = 0.1 Hz to 10 Hz 38 μV p-p Input Current Noise Input frequency (fIN) = 100 kHz 1 pA/√Hz


ADAQ4003 Data Sheet


Parameter Test Conditions/Comments Min Typ Max Unit AC ACCURACY Single-ended to differential and fully

differential configuration

Dynamic Range All gains, −60 dBFS 94.5 dB G = 0.454 100 dB G = 0.909 and G = 1 97.5 dB G = 1.9 98.5 dB Oversampled Dynamic Range Oversampling ratio (OSR) = 2, all gains 103 dB OSR = 256, all gains 122 dB Total RMS Noise All gains 35.35 µV rms Signal-to-Noise Ratio (SNR) fIN = 1 kHz, −0.5 dBFS 94.2 dB G = 0.454 99.5 dB G = 0.909 and G =1 97 dB G = 1.9 98 dB fIN = 100 kHz, G = 0.909 98 dB fIN = 400 kHz, G = 0.909 92 dB Low power mode enabled, G = 0.909 96 dB VS+ = 3.3 V, VS− = 0 V,

VREF = 2.5 V, G = 0.909 92 dB

Signal-to-Noise + Distortion (SINAD) fIN = 1 kHz, −0.5 dBFS 94 dB G = 0.454 99 dB G = 0.909 and G =1 96.5 dB G = 1.9 97.5 dB fIN = 100 kHz, G = 0.909 97.5 dB fIN = 400 kHz, G = 0.909 91.5 dB Low power mode enabled, G = 0.909 95.5 dB VS+ = 3.3 V, VS− = 0 V,

VREF = 2.5 V, G = 0.909 91.5 dB

Total Harmonic Distortion (THD) fIN = 1 kHz, −0.5 dBFS, all gains −120 dB fIN = 100 kHz, G = 0.909 −100 dB fIN = 400 kHz, G = 0.909 −95 dB Low power mode enabled, G = 0.909 −110 dB VS+ = 3.3 V, VS− = 0 V,

VREF = 2.5 V, G = 0.909 −118 dB

Spurious-Free Dynamic Range (SFDR) fIN = 1 kHz, −0.5 dBFS, all gains 122 dB fIN = 100 kHz, G = 0.909 101 dB fIN = 400 kHz, G = 0.909 95 dB Low power mode enabled, G = 0.909 110 dB VS+ = 3.3 V, VS− = 0 V,

VREF = 2.5 V, G = 0.909 118 dB

−3 dB Input Bandwidth 4.4 MHz Recovery Time

Input Overdrive All gains 280 ns Output Overdrive All gains 120 ns Clamp All gains 100 ns

Aperture Delay 1 ns Aperture Jitter 1 ps rms

REFERENCE VREF Range Buffer enabled 2.4 5.1 or VS+ − 0.08 V Input Current (IREF) Buffer enabled 60 µA REF_OUT Current (IREF_OUT) Buffer disabled, 2 MSPS, VREF = 5 V 1.27 mA


Data Sheet ADAQ4003


Parameter Test Conditions/Comments Min Typ Max Unit VCMO

VCMO Voltage (VVCMO)7 VREF/2 − 0.003 VREF/2 VREF/2 + 0.003 V Output Impedance 5 kΩ

DIGITAL INPUTS SDI, SCK, and CNV Logic Levels

Input Low Voltage (VIL) VIO > 2.7 V −0.3 +0.3 × VIO V VIO ≤ 2.7 V −0.3 +0.2 × VIO V Input High Voltage (VIH) VIO > 2.7 V 0.7 × VIO VIO + 0.3 V VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V Input Low Current (IIL) −1 +1 µA Input High Current (IIH) −1 +1 µA

Input Pin Capacitance 6 pF DIGITAL OUTPUTS8

Data Format Twos complement Output Low Voltage (VOL) Sink current (ISINK) = +500 µA 0.4 V Output High Voltage (VOH) Source current (ISOURCE) = −500 µA VIO − 0.3 V

POWER-DOWN AND MODE SIGNALING ADC Driver and Reference Buffer

PD_AMP, PD_REF, and MODE Voltage

Low Powered down, low power mode 1.7 V

POWER REQUIREMENTS VDD 1.71 1.8 1.89 V VS+ 3 5.5 VS− + 10 V VS− VS+ − 10 0 0.1 V VIO 1.7 5.5 V Total Standby Current9, 10 Static, all devices enabled 11 14 mA Power-Down Current ADC driver, reference buffer disabled 100 250 nA Power Dissipation VDD = VIO = 1.8 V, VS+ = 5.5 V, VS− = 0 V

VS+ 41.5 51.5 mW VDD 9.5 12 mW VIO 0.6 0.7 mW Total 51.6 64.2 mW

VDD = VIO = 1.8 V, VS+ = 5 V, VS− = 0 V, high-Z mode enabled

VS+ 44 53 mW VDD 12.8 16.5 mW VIO 0.6 0.7 mW Total 57.4 70.2 mW

TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +125 °C

1 VIN must be within the allowed input common-mode range as per Figure 35, Figure 36, and Figure 37 and is dependent on the VS+ and VS− supply rails used. 2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 5 for the maximum achievable

throughput for different modes of operation. 4 Transient response is the time required for the ADAQ4003 to acquire a full-scale input step to ±1 LSB accuracy. 5 The weight of the LSB, referred to input, changes depending on the input voltage range. See Table 10 for the LSB size. 6 See the 1/f noise plot in Figure 28. 7 The VCMO voltage can be used for other circuitry, but it should be driven with a buffer to ensure the VCMO voltage remains stable as per the specified range. 8 There is no pipeline delay. Conversion results are available immediately after a conversion is completed. 9 With all digital inputs forced to VIO or GND as required. 10 The total standby current during the acquisition phase.


ADAQ4003 Data Sheet


TIMING SPECIFICATIONS VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.71 V to 5.5V, VREF = 5 V, fS = 2 MSPS, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled, unless otherwise noted.

Table 3. Digital Interface Timing Parameter Symbol Min Typ Max Unit Conversion Time—CNV Rising Edge to Data Available tCONV 290 320 ns Acquisition Phase1 tACQ 290 ns Time Between Conversions tCYC 500 ns CNV Pulse Width (CS Mode)2 tCNVH 10 ns

SCK Period (CS Mode)3 tSCK

VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns

SCK Period (Daisy-Chain Mode)4 tSCK VIO > 2.7 V 20 ns VIO > 1.7 V 25 ns

SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns SCK Falling Edge to Data Remains Valid Delay tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO

VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns

CNV or SDI Low to SDO D17 MSB Valid Delay (CS Mode) tEN

VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns

CNV Rising Edge to First SCK Rising Edge Delay tQUIET1 190 ns Last SCK Falling Edge to CNV Rising Edge Delay tQUIET2 60 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns

SDI Valid Setup Time from CNV Rising Edge tSSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns

SCK Valid Hold Time from CNV Rising Edge (Daisy-Chain Mode) tHSCKCNV 12 ns SDI Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode) tHSDISCK 2 ns 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. 4 A 50% duty cycle is assumed for SCK.


Data Sheet ADAQ4003


Table 4. Register Read and Write Timing Parameter Symbol Min Typ Max Unit READ AND WRITE OPERATION

CNV Pulse Width1 tCNVH 10 ns SCK Period tSCK

VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns

SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns

READ OPERATION CNV Low to SDO D17 MSB Valid Delay tEN

VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns

SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO

VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns

CNV Rising Edge to SDO High Impedance tDIS 20 ns WRITE OPERATION

SDI Valid Setup Time from SCK Rising Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns

1 For turbo mode, tCNVH must match the tQUIET1 minimum.

X% VIO1Y% VIO1

VIH2VIL2VIL2

VIH2

tDELAY tDELAY

1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 2. 21

657-

002

Figure 2. Voltage Levels for Timing

Table 5. Achievable Throughput for Different Modes of Operation Parameter Test Conditions/Comments Min Typ Max Unit

THROUGHPUT, CS MODE

3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 2 MSPS 3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.78 MSPS 3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.75 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.62 MSPS 3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.59 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.44 MSPS


ADAQ4003 Data Sheet


ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Analog Inputs

R1K+, R1K−, R1K1+, R1K1− to GND1 −16 V to +16 V2 or ±18 mA2

Supply Voltage REF_OUT and VIO to GND −0.3 V to +6.0 V VDD to GND −0.3 V to +2.1 V VDD to VIO −6 V to +2.4 V VS+ to VS− 11 V VS+ to GND −0.3 V to +11 V VS− to GND −11 V to +0.3 V

Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Temperature

Storage Range −65°C to +150°C Junction 150°C Lead Soldering 260°C reflow as per

JEDEC J-STD-020

1 See the Analog Inputs section. 2 The iPassives resistors can sustain specified maximum voltage and current

indefinitely.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL RESISTANCE Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required.

θJA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure, and θJC is the junction to case thermal resistance.

Table 7. Thermal Resistance Package Type1 θJA θJC Unit JEDEC Board Layers BC-49-5 53.5 54.9 °C/W 2S2P

1 Test Condition 1: thermal impedance simulated values are based upon use of a 2S2P JEDEC standard PCB configuration per JEDEC Standard JESD51-7.

ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only.

Human body model (HBM) per ANSI/ESDA/JEDDEC JS-001.

Field induced charged device model (FICDM) per ANSI/ ESDA/JEDEC JS-002.

ESD Ratings for the ADAQ4003

Table 8. ADAQ4003, 49-Ball CSP_BGA ESD Model Withstand Threshold (V) Class HBM 4000 2 FICDM 1000 C4

ESD CAUTION


Data Sheet ADAQ4003


PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A

B

C

D

E

F

A1 BALLCORNER

G

76321 54

2165

7-00

3

Figure 3. Ball Configuration, Top View

A

B

C

D

E

F

G

GND

R1K−

R1K1−

IN−

R1K1+

R1K+

GND

VDD

R1K−

R1K1−

IN+

R1K1+

R1K+

VCMO

OUT+

OUT+

VS–

DNC

MODE

OUT–

OUT−

VS–

VS–

VS–

DNC

VS+

VS+

VS+

REF_OUT

GND

DNC

DNC

ADCIN+

DNC

VS+

REF

VIO

GND

DNC

ADCIN−

GND

1 2 3 4 5 6 7

VIO

SDI

SCK

SDO

CNV

GND

2165

7-00

4

PD_AMP

PD_REF

Figure 4. Ball Configuration

Table 9. Ball Function Descriptions Ball No. Mnemonic Type1 Description A1, A7, B5, E6, G1, G7 GND P Power Supply Ground. A2 VDD P 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. A3, B3 OUT+ AO Positive Output of the Fully Differential ADC Driver. A4, B4, C3, C4 VS− P Negative Supply of the Fully Differential ADC Driver. A5 REF_OUT AO Reference Buffer Output Voltage. A6 REF AI Reference Buffer Input Voltage. B1, B2 R1K− AI 1 kΩ Resistor Input to Negative Input of the Fully Differential ADC Driver. B6, B7 VIO P Input and Output Interface Digital Power. Nominally, the VIO pins are at the same supply as

the host interface (1.8 V, 2.5 V, 3 V, or 5 V). C1, C2 R1K1− AI 1.1 kΩ Resistor Input to Negative Input of the Fully Differential ADC Driver. C5, D3 to D5, F5, F6 DNC N/A Do Not Connect. Do not connect to this pin. C6 PD_AMP DI Power-Down Amplifier. Active low. Connect the PD_AMP pin to GND to power down the

fully differential ADC driver. Otherwise, connect the PD_AMP pin to logic high.

C7 SDI DI Serial Data Input. This input provides multiple features. SDI selects the interface mode of the ADC as follows:

Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of SCK.


ADAQ4003 Data Sheet


Ball No. Mnemonic Type1 Description D1 IN− AI Negative Input of the Fully Differential ADC Driver. D2 IN+ AI Positive Input of the Fully Differential ADC Driver. D6 PD_REF DI Power-Down Reference Buffer. Active low. Connect the PD_REF pin to GND to power down

the reference buffer. Otherwise, connect the PD_REF pin to logic high.

D7 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.

E1, E2 R1K1+ AI 1.1 kΩ Resistor Input to Positive Input of the Fully Differential ADC Driver. E3 MODE DI Power Mode for the Fully Differential ADC Driver. Full performance when the MODE pin is

high, and low power mode when the MODE pin is low. E4, F4, G4, G5 VS+ P Fully Differential ADC Driver and Reference Buffer Positive Supply. E5 ADCIN+ AO Positive Input to the ADC. Extra capacitance can be added on the ADCIN+ pin to reduce the

RC filter bandwidth. E7 SDO DO Serial Data Output. The conversion result is output on the SDO pin. SDO synchronizes to SCK. F1, F2 R1K+ AI 1 kΩ Resistor Input to Positive Input of the Fully Differential ADC Driver. F3, G3 OUT− AO Negative Output of the Fully Differential ADC Driver. F7 CNV DI Convert Input. This input has multiple functions. On its leading edge, CNV initiates the

conversions and selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high.

G2 VCMO AO Fully Differential ADC Driver Output Common-Mode Voltage. Nominally, VREF/2. G6 ADCIN− AO Negative Input to the ADC. Extra capacitance can be added on the ADCIN− pin to reduce

the RC filter bandwidth. 1 P is power, AO is analog output, AI is analog input, N/A is not applicable, DI is digital input, and DO is digital output.


Data Sheet ADAQ4003


TYPICAL PERFORMANCE CHARACTERISTICS VS+ = 5.5 V, VS− = 0 V, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, TA = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 2 MSPS, unless otherwise noted.

CODE

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

INL

(LSB

)

0 32768 65536 98304 131072 163840 196608 229376 262144

–40°C+25°C125°C

2165

7-10

5

Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V, G = 0.454

–300

–250

–200

–150

–100

–50

0

–40

–20

0

20

40

60

80

100

120

140

160

PHAS

E (D

egre

es)

OPE

N-LO

OP

GAI

N (d

B)

FREQUENCY (Hz) 2165

7-00

7

1 10 100 1k 10k 100k 1M 10M 100M 1G

Figure 6. ADC Driver Open-Loop Gain and Phase vs. Frequency

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

TRAN

SITI

ON

NOIS

E(L

SB)

TEMPERATURE (°C)

G = 0.454, VREF = 5VG = 0.454, VREF = 2.5VG = 0.909, VREF = 5VG = 0.909, VREF = 2.5VG = 1, VREF = 5VG = 1, VREF = 2.5VG = 1.9, VREF = 5VG = 1.9, VREF = 2.5V

2165

7-11

0

–40 –20 0 20 40 60 80 100 120

Figure 7. Transition Noise vs. Temperature for G = 0.454, G = 0.909, G = 1, and

G = 1.9 and VREF = 5 V and VREF = 2.5 V

0.5

0.4

–0.4

0.3

–0.3

0.1

–0.1

0.2

–0.2

0

–0.5

DNL

(LSB

)

0 32768 65536 98304 131072CODE

163840 196608 229376 262144

–40°C+25°C+125°C

2165

7-10

8

Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V, G = 0.454

0

50000

100000

150000

200000

250000

300000

350000

400000

–23 –21 –19 –17 –15 –13 –11 –9 –7 –5 –3

COUN

TS

CODES

VREF = 5VVREF = 2.5V

2165

7-00

5

Figure 9. Histogram of a DC Input at the Code Center, VREF = 2.5 V and VREF = 5 V

–23 –21 –19 –17 –15 –13 –11 –9 –7 –5 –30

50000

100000

150000

200000

250000

300000

350000

400000

COUN

TS

CODES

VREF = 5VVREF = 2.5V

2165

7-00

6

Figure 10. Histogram of a DC Input at the Code Transition, VREF = 2.5 V and

VREF = 5 V


ADAQ4003 Data Sheet


–180

–160

–140

–120

–100

–80

–60

–40

–20

0

100 1k 10kFREQUENCY (Hz)

AMPL

ITUD

E (d

B)

100k 1M

VREF = 5VSNR = 98.2dBTHD = –123.1dBSINAD = 98.1dB

2165

7-11

2

Figure 11. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT),

Wide View, G = 1,VREF = 5 V, Differential

–180

–160

–140

–120

–100

–80

–60

–40

–20

0


AMPL

ITUD

E (d

B)

100k 1M


2165

7-11

3

Figure 12. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1,

VREF = 5 V, Single-Ended

–180

–160

–140

–120

–100

–80

–60

–40

–20

0


AMPL

ITUD

E (d

B)

100k 1M

VREF = 2.5VSNR = 93.3dBTHD = –117.8dBSINAD = 93.1dB

2165

7-11

5

Figure 13. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, VREF = 2.5 V,

Differential

FREQUENCY (Hz)

AMPL

ITUD

E (d

B)

100 1k 10k 100k 1M–180

–160

–140

–120

–100

–80

–60

–40

–20

0VREF = 2.5VSNR = 93.1dBTHD = –112.1dBSINAD = 92.9dB

2165

7-11

6

Figure 14. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1,

VREF = 2.5 V, Single-Ended

–180

–160

–140

–120

–100

–80

–60

–40

–20

0


AMPL

ITUD

E (d

B)

100k 1M

2165

7-11

7

VREF = 5VSNR = 97.5dBTHD = –117.9dBSINAD= 97.4dB

Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, Differential,

G = 0.909, VREF = 5 V, Low Power Mode

–180

–160

–140

–120

–100

–80

–60

–40

–20

0


AMPL

ITUD

E (d

B)

100k 1M


2165

7-11

8

Figure 16. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, VREF = 5 V


Data Sheet ADAQ4003


–180

–160

–140

–120

–100

–80

–60

–40

–20

0


AMPL

ITUD

E (d

B)

100k 1M

VREF = 2.5VSNR = 92.4dBTHD = –113.7dBSINAD = 92.2dB

2165

7-12

0

Figure 17. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, Differential,

G = 0.909, VREF = 2.5 V, Low Power Mode

14.95

15.15

15.35

15.55

15.75

15.95

16.15

92

93

94

95

96

97

98

99

2.5 3.0 3.5 4.0 4.5 5.0

ENO

B (B

its)

SNR,

SIN

AD (d

B)

REFERENCE VOLTAGE (V)

G = 0.909 SNRG = 0.909 SINADG = 0.909 ENOBG = 1.9 SNRG = 1.9 SINADG = 1.9 ENOB

G = 0.454 SNRG = 0.454 SINADG = 0.454 ENOB

2165

7-03

9

Figure 18. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Reference Voltage for G = 0.454, G = 0.909, and G = 1.9, fIN = 1 kHz

15.80

15.85

15.90

15.95

16.00

16.05

16.10

16.15

97.0

97.2

97.4

97.6

97.8

98.0

98.2

98.4

98.6

98.8

99.0

–40 –20 0 20 40 60 80 100 120

ENO

B (B

its)

SNR,

SIN

AD (d

B)

TEMPERATURE (°C)




2165

7-04

0

Figure 19. SNR, SINAD, and ENOB vs. Temperature,

G =1.9, G = 0.909, and G = 0.454, fIN = 1 kHz

0

–20

–40

–60

–80

–100

–120

–140

–160

–180100 1k 10k 100k 1M

AMPL

ITUD

E (d

B)

FREQUENCY (Hz) 2165

7-15

0


Figure 20. 400 kHz, −0.5 dBFS Input Tone FFT, G = 1, Wide View, VREF = 5 V

84

86

88

90

92

94

96

98

100

ENO

B (B

its)

SNR,

SIN

AD (d

B)

FREQUENCY (Hz)1k 1M100k10k

16.5

16.0

15.5

15.0

14.5

14.0

13.5

G = 1.9 SNRG = 1.9 SINAD

G = 0.909 SNRG = 0.909 SINAD

G = 1.9 ENOB

G = 0.909 ENOB

2165

7-12

3

Figure 21. SNR, SINAD, and ENOB vs. Frequency for G = 1.9 and G = 0.909,

VREF = 5 V

–126

–124

–122

–120

–118

–116

–114

–112

2.5 3.0 3.5 4.0 4.5 5.0

THD

(dB)


G = 0.454G = 0.909G = 1.9

2165

7-04

3

Figure 22. THD vs. Reference Voltage, G = 0.454, G = 0.909, and G = 1.9,

fIN = 1 kHz


ADAQ4003 Data Sheet


–126

–124

–122

–120

–118

–116

–114

–112

–40 –20 0 20 40 60 80 100 120

THD

(dB)

TEMPERATURE (°C)

G = 0.454G = 0.909G = 1.9

2165

7-04

1

Figure 23. THD vs. Temperature for G = 0.454, G = 0.909, and G = 1.9,

fIN = 1 kHz

85

90

95

100

105

110

115

120

125

130

–130

–125

–120

–115

–110

–105

–100

–95

–90

–85

SFDR

(dB)

THD

(dB)

FREQUENCY (Hz)

G = 1.9 THDG = 0.909 THD

G = 0.909 SFDRG = 1.9 SFDR

2165

7-12

6

1k 10k 100k 1M

Figure 24. THD and SFDR vs. Frequency for G = 0.909 and G = 1.9, VREF = 5 V

114

116

118

120

122

124

126

2.5 3.0 3.5 4.0 4.5 5.0

SFDR

(dB)


G = 0.454G = 0.909G = 1.9

2165

7-04

4

Figure 25. SFDR vs. Reference Voltage for G = 0.454, G = 0.909, and G = 1.9,

fIN = 1 kHz

114

116

118

120

122

124

126

–40 –20 0 20 40 60 80 100 120

SFDR

(dB)

TEMPERATURE (°C)

G = 0.454G = 0.909G = 1.9

2165

7-04

5

Figure 26. SFDR vs. Temperature for G = 0.454, G = 0.909, and G = 1.9, fIN = 1kHz

OFF

SET

ERRO

R (m

V)

TEMPERATURE (°C)

G = 0.454G = 0.909G = 1G = 1.9

2165

7-13

0

0.25

0.20

0.15

0.10

0.05

–0.05

–0.15

–0.10

–0.20

–20 0 20 40 60 80 100 120–40–0.25

0

Figure 27. Offset Error vs. Temperature for G = 0.454, G = 0.909, G = 1, and

G = 1.9

0 1 2 3 4 5 6 7 8 9 10

ADC

OUT

PUT

VOLT

AGE

(µV)

TIME (Seconds) 2165

7-04

8

39.5

39.0

38.5

38.0

37.5

37.0

Figure 28. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 100 kSPS,

250 Samples Averaged per Reading


Data Sheet ADAQ4003


0

1

2

3

4

5

6

7

8

9

10

OPE

ARTI

NG C

URRE

NT (m

A)

TEMPERATURE (°C)–40 –5 25 85 125

VDD, HIGH-Z DISABLEDVDD, HIGH-Z ENABLEDVIO, HIGH-Z DISABLEDVIO, HIGH-Z ENABLEDVS+, HIGH-Z DISABLEDVS+, HIGH-Z ENABLED

2165

7-13

1

Figure 29. Operating Current vs. Temperature, 2 MSPS

–30

–25

–20

–15

–10

–5

0

5

10

15

20

25

30

GAI

N ER

ROR

(LSB

)

TEMPERATURE (°C)

POSITIVE FULL-SCALE ERROR, G = 0.454POSITIVE FULL-SCALE ERROR, G = 0.909POSITIVE FULL-SCALE ERROR, G = 1.9NEGATIVE FULL-SCALE ERROR, G = 0.454NEGATIVE FULL-SCALE ERROR, G = 0.909NEGATIVE FULL-SCALE ERROR, G = 1.9

–40 –5 25 85 125

2165

7-23

3

Figure 30. Gain Error vs. Temperature for Positive Full-Scale Error and

Negative Full-Scale Error and for G = 0.454, G = 0.909, and G = 1.9

90

95

100

105

110

115

120

125

130

135

DYNA

MIC

RAN

GE

AND

SNR

(dB)

OVERSAMPLING RATE (OSR)

G = 0.454, DYNAMIC RANGEG = 0.454, fIN = 1kHzG = 0.454, fIN = 10kHzG = 0.909, DYNAMIC RANGEG = 0.909, fIN = 1kHzG = 0.909, fIN = 10kHzG = 1.9, DYNAMIC RANGEG = 1.9, fIN = 1kHzG = 1.9, fIN = 10kHz

2165

7-13

3

0 2 4 8 16 32 64 128 256 512 1024

Figure 31. Dynamic Range and SNR vs. Oversampling Rate for G = 0.454,

G = 0.909, and G = 1.9, and for Input Frequencies, 2 MSPS

0

2

4

6

8

10

12

14

16

18

20

POW

ER (m

W)

THROUGHPUT (Hz)

VDDVIOREFTOTAL POWER

100 1k 10k 100k 1M

2165

7-13

7

Figure 32. Power vs. Throughput

50

60

70

80

90

100

110

120

130

PSRR

(dB)

FREQUENCY (Hz)1k100 1M100k10k

VS+VS–VDD

2165

7-13

5

Figure 33. PSRR vs. Frequency

40

50

60

70

80

90

100

110

120

CMRR

(dB)

FREQUENCY (Hz)

G = 0.454G = 0.909G = 1.9

2165

7-13

6

100 1k 10k 100k 1M

Figure 34. CMRR vs. Frequency for G = 0.454, G = 0.909, and G = 1.9


ADAQ4003 Data Sheet


+4.55, –10.50, –10.5–4.55, –10.5

–4.55, +8 +4.55, +8

+4.55, –5.5–4.55, –5.5 0, –6

+4.55, –8.8–4.55, –8.80, –9.3

–4.55, +10 +4.55, +10

–4.55, +10 +4.55, +10

–12

–9

–6

–3

–0

3

6

9

12

–5 –4 –3 –2 –1 0 1 2 3 4 5

INPU

T CO

MM

ON-

MO

DE V

OLT

AGE

(V)

FDA OUTPUT VOLTAGE (V)

VS = ±5VVS = +5.5V/0VVS = +5.5V/–1V

2165

7-04

2

Figure 35. Input Common-Mode Voltage vs. FDA Output Voltage, G = 0.454,

Differential Input 21

657-

046

+4.55, –13.250, –13.25–4.55, –13.25

–4.55, +6 +4.55, +6

+4.55, –2.4–4.55, –2.4 0, –2.8

+4.55, –4.8–4.55, –4.8

0, –4.8

–4.55, +7.15–4.55, +7.15

+4.55, +7.15+4.55, +7.15

–15

–9

–12

–6

–3

0

3

9

6

–5 –4 –3 –2 –1 0 1 2 3 4 5

INPU

T CO

MM

ON-

MO

DE V

OLT

AGE

(V)


VS = ±5VVS = +5.5V/0VVS = +5.5V/–1V

Figure 36. Input Common-Mode Voltage vs. FDA Output Voltage,

G = 0.909, Differential Input

+4.77, –8.850, –8.9–4.77, –8.85

–4.77, +5 +4.77, +5

+4.77, –1.43–4.77, –1.43 0, –1.43

+4.77, –2.95–4.77, –2.95

0, –2.91

–4.77, +5.93–4.77, +5.93

+4.77, +5.93+4.77, +5.93

–10

10

–5 –4 –3 –2 –1 0 1 2 3 4 5

INPU

T CO

MM

ON-

MO

DE V

OLT

AGE

(V)


VS = ±5VVS = +5.5V/0VVS = +5.5V/–1V

2165

7-04

7

–8

–6

–4

–2

0

2

4

6

8

Figure 37. Input Common-Mode Voltage vs. FDA Output Voltage, G = 1.9,

Differential Input

–30

–25

–20

–15

–10

–5

0

5

0.1 1 10 100

GAI

N (d

B)

FREQUENCY (MHz)

G = 1.9, FULL POWERG = 1.9, LOW POWERG = 0.454, FULL POWERG = 0.454, LOW POWERG = 0.909, FULL POWERG = 0.909, LOW POWER

2165

7-13

4

Figure 38. Small Signal Frequency Response and 0.1 dB Flatness for

G = 1.9, G = 0.454, and G = 0.909 at Full Power and Low Power


Data Sheet ADAQ4003


TERMINOLOGY Integral Nonlinearity (INL) Error INL error is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 39).

Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL error is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error Offset error is the difference between the ideal midscale voltage, 0 V, and the actual voltage producing the midscale output code, 0 LSB.

Gain Error The first transition (from 100 … 00 to 100 … 01) occurs at a level ½ LSB above nominal negative full scale. The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels.

Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal, including harmonics.

Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. ENOB is related to SINAD as follows:

ENOB = (SINADdB − 1.76)/6.02

ENOB is expressed in bits.

Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.

Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. Dynamic range is measured with a signal at −60 dBFS so that the range includes all noise sources and DNL artifacts.

Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels.

Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion.

Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy.

Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the input common-mode voltage of f.

CMRR (dB) = 10log(PADC_IN/PADC_OUT)

where: PADC_IN is the common-mode power at f applied to the inputs. PADC_OUT is the power at f in the ADC output.

Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at f to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of f.

PSRR (dB) = 10 log(PVDD_IN/PADC_OUT)

where: PVDD_IN is the power at f at the VDD pin. PADC_OUT is the power at f in the ADC output.


ADAQ4003 Data Sheet


THEORY OF OPERATION CIRCUIT INFORMATION The ADAQ4003 SiP is a fast, precision DAQ signal chain that uses a SAR architecture. As shown in Figure 1, the ADAQ4003 μModule DAQ solution contains a high bandwidth, fully differential, ADC driver, a low noise reference buffer, and an 18-bit SAR ADC, along with the critical precision passive components required to achieve optimized performance with pin-selectable gain options of 0.454, 0.909, 1, or 1.9. All active components including iPassives thin film resistors with ±0.005% matching in the circuit are designed by Analog Devices, which are factory calibrated to achieve a high degree of specified accuracy and minimize temperature dependent error sources.

The ADAQ4003 is capable of converting 2,000,000 samples per second (2 MSPS). The ADAQ4003 has a valid first conversion after being powered down for long periods that can reduce power consumed in applications where the ADC does not convert constantly.

The ADAQ4003 offers a significant reduction in form factor and total cost of ownership compared to traditional discrete signal chains from a selection of individual components, size of PCB, and manufacturing perspective, while still providing flexibility to adapt to a wide array of applications.

The ADAQ4003 incorporates a fully differential, high speed ADC driver with integrated precision resistors. The precision resistors can be pin strapped to achieve different gains for the fully differential ADC driver, which allows the user to match the input signal range. The fully ADC driver can be used in a differential manner or to perform a single-ended to differential conversion for a single-ended input.

The fast conversion time of the ADAQ4003, along with turbo mode, allows low clock rates to read back conversions, even when running at its maximum throughput rate. Note that for the ADAQ4003, the full throughput rate of 2 MSPS can be achieved only with turbo mode enabled. Because the ADAQ4003 has on-board conversion clocks, the serial clock (SCK) is not required for the conversion process.

The ADAQ4003 interfaces to any 1.8 V to 5 V digital logic family. The device is housed in a 7 mm × 7 mm, 0.80 mm pitch 49-ball CSP_BGA that provides significant space savings and allows flexible configurations.

TRANSFER FUNCTIONS The ideal transfer characteristics for the ADAQ4003 are shown in Figure 39 and Table 10.

100...000100...001100...010

011...101011...110011...111

ADC

CODE

(TW

OS

COM

PLEM

ENT)

ANALOG INPUT+FSR – 1.5 LSB

+FSR – 1 LSB–FSR + 1 LSB–FSR

–FSR + 0.5 LSB

21657-012

Figure 39. ADC Ideal Transfer Function (FSR Is Full-Scale Range)

Table 10. Output Codes and Ideal Input Voltages Analog Inputs Digital Output Code1

(Twos Complement, Hex) Description Span Compression Disabled Span Compression Enabled FSR − 1 LSB (131,071 × VREF)/(131,072 × G) (131,071 × 0.8 × VREF)/(131,072 × G) 0x1FFFF2 Midscale + 1 LSB VREF/(131,072 × G) 0.8 × VREF/(131,072 × G) 0x00001 Midscale 0 V 0 V 0x00000 Midscale − 1 LSB −VREF/(131,072 × G) −0.8 × VREF/(131,072 × G) 0x3FFFF −FSR + 1 LSB −(131,071 × VREF)/(131,072 × G) −(131,071 × 0.8 × VREF)/(131,072 × G) 0x20001 −FSR −VREF × G −0.8 × VREF × G 0x200003 1 This output code assumes that the negative input, IN−, of the ADC driver is being driven. 2 This output code is also the code for an overranged analog input (IN+ − IN− above VREF with the span compression disabled and above 0.8 × VREF with the span

compression enabled). 3 This output code is also the code for an underranged analog input (IN+ − IN− below −VREF with the span compression disabled and above 0.8 × VREF with the span

compression enabled).


Data Sheet ADAQ4003


APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS Figure 40 through Figure 47 show the recommended connection diagrams for the ADAQ4003 when applying a single-ended and differential input signal for four different gain options with respect to ground reference.

0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF


VDD = 1.8VREF_OUTREF = 5VVS+ = 5.5V

2.2µF

VIO

SDISCKSDOCNV

IN–

IN+

+11V

G = 0.454

R1K1–

–11V

0V 1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

ADC

21657-013

ADAQ4003

FDA

OUT+R1K–

R1K1–

R1K1+R1K+

OUT–

PD_AMP

PD_REF

Figure 40. Single-Ended to Differential Configuration with G = 0.454

0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

+5.5V

G = 0.909

–5.5V

0V 1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

IN–

IN+

OUT+R1K–

R1K1–

R1K1–

R1K1+

R1K+

PD_AMP

PD_REF

ADC

21657-014

ADAQ4003

FDA

OUT–


0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

OUT–

G = 1

1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

+5V

–5V

0V

R1K–

IN–

IN+

OUT+R1K–

R1K1–

R1K1+R1K+

PD_AMP

PD_REF

ADC

21657-015

ADAQ4003

FDA

Figure 42. Single-Ended to Differential Configuration with G = 1


ADAQ4003 Data Sheet


IN–

IN+

OUT+R1K–

R1K1–

R1K1+R1K+

0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

OUT–

+2.6V

G = 1.9

–2.6V0V 1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

PD_AMP

PD_REF

ADC

21657-016

ADAQ4003

FDA

R1K–/R1K1–


0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

+5.5V

EXAMPLE 3

–5.5V

0V

+15.5V

EXAMPLE 2

G = 0.454

+4.5V

+10V

0V0V

EXAMPLE 1

–11V

–5.5V

PD_AMP

PD_REF

ADC

R1K1+

R1K1–

R1K1+

R1K1–R1K1+

R1K1–

21657-017

ADAQ4003

FDAIN–

IN+

OUT+R1K–

R1K1–

R1K1+R1K+

OUT–

Figure 44. Differential Configuration with G = 0.454

0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

OUT–

1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

IN–

IN+

OUT+R1K–

R1K1–

R1K1+R1K+

PD_AMP

PD_REF

ADC

21657-018

ADAQ4003

FDA

+2.75V

EXAMPLE 3

–2.75V

0V

–7V

+7V

–7V–7V

0V

+7V

+9.75V

EXAMPLE 2

G = 0.909

+4.25V+7V

+0.35V

EXAMPLE 1

–5.15V–2.4V

R1K1+

R1K1–

R1K1+

R1K1–

R1K1+

R1K1–



Data Sheet ADAQ4003


0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

OUT–

1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

IN–

IN+

OUT+R1K–

R1K1–

R1K1+R1K+

PD_AMP

PD_REF

ADC

+2.5V

EXAMPLE 3

–2.5V

0V

–7V

+7V

–7V–7V

0V

+7V

+9.5V

EXAMPLE 2

G = 1

+4.5V+7V

+0.5V

EXAMPLE 1

–4.5V–2V

R1K+

R1K–

R1K+

R1K–

R1K+

R1K–

21657-019

ADAQ4003

FDA

Figure 46. Differential Configuration with G = 1

0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

OUT–

1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

IN–

IN+

OUT+R1K–

R1K1–

R1K1+R1K+

ADC

+1.3V

EXAMPLE 3

–1.3V

0V

–5V

+5V

–5V–5V

0V

+5V

+6.3V

EXAMPLE 2

G = 1.9

+3.7V+5V

+0V

EXAMPLE 1

–2.6V–1.3V

R1K+

R1K–

R1K+

R1K–

R1K+

R1K–

21657-020

ADAQ4003

FDA

PD_AMP

PD_REF


ANALOG INPUTS High Frequency Input Signals

The ADAQ4003 ac performance over a wide input frequency range using a 5 V reference voltage is shown in Figure 21 and Figure 24. The ADAQ4003 maintains exceptional ac performance for input frequencies up to the Nyquist frequency with minimal performance degradation.

EASE OF DRIVE FEATURES Input Span Compression

The ADAQ4003 includes a span compression feature that increases the headroom and footroom available to the ADC driver by reducing the input range by 10% from the top and bottom of the range while still accessing all available ADC codes. The SNR decreases by approximately 1.9 dB (20 × log(8/10)) for the reduced input range when span compression is enabled. Span compression is disabled by default but can be enabled by writing to the relevant register bit (see the Digital Interface section).

ADC High-Z Mode

The ADAQ4003 incorporates ADC high-Z mode, which reduces the nonlinear charge kickback when the capacitor DAC switches back to the input at the start of the acquisition. The ADC high-Z mode is disabled by default but can be enabled by writing to the register (see Table 14). Disable high-Z mode for input frequencies above 100 kHz or when multiplexing.

Driving the ADAQ4003 Using a High Impedance PGIA

The majority of instrumentation and programmable gain instrumentation amplifiers (PGIAs) are single-ended output, which cannot directly drive the fully differential data acquisition signal chain. However, the LTC6373 PGIA offers fully differential outputs, low noise, low distortion, and high bandwidth. The LTC6373 is dc-coupled on the input and the output with programmable gain settings (using the A2, A1, and A0 pins). These features enable the LTC6373 to drive the ADAQ4003 directly in many signal chain applications without sacrificing precision performance.

https://www.analog.com/LTC6373?doc=ADAQ4003.pdfhttps://www.analog.com/ADAQ4003?doc=ADAQ4003.pdf

ADAQ4003 Data Sheet


In Figure 50, the LTC6373 is used in a differential input to differential output configuration with dual supplies of ±15V. The LTC6373 can also be used in a single-ended input to differential output configuration, if required. The LTC6373 is directly driving the ADAQ4003 with its gain set as 0.454. The VOCM pin of LTC6373 is connected to ground and its outputs swing between −5.5 V and +5.5 V (opposite in phase). The FDA of ADAQ4003 level shifts the outputs of the LTC6373 to match the desired input common mode of the ADAQ4003 and provides the signal amplitude necessary to utilize the maximum 2 × VREF peak-to-peak differential signal range of the ADC inside the ADAQ4003 μModule. Figure 48 and Figure 49 show the SNR and THD performance using various gain settings of the LTC6373 for the circuit configuration shown in Figure 50.

21657-052

SNR

(dB)

LTC6373 GAIN SETTING (G)

fIN = 1kHzfIN = 5kHzfIN = 10kHz

0.5 1.0 2.0 4.0 8.0 16.0

95

93

91

89

87

85

Figure 48. SNR vs. LTC6373 Gain Setting, LTC6373 Driving the ADAQ4003

(Gain = 0.454)

21657-053

THD

(DB)

LTC6373 GAIN SETTING (G)

fIN = 1kHzfIN = 5kHzfIN = 10kHz

–92

–97

–102

–107

–112

–117

–1220.5 1.0 2.0 4.0 8.0 16.0

Figure 49. THD vs. LTC6373 Gain Setting, LTC6373 Driving the ADAQ4003

(Gain = 0.454)

V+IN

V+OUT

V–

V+

CAPDGND

V–IN

180pF–15V

(–5.5V)/G

+5.5V

–5.5V

+5.5V

+15V

–5.5V

(+5.5V)/G

(–5.5V)/G

+

–

21657-054

VOCM LTC6373

A2 A0

A1

0.1µF

0.1µF

10kΩVCMO

10kΩ

33Ω

33Ω

10µF

1nF

1nF

0.1µF



2.2µF

VIO

SDISCKSDOCNV

1kΩ

VCMO

1kΩ

1kΩ

1.1kΩ

1.1kΩ1kΩ

PD_AMP

PD_REF

ADC

ADAQ4003

FDAIN–

IN+

OUT+R1K–

R1K1–

R1K1+R1K+

OUT–

(+5.5V)/G

Figure 50. LTC6373 Driving ADAQ4003 (G = 0.454)

https://www.analog.com/LTC6373?doc=ADAQ4003.pdfhttps://www.analog.com/ADAQ4003?doc=ADAQ4003.pdf

Data Sheet ADAQ4003


VOLTAGE REFERENCE INPUT The ADAQ4003 voltage reference input (REF) is the noninverting node of the on board, low noise reference buffer. The reference buffer is included to optimally drive the dynamic input impedance of the SAR ADC reference node.

Also housed in the ADAQ4003 is a 10 µF decoupling capacitor that is ideally laid out within the device. This decoupling capacitor is a required piece of the SAR architecture. The REF_OUT capacitor is not just a bypass capacitor. This capacitor is part of the SAR ADC that cannot fit on the silicon simply. During the bit decision process, because the bits are settled in a few tens of nanoseconds or faster, the storage capacitor replenishes the charge of the internal capacitive DAC. As the binary bit weighted conversion is processed, small chunks of charge are taken from the 10 µF capacitor. The internal capacitor array is a fraction of the size of the decoupling capacitor, but this large value storage capacitor is required to meet the SAR bit decision settling time. There is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF_OUT and GND pins.

The reference value sets the maximum ADC input voltage that the SAR capacitor array can quantize. The reference buffer is set in the unity-gain configuration. Therefore, the user sets the reference voltage value with the REF pin and observes this value at the REF_OUT pin. The user is responsible for selecting a reference voltage value that is appropriate for the system under design. Allowable reference values range from 2.4 V to 5.1 V. However, do not violate the input common-mode voltage range specification of the reference buffer. With the inclusion of the reference buffer, the user can implement a much lower power reference source than many traditional SAR ADC signal chains because the reference source drives a high impedance node instead of the dynamic load of the SAR capacitor array. Root sum square the reference buffer noise with the reference source noise to arrive at a total noise estimate. Generally, the reference buffer has a noise density much less than that of the reference source.

For highest performance and lower drift, use a reference such as the ADR4550, or use a low power reference such as the ADR3450 at the expense of a decrease in the noise performance.

POWER SUPPLY (POWER TREE) The ADAQ4003 uses four power supply pins: an ADC driver positive (VS+) and negative supply (VS−), a core ADC supply (VDD), a digital input and output interface supply (VIO). VIO allows direct interface with any logic among 1.8 V, 2.5 V, 3 V, or 5 V. To reduce the number of supplies needed, VIO and VDD can be tied together for 1.8 V operation. A combination of the ADP5070 (dual, high performance dc-to-dc switching regulator), the LT3032 (dual, low noise, positive and negative, low dropout voltage linear regulator), and the LT3023 (dual, micropower, low noise, low dropout regulator) can generate independently regulated positive and negative rails for all four power supply pins, including ±15 V rails for any additional signal conditioning. Refer to the EVAL-ADAQ4003FMCZ user guide for details. The ADAQ4003 is insensitive to power supply variations (PSRR) over a wide frequency range, as shown in Figure 33.

The ADAQ4003 ADC powers down automatically at the end of each conversion phase. Therefore, the power scales linearly with the sampling rate. This feature makes the device ideal for low sampling rates (even a few samples per second) and battery-powered applications. Figure 32 shows the ADAQ4003 total power dissipation and individual power dissipation for each rail.

DIGITAL INTERFACE Although the ADAQ4003 has a reduced number of pins, the device offers flexibility in its serial interface modes. The ADAQ4003 can also be programmed via 16-bit SPI writes to the configuration registers.

When in CS mode, the ADAQ4003 is compatible with SPI, QSPI™, MICROWIRE®, digital hosts, and digital signal processors (DSPs). In this mode, the ADAQ4003 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, which is useful in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This interface is useful in low jitter sampling or simultaneous sampling applications.

The ADAQ4003 provides a daisy-chain feature using the SDI for cascading multiple ADCs on a single data line, similar to a shift register.

The mode in which the ADAQ4003 operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if SDI is high, and daisy-chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, daisy-chain mode is automatically selected.

In either 3-wire or 4-wire mode, the ADAQ4003 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital

http://www.analog.com/ADR4550?doc=ADAQ4003.pdfhttp://www.analog.com/ADR3450?doc=ADAQ4003.pdfhttps://www.analog.com/ADP5070?doc=ADAQ4003.pdfhttps://www.analog.com/LT3032?doc=ADAQ4003.pdfhttps://www.analog.com/LT3023?doc=ADAQ4003.pdfhttps://www.analog.com/EVAL-ADAQ4003?doc=ADAQ4003.pdfhttps://www.analog.com/ADAQ4003?doc=ADAQ4003.pdf

ADAQ4003 Data Sheet


host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback.

The busy indicator feature is enabled in CS mode if CNV or SDI is low when the ADC conversion ends.

The state of SDO on power-up is either low or high-Z depending on the states of CNV and SDI (see Table 11).

Table 11. State of SDO on Power-Up CNV SDI SDO 0 0 Low 0 1 Low 1 0 Low 1 1 High-Z

The ADAQ4003 has a turbo mode capability in both 3-wire and 4-wire mode. Turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enabled. Turbo mode allows a slower SPI clock rate, making interfacing simpler. The maximum throughput of 2 MSPS for the ADAQ4003 can be achieved only with turbo mode enabled and a minimum SCK rate of 75 MHz. The SCK rate must be sufficiently fast to ensure the conversion result is clocked out before another conversion initiates. The minimum required SCK rate for an application can be derived based on the sample period (tCYC), the number of bits that must be read (including the data and optional status bits), and the digital interface mode used. Timing diagrams and explanations for each digital interface mode are given in the digital modes of operation sections (see the CS Mode, 3-Wire Turbo Mode section and the CS Mode, 4-Wire with Busy Indicator section).

Status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration register. The six status bits are described in Table 12.

The ADAQ4003 is configured by 16-bit SPI writes to the desired configuration register. The 16-bit word can be written via the SDI line while CNV is held low. The 16-bit word consists of an 8-bit header and 8-bit register data. For isolated systems, the ADuM141D is recommended, which can support the 75 MHz SCK rate required to run the ADAQ4003 at its full throughput of 2 MSPS.

REGISTER READ AND WRITE FUNCTIONALITY The ADAQ4003 register bits are programmable, and the bits default statuses are listed in Table 12. The register map is shown in

Table 14. The OV clamp flag is a read only sticky bit, and this bit is cleared only if the register is read and the overvoltage condition is no longer present. The OV clamp flag gives an indication of the overvoltage condition when this bit is set to 0.

Table 12. Register Bits Register Bits Default Status OV Clamp Flag 1 bit, 1 = inactive (default)

Span Compression 1 bit, 0 = disabled (default) High-Z Mode 1 bit, 0 = disabled (default) Turbo Mode 1 bit, 0 = disabled (default) Enable Six Status Bits 1 bit, 0 = disabled (default)

All access to the register map must start with a write to the 8-bit command register in the SPI interface block. The ADAQ4003 ignores all 1s until the first 0 is clocked in (represented by WEN in Figure 51, Figure 52, and Table 13). The value loaded into the command register is always 0 followed by seven command bits. This command determines whether that operation is a write or a read. The ADAQ4003 command register is listed in Table 13.

Table 13. Command Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WEN R/W 0 1 0 1 0 0

All register read and writes must occur while CNV is low. Data on SDI is clocked in on the rising edge of SCK. Data on SDO is clocked out on the falling edge of SCK. At the end of the data transfer, SDO is put in a high impedance state on the rising edge of CNV if daisy-chain mode is not enabled. If daisy-chain mode is enabled, SDO goes low on the rising edge of CNV. Register reads are not allowed in daisy-chain mode.

A register write requires three signal lines: SCK, CNV, and SDI. During a register write to read the current conversion results on SDO, the CNV pin must be brought low after the conversion completes. Otherwise, the conversion results may be incorrect on SDO. However, the register write occurs regardless.

The LSB of each configuration register is reserved because a user reading 16-bit conversion data may be limited to a 16-bit SPI frame. The state of SDI on the last bit in the SDI frame may be the state that then persists when CNV rises. Because interface mode is partly set based on the SDI state when CNV rises, in this scenario, the user may need to set the final SDI state.

The timing diagrams in Figure 51 through Figure 53 show how data is read and written when the ADAQ4003 is configured in register read, write, and daisy-chain mode.

Table 14. Register Map ADDR[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x0 Reserved Reserved Reserved Enable six

status bits Span compression

High-Z mode

Turbo mode

OV clamp flag (read only sticky bit)

0xE1

http://www.analog.com/ADuM141D?doc=ADAQ4003.pdfhttps://www.analog.com/ADAQ4003?doc=ADAQ4003.pdf

Data Sheet ADAQ4003


tCYC

tSCK

tDIS

tSCKL

tSCKH

tSCNVSCK

tSSDISCKtHSDISCK

tCNVH

tEN

CNV

SCK 1 2 3 4 5 6 7

0 1

1

0 1 0 1 0 0

B0B1B2B3B4B5B6

WEN R/W 0 1 0 1 ADDR[1:0]

8 9 10 11 12 13 14 15 16

SDI

SDO

tHSDOtDSDO

B7 XD17 D16 D15 D14 D13 D12 D11 D10

2165

7-02

1

Figure 51. Register Read Timing Diagram

1

CONVERSION RESULT ON D17:0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

tCYCtSCK

tSCKL

tSCKH

tSCNVSCK

tSSDISCK

tHSDISCK

tCNVH1

tEN

CNV

SCK 1 2 3 4 5 6 7

0 0

1

0 1 0 1 0 0

WEN R/W 0 1 0 1 ADDR[1:0]

8 9 10 11 12 13 14 15 16 17 18

SDI

SDO

B0B1B2B3B4B5B6B7

tHSDOtDSDO

tHCNVSCK

1THE USER MUST WAIT tCONV TIME WHEN READING BACK THE CONVERSION RESULT AND DOING A REGISTER WRITE AT THE SAME TIME. 21657

-022

Figure 52. Register Write Timing Diagram

SDIA

SDOA/SDIB

SDOB

0 0COMMAND (0x14)

0 0COMMAND (0x14)

0 0COMMAND (0x14)

tCYC

tSCK

tSCKL

tSCKH

tSCNVSCK

CNV

SCK 1 24

tDIS

tCNVH

DATA (0xAB)

DATA (0xAB)

2165

7-02

3

Figure 53. Register Write Timing Diagram, Daisy-Chain Mode


ADAQ4003 Data Sheet


STATUS WORD The 6-bit status word can be appended to the end of a conversion result, and the default conditions of these bits are shown in Table 15. The status bits must be enabled in the register setting. When the OV clamp flag is 0, this bit indicates an overvoltage condition. The OV clamp flag status bit updates on a per conversion basis.

The SDO line returns to high impedance after the sixth status bit is clocked out (except in daisy-chain mode). The user is not required to clock out all status bits to start the next conversion. The serial interface timing for CS mode, 3-wire without busy indicator, including status bits, is shown in Figure 54.

Table 15. Status Bits (Default Conditions) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OV clamp flag Span compression High-Z mode Turbo mode Reserved Reserved

SDO D17 D16 D15 D1 D0

SCK 1 2 3 16 17 18

tSCK

tSCKL

tSCKHtHSDOtDSDO

CN V

CONVERSIONACQUISITION

tCYC

ACQUISITION

SDI = 1

tCNVH

ACQ

tEN

23 24

tQUIET2

STATUS BITS B[5:0]

B1

tDIS

B0

22

tCONV

2165

7-02

4

Figure 54. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram Including Status Bits (SDI High)


Data Sheet ADAQ4003


CS MODE, 3-WIRE TURBO MODE

This mode is typically used when a single ADAQ4003 device is connected to an SPI-compatible digital host. This mode provides additional time during the end of the ADC conversion process to clock out the previous conversion result, providing a lower SCK rate. The ADAQ4003 can achieve a throughput rate of 2 MSPS only when turbo mode is enabled and using a minimum SCK rate of 75 MHz. The connection diagram is shown in Figure 55, and the corresponding timing diagram is shown in Figure 56.

To enable turbo mode, set the turbo mode enable bit in the configuration register to 1 (see Table 12). This mode replaces the 3-wire with busy indicator mode by programming the turbo mode bit, Bit 1 (see Table 14). Writing to the user configuration register requires SDI to be connected to the digital host (see the Register Read and Write Functionality section). When turbo mode is enabled, the conversion result read on SDO corresponds to the result of the previous conversion.

When performing conversions in this mode, SDI must be held high, and a CNV rising edge initiates a conversion and forces

SDO to high impedance. The user must wait the tQUIET1 time after CNV is brought high before bringing CNV low to clock out the previous conversion result. When the conversion is complete (after tCONV), the ADAQ4003 enters the acquisition phase and powers down. The user must also wait the tQUIET2 time after the last falling edge of SCK to when CNV is brought high.

When CNV goes low, the MSB is output to SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time, as dictated by tHSDO (see Table 3). If the status bits are not enabled, SDO returns to high impedance after the 18th SCK falling edge. If the status bits are enabled, the bits are shifted out on SDO on the 19th through the 24th SCK falling edges (see the Status Word section). SDO returns to high impedance after the 18th SCK falling edge, or when CNV goes high (whichever occurs first). The user must also provide a delay of tQUIET2 between the final SCK falling edge and the next CNV rising edge to ensure specified performance.

2165

7-02

5

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

DATA OUT

ADAQ4003

Figure 55. CS Mode, 3-Wire Turbo Mode Connection Diagram (SDI High)

SDI = 1

tCYC

CNV

ACQUISITION ACQUISITION

tACQ

tSCK

tSCKL

CONVERSION

SCK

D0D1D15D16D17SDO

tEN

tHSDO

1 2 3 16 17 18

tDSDO tDIS

tSCKH

tQUIET1tQUIET2

tCONV

2165

7-02

6

Figure 56. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)


ADAQ4003 Data Sheet


CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is typically used when a single ADAQ4003 device is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 57, and the corresponding timing diagram is shown in Figure 58.

When SDI is connected to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. After a conversion initiates, it continues until completion irrespective of the state of CNV. This feature can be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers. However, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator.

When the conversion completes, the ADAQ4003 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that the digital host has an acceptable hold time. After the 18th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance.

There must not be any digital activity on SCK during the conversion.

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOSTVIO

ADAQ4003

2165

7-02

7

Figure 57. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)

SDO D17 D16 D15 D1 D0

tDIS

SCK 1 2 3 16 17 18

tSCK

tSCKL

tSCKHtHSDOtDSDO

CNV


tCYC

ACQUISITION

SDI = 1

tCNVH

tACQ

tEN

tQUIET2

tCONV21

657-

028

Figure 58. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High)


Data Sheet ADAQ4003


CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is typically used when a single ADAQ4003 device is connected to an SPI-compatible digital host with an interrupt input (IRQ).

The connection diagram is shown in Figure 59, and the corresponding timing diagram is shown in Figure 60.

When SDI is connected to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can select other SPI devices, such as analog multiplexers. However, CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator.

When the conversion completes, SDO goes from high impedance to low impedance. With a pull-up resistor of 1 kΩ on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The ADAQ4003 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that the digital host has an acceptable hold time. After the optional 19th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance.

If multiple ADAQ4003 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation.

There must not be any digital activity on the SCK during the conversion.

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOSTVIO

IRQ

VIO

1kΩ

ADAQ4003

2165

7-02

9

Figure 59. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)

SDO D17 D16 D1 D0

tDIS

SCK 1 2 3 17 18 19

tSCK

tSCKL

tSCKHtHSDO

tDSDO

CNV


tCONV

tCYC

ACQUISITION

SDI = 1

tCNVH

tACQ

tQUIET2

2165

7-03

0

Figure 60. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High)


ADAQ4003 Data Sheet


CS MODE, 4-WIRE TURBO MODE

This mode is typically used when a single ADAQ4003 is connected to an SPI-compatible digital host. This mode provides additional time during the end of the ADC conversion process to clock out the previous conversion result, giving a lower SCK rate. The ADAQ4003 can achieve a throughput rate of 2 MSPS only when turbo mode is enabled and using a minimum SCK rate of 75 MHz. The connection diagram is shown in Figure 61, and the corresponding timing diagram is shown in Figure 62.

This mode replaces the 4-wire with busy indicator mode by programming the turbo mode bit, Bit 1 (see Table 14).

With SDI high, a rising edge on CNV initiates a conversion. The previous conversion data is available to read after the CNV

rising edge. The user must wait tQUIET1 after CNV is brought high before bringing SDI low to clock out the previous conversion result. The user must also wait tQUIET2 after the last falling edge of SCK to when CNV is brought high.

When the conversion is complete, the ADAQ4003 enters the acquisition phase and powers down. The ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that the digital host has an acceptable hold time. After the 18th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance.

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

IRQ

CS1

VIO

1kΩ

ADAQ4003

2165

7-03

1

Figure 61. CS Mode, 4-Wire Turbo Mode Connection Diagram

ACQUISITION

SDO

SCK

ACQUISITION

SDI

CNV

tSSDICNV

tHSDICNV

tCYC

tSCK

tSCKL

tEN

tHSDO

1 2 3 16 17 18

tDSDO tDIStSCKH

D17 D16 D15 D1 D0

tQUIET1tQUIET2

tACQ

CONVERSION

tCONV

2165

7-03

2

Figure 62. CS Mode, 4-Wire Turbo Mode Timing Diagram


Data Sheet ADAQ4003


CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is typically used when multiple ADAQ4003 devices are connected to an SPI-compatible digital host.

A connection diagram example using two ADAQ4003 devices is shown in Figure 63, and the corresponding timing diagram is shown in Figure 64.

With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers. However, SDI must be returned high before the minimum

conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator.

When the conversion is complete, the ADAQ4003 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that the digital host has an acceptable hold time. After the 18th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance and another ADAQ4003 can be read.

SDI SDO

CNV

SCK

CONVERT

CLKDATA IN

DIGITAL HOST

CS1CS2

ADAQ4003SDI SDO

CNV

SCK

ADAQ4003DEVICE BDEVICE A

2165

7-03

3

Figure 63. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

SDO D17 D16 D15 D1 D0

tDIS

SCK 1 2 3 34 35 36

tHSDOtDSDOtEN


tCONV

tCYC

tACQ

ACQUISITION

SDI (CS1)

CNV

tSSDICNV

tHSDICNV

D1

16 17

tSCKtSCKL

tSCKH

D0 D17 D16

19 2018

SDI (CS2)

tQUIET2

2165

7-03

4

Figure 64. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram


ADAQ4003 Data Sheet


CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is typically used when a single ADAQ4003 device is connected to an SPI-compatible digital host with an interrupt input (IRQ), and when it is desired to keep CNV, which samples the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 65, and the corresponding timing diagram is shown in Figure 66.

With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers.

However, SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator.

When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up resistor of 1 kΩ on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The ADAQ4003 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that the digital host has an acceptable hold time. After the optional 19th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance.

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

IRQ

CS1

VIO

1kΩ

ADAQ4003

2165

7-03

5

Figure 65. CS Mode, 4-Wire with Busy Indicator Connection Diagram

SDO D17 D16 D1 D0

tDIS

SCK 1 2 3 17 18 19

tSCK

tSCK

18-bit, 2 msps, µmodule data acquisition solution data ......18-bit, 2 msps, µmodule data...

Documents