2009 IEEE International Advance Computing Conference (IACC 2009)Patiala, India, 6-7 March 2009

Power Optimization of Linear Feedback ShiftRegister (LFSR) for Low Power BIST

Balwinder Singh Arun Khosla Sukhleen BindraVLSI & Embedded System Design ECE Department, Dr.B.R.Ambedkar Electronics Department

Centre for Development Of National Institute of Technology, Guru Nanak Dev University,Advanced Computing, Mohali, India Jalandhar, India Amritsar, India

Abstract-This paper proposes a low power LinearFeedback Shift Register (LFSR) for Test Pattern cost: cents !tansistorGeneration (TPG) technique with reducing power o.1dissipation during testing. The correlations between the ooi1consecutive patterns are higher during normal mode than 01 transistorduring testing. The proposed approach uses the concept of

T protreducing the transitions in the test pattern generated by i.T al nsconventional LFSR. The transition is reduced by OXI Based on 97 SIA Roadmap Datincreasing the correlation between the successive bits. The 0000

simulation result show that the interrupt controller 1982 1985 188 1991 9 9 2 2003 2006 2009 220l2benchmark circuit's testing power is reduced by 46%withrespect to the power consumed during the testing carried Figure 1: Fabrication cost versus testing costby conventional LFSR.

Keywords-LFSR, Optimization, LowPower,TestPattrens There are main two sources of power dissipation in digitalcircuits; these are static and dynamic power dissipation. Static

I. INTRODUCTION power dissipation is mainly due to leakage current and itscontribution to total power dissipation is very small. Dynamic

The main challenging areas in VLSI are performance, cost, power dissipation is due to switching i.e. the power consumeddue to short circuit current flow and charging of loadtesting, area, reliability and power. The demand for portable

computing devices and communications system are increasingrapidly. These applications require low power dissipation for 0.5VDD2E(sw)CLFCLKVLSI circuits. The power dissipation during test mode is 200% Pmore than in normal mode [1]. Hence it is important aspect tooptimize power during testing. Power optimization is one of where Vdd is supply voltage, E(sw) is the average number ofthe main challenges. output transitions per 1/fclk, fclk is the clock frequency and CL

is the physical capacitance at the output of the gate. DynamicThere are various factors that affect the cost of chip likepackaging, application, testing etc. In VLSI, according to power dissipation contributed to total power dissipation. Fromthumb rule 5000 of the total integrated circuits cost is due to the above equation the dynamic power depends on three

parameters: Supply voltage, Clock frequency, Switchingactivity. To reduce the dynamic power dissipation by using

* Cost of testing that can't be scaled. first two parameter only at the expense of circuit performance.But power reduction using the switching activity doesn't* Engineering effort for generating test vectors derethprfmacofheicu.

increases as complexity of circuit increasesderethprfnacofheicu.Power dissipation during the testing is one of most importantBased on 1997 SIA data, the upper curve shows the issue [12]. There are several reasons for this power increased

fabrication cost of transistor and lower curve shows the testing in test mode.cost of transistor. Figure 1 shows that the fabrication costtransistor decreases over the decades according to Moore's law * To test large circuit, circuits are partitioned to savebut the testing cost as constant.[2] the test time but this parallel testing results in

excessive energy and power dissipation.

978-1T-4244-2928-8/09/$25.00 ©& 2009 IEEE 3l11

* Due to the lack of at-speed equipment availability, II. PRIORWORKdelay is introduced in the circuit during testing. Thiscause power dissipation. There has been various low power approaches proposed to* In the successive functional input vectors applied to a

give cicuitinnonnl mde hve sigifiant solve the problem of power dissipation during the testing.givrenlcircuitshin normal modrelhaveatignifient Some of the earliest work that has been proposed forcorrelation, whil the con be twen. optimizing the power during testing are discussed in thisconsecutive testpatns canbeveryuowThin section of the paper. One method is to use Random Singlecause large stchtding avityino l thecircuitn d eri Input Change (RSIC) test generation, which is used totest than that during its normal operation. Po generate low power test patter. In this method, power

issipatcion acMO cir.i p otciongalt consumption is reduced but at the additional cost is betweensicing ativtmy tirexcesive r witchin lacivity, 1900 and 130o. Another technique was proposed in [5]. Thisduringtestmayneverespcation,autosil fr cst,recola ty, approach proposed a low transition LFSR for BISTpelaterf prormance applications. This reduces the average and peak power of

related problems. circuit during testing. In [6] approach, a fault model and

During testing large power is dissipated than in the normal ATPG algorithm is chosen first and then test pattern are

mode. This is due to lack of correlation between the generated to obtain the desired fault coverage. There are

various advantages of test pattern generation at a higher levelsucsietesti patteRnsgnrte(forBISTandthislargepow e xalion than the gate level. While F. Corno et al has proposed for the

tasesting)forlFSRin (frcts:BIST)andthislargepowerdissipatio low power test pattern generation for sequential circuit [7]. Incases following effects: this paper, redundancy is introduced during testing and this

reduces the power consumption without affecting the fault..t inreasednpowerimay rons for coverage. In [8], it is shown that different LFSR architecture

rechnoliy, performance veriicton aonomy .an affects the power consumed and the hardware used. Jinkyutechnog restappliated oproblems.sLowcpower Lee et al [9] developed a LFSR reseeding scheme. In this

duporiangtest appliaof iti is thuay's beSIcircming tan deql approach, there are two goals, first is to reduce the number ofimportant fiue o me in od VLS circuitstdesin transition in scan chain. Second is to reduce the number ofand iS expected to become one of the major objectives in spcfebisgnrtdyLFReedn.

the near future. ~~~~~~~specified bits generated by LFSR reseeding.the near future.* High power and ground noise caused by high

switching during testing are serious problem where the III. BIST ARCHITECTUREsupply connects are poor. Thus excessive noise canchange the logic state of the circuit lines leading good It is very important to choose the proper LFSR architecture fordies to fail the test and hence loss of yield.diAst.he rut is hendeeposubfmicron.achieving the appropriate fault coverage. Every architecture*As the circuit iS designed in the deep sub micron(DSM) technology, this uses small supply voltages and consumes different power even for same polynomial. Another

' . . . p~~~~~~roblem associated with choosing LFSR iS LFSR desi n issuehence this reduces the use of special cooling equipment to .g giwhich includes LFSR partitioning, in this the LFSR areremove t werxessive h dungatatest. ed.Butinoth differentiated on the basis of hardware cost and testing time* Low power testing iS done at at-speed. But in other cs

testing techniques, circuits are added to lower thefrequency of circuit during test.

A typical BIST architecture consists of a test pattern generator(TPG), usually implemented as a linear feedback shift register

For complex circuits, hierarchical approach is used. The (LFSR), a test response analyzer (TRA), implemented as a

advantage of hierarchical approach is that every block is tested multiple input shift register (MISR), and a BIST control unit

separately. Test input is given to each block and output is (BCU), all implemented on the chip (Figure 1). This approachobserved and verified. DFT (Design For Testability) is the allows applying at-speed tests and eliminates the need for an

action of placing features in a chip design process to enhance external tester. The BIST architecture components are giventhe ability to generate vectors, achieve a measured quality below.level or reduce cost of testing. The conventional DFT * Circuit Under Test (CUT): It is the portion of the circuitapproaches use scan and BIST. tested in BIST mode. It can be sequential, combinational

or a memory. Their Primary Input (PI) and PrimaryIn this paper a modified low power LFSR are used in which output (P0) delimitmit.

the number of transitions of test pattern are reduced testing. Outest Pae Generat (t P0 Test Pattern Generator (TPG): It generates the testThe remainder paper is organized as follows: Section 2

describes the previous work while section 3 presents the microprocessor. The patterns may be generated inproposed work. Section 4 describes the simulation results and psuorno ordtriitclyconclusions.

312 2009 IEEE Internlationlal Advance Computing Conference (IACC 2009)

ParttrenGeneration

Ciruit Under D Q I Q 1Q QQ

B IST Co ntro Her T est; (CUT)Unit (B CTJ) 1> * p

ty F~~~~~~~~~~ ~~ ~~ ~ ~~reset r r ,

Figure 3: LFSR in which input of first flip-flop is xored with0- Test Response ArLalysis (TRA) last flip-flop.

In this approach the 3 intermediate test vectors are generatedTest Results between every two successive vectors (say TI, T2). The total

number of signal transition occurs between these 5 vectors areFigure 2 BIST Architecture equivalent to the number of transition occurs between the 2

vectors. Hence the power consumption is reduced. Additional* Multiple input signatures registers (MISR): it is designed circuit is used for few logic gates in order to generate 3

for signature analysis, which is a technique for data intermediate vectors. The 3 intermediate vectors (Ta, Tb, Tc)compression. MISR efficiently map different input are achieved by modifying conventional flip-flops outputs andstreams to different signatures with every small low power outputs. The first level of hierarchy from top toprobability of alias. MISR are frequently implemented in down includes logic circuit design for propagation either thebuilt-in-self-test (BIST) designs, in which output present or next state of flip-flop to second level of hierarchy.responses are compressed by MISR. Second level of hierarchy is implementing Multiplexed

* Test Response Analysis (TRA): It analyses the value (MUX) function i.e. selecting two states to propagate to outputsequence on PO and compares it with the expected output as shown in flow:

* BIST Controller Unit (BCU): It controls the testexecution; it manages the TPG, TRA and reconfigures theCUT and the multiplexer. It is activated by theNormal/Test signal and generates a Go/No go. F al i c

gives output as previous

IV. ALGORITHM FOR LOW POWER LFSR GeneratinggTIBothhales axe idle. Firsthalf sentto outpu.t and|

As discussed in the previous section LFSR is used to generate seondhalfs oueis sentitor cutptest patterns for BIST. In this, test patterns are generated

e Xondsutputissrb inj e ctor

externally by LFSR, which is inexpensive and high speed.0

LFSR is a circuit consists of flip-flops in series. LFSR is a Generating eneratingTashift register where output bit is an XOR function of some next vectorinput bits. The initial value of LFSR is called seed value. Second half is active, and first half is in idle modeLFSR's seed value has a significant effect on energy ard gives same output a previousconsumption. [3]. The output that influence the input arecalled tap. A LFSR is represented by as polynomial, which is OeneratinggTbalso known as characteristic polynomial used to determine thefeedback taps, which determine the length of random pattern Both halves are in idle mode. First havees is givengeneration. The output of LFSR is combination of I's and O's. byinjector and secondhIf is same as previousA common clock signal is applied to all flip-flops, whichenable the propagation of logical values from input to output Generating Tcof flip-flops. Increasing the correlation between bits reducesthe power dissipation. This can be achieved by adding morenumber of test vectors, which decreases the switching activity. Figure 4: Proposed algorithm for low power LFSRLFSR is characterized by the polynomial by its characteristicspolynomial and inverse of characteristics polynomial isgenerated polynomial.

2009 IEEE Internlationlal Advance Computing Conference (IACC 2009) 313

The EDA tool is used in which conventional and low power | 350 RFSRl-LP LFSRLFSR is coded in Verilog hardware descriptive language and a 366

seed value is given 256-|(01001010010110101101001O100101101011) to the 2606polynomial and primitive value polynomial in LFSR block. X l5 I

The outputs of the 36-bit LFSR are used as the inputs to the 166c432 ISCAS-85 a benchmark circuit of interrupt controller. In 50

this c432 is used as CUT; the generated code is synthesized in 6Xilinx Web Pack 9.1 for Spartan 2e device. The hardware input Output Total power

Dynamic Dynamicsummary is obtained for each method implementation log file pcwDer pcoi'ierof Xilinx 9.1 project navigator. The RTL view of LP-LFSRwith c432 benchmark circuit is shown in figure 5.

Figure 6. Comparison of Power dissipation in testing withconventional and low power LFSR

E. rLet ifi:_Itis observed that the total power consumed in modifiedLFSR is 46% less than the power consumed with normal

l $--:E U LFSR and out put dynamic power is decreased by 44.6 %. It isconcluded that low power LFSR is very useful for BISTimplementation in which the CUT may be Combinational,sequential and memory circuits. Using low power LFSRtechnique we can further decrease the power in BISTimplementation.

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314 2009 IEEE Internlationla/Advance Computing Conference (IACC 2009)