TRNG H K THUT CNG NGH TP HCM

N MN HC: DO KHONG CCH

LI M U Cm bin trong ting anh gi l sensor xut pht t ch sense tc l cm nhn. T ngn xa ngi tin s nh vo cc gic quan xc gic cm nhn, tm hiu c im ca th gii t nhin v hc cch s dng nhng hiu bit nhm mc ch khai thc th gii xung quanh phc v cho cuc sng ca h.

Trong thi i pht trin ca khoa hc v k thut ngy nay con ngi khng ch da vo cc c quan xc gic ca c th km ph th gii. cc chc nng xc gic nhn bit cc vt th hin tng xy ra trong thin nhin c tng cng nh cc pht trin dng c dung lng v phn tch m ta gi l cm bin.

Cm bin c nh ngha nh cc thit b dung bin i cc ddaij lng vt l v cc i lng khng in cn o thnh cc i lng in c th o c( nh dng in,in th,in dung , tr khng). N l thnh phn quan trng nht trong cc thit b o hay trong cc h thng iu khin t ng . c th ni: nguyn l hot ng ca mt cm bin, trong hiu trng hp thc t cng chnh l nguyn l ca php o hay ca phng php iu khin t dng.

t lu cm bin c s dng nh nhng b phn cm nhn v pht hin, nhng ch t vi chc nm tr li y chng mi th hin r vai tr quan trng trong cc hot ng ca con ngi. Nh nhng thnh tu mi ca khoa hc v cng ngh trong lnh vc vt liu, thit b in t v tin hc, cc cm bin c gim thiu kch thc, ci thin tnh nng v ngy cng m rng phm vi ng dng. gi y khng c mt lnh vc no m khng s dng cc cm biin. chng c mt trong cc h thng t ng phc tp, ngi my, kim tra cht lng sn phm, ti kim nng lng, chng nhim mi trng. Cm bin cng c s dng rng ri trong lnh vc giao thng vn ti, hang tiu dung, bo qun thc phm, t, tr chi in t..

Mt trong cc ng ng rt dng ri v ph bin l cm bin v tr v dch chuyn. V vic kim tra v tr v dch chuyn dng vai tr raats quan trng i vi hot ng ca nhiu my mc,cng c. Hn na, mt s i lng vt l c th o c thng qua vic xc nh s dch chuyn ca mt vt chu tc ng ca i lng vt l .

C nhiu phng php xc nh v tr v dch chuyn. trong phm vi mn hc, chng ta c th thit k c mt mch in t n gin o khoang cch, s dng cm bin siu m. lm mch ny cn thit k c 3 phn chnh : b phn cm bin - b phn x l - b phn hin th. PH LC.1LI M U

2PH LC.

3BNG NHN XT CA GIO VIN HNG DN

4BNG NHN XT CA GIO VIN PHN BIN

5PHN II : L THUYT THIT K

5I.S KHI

5II.KHI CM BIN SIU M SRF 05 :

51.Gii thiu cm bin siu m SRF05 :

52.Thng s k thut :

63.Ch hoat ng :

63.1Ch 1 :

73.2Ch 2 :

84.Chc nng cc chn :

85.Nguyn tc hot ng ca SRF05:

86.Tnh ton v xc nh khong cch :

11III.KHI IU KHIN ATMEGA8.

111.S chn ATMEGA8 :

122.T chc ca ATMega8 ni ring, AVR ni chung.

122.1B nh d liu.

132.2Vng Nh

132.3RAM tnh, ni (internal SRAM).

142.4RAM ngoi (external SRAM).

142.5EEPROM (Electrically Ereasable Programmable ROM)

143.Cu trc bn trong ca ATMEGA8

15IV.KHI HIN TH.

151.Chc Nng chn LCD.

162.S khi LCD

162.1Cc thanh ghi

162.2C bo bn BF

172.3B m a ch AC : (Address Counter)

172.4Vng RAM hin th DDRAM : (Display Data RAM)

182.5Vng ROM cha k t CGROM: Character Generator ROM

192.6Vng RAM cha k t ha CGRAM

20PHN III: NI DUNG THI CNG

20I.S NGUYN L

21II.CODE LP TRNH CHOVDK:

26PHN IV : U NHC IM V TLTK.

26I.U IM :

26II.NHC IM :

26III.TI LIU THAM KHO:

BNG NHN XT CA GIO VIN HNG DNGio vin hng dn : NGUYN TH NGC ANH

H v tn sinh vin : Bi Cng Tun

Lp : 09HDT1

Mssv : 09B1010058

Tn ti: THIT K V THI CNG MCH DO KHONG CCH im nh gi : Xp loi :

TP H Ch Minh, ngy 28 thng 11 nm 2010

Gio vin hng dn

( K tn v ghi r h tn)

BNG NHN XT CA GIO VIN PHN BIN

Gio vin phn bin :

H v tn sinh vin : BI CNG TUN

Lp : 09HDT1

Mssv : 09B100058

Tn ti: THIT K V THI CNG MCH O KHONG CCHim nh gi : Xp loi :

TP H Ch Minh, ngy thng nm 2010

Gio vin phn bin

( K tn v ghi r h tn)

PHN II : L THUYT THIT KI. S KHI

II. KHI CM BIN SIU M SRF 05 : 1. Gii thiu cm bin siu m SRF05 : SRF05 l mt bc pht trin t SRF04 , oc thit k lm tng tnh linh hot, tng phm vi hot dng v gim chi ph. Do ,SRF05 As such, the SRF05 is fully compatible with the SRF04.hon ton tng thch vi SRF04. Range is increased from 3 meters to 4 meters. Khong cch c tng ln t 3 mt n 4 mt. A new operating mode (tying the mode pin to ground) allows the SRF05 to use a single pin for both trigger and echo, thereby saving valuable pins on your controller. Mt ch hot ng mi (chn chn ch ni t ) cho php SRF05 s dng mt chn duy nht cho c kch hot v phn hi, do tit kim chn cho b iu khin ca bn. When the mode pin is left unconnected, the SRF05 operates with separate trigger and echo pins, like the SRF04. Khi chn ch c ngt kt ni, SRF05 hot ng vi cc chn kch hot v chn phn hi ring bit. chn hi tip, ging nh l SRF04. The SRF05 includes a small delay before the echo pulse to give slower controllers such as the Basic Stamp and Picaxe time to execute their pulse in commands. SRF05 thit lp sn mt thi gian tr nh trc khi xung phn hi mang li iu khin chm hn chng hn nh b iu khin thi gian c bn Stamps v Picaxe thc hin cc xung lnh.

HNH: cm bin siu m SRF05.2. Thng s k thut :

in p 5V

Dng thp 4mA

Tn s 40KHz

Phm vi hot ng 1cm - 4cm

Loi 1 chn cho triger/echo

hoc 2 chn tng thch SRF04

u vo kch khi 10uS min, mc xung TTL

Xung va p Mc tn hiu dng, b rng i xng

43x20x17 (mm)

iu khin t ng Khng nh kch c hot ng, tu x l, hot ng nhanh

Tgian hot ng Thi gian hi p, a tn hiu iu khin

3. Ch hoat ng : 3.1 Ch 1 :

Ch ny s dng chn kch hot v chn phn hi ring bit, v l ch n gin nht s dng. Tt c cc chng trinh mu cho SRF04 s lm vic vi SRF05 ch ny. s dng ch ny, ch vic ngt kt ni chn mode - SRF05 c mt in tr ni pull up chn ny.

3.2 Ch 2 :

Ch ny s dng mt chn duy nht cho c tn hiu kch hot v hi tip, v c thit k lu cc gi tr trn chn ln b iu khin nhng.

To use this mode, connect the mode pin to the 0v Ground pin. s dng ch ny, chn mode ni vi mass. The echo signal will appear on the same pin as the trigger signal. Tn hiu hi tip s xut hin trn cng mt chn vi tn hiu kch hot. The SRF05 will not raise the echo line until 700uS after the end of the trigger signal. SRF05 s khng tng dng phn hi cho n 700uS sau khi kt thc cc tn hiu kch hot. You have that long to turn the trigger pin around and make it an input and to have your pulse measuring code ready. Bn c thi gian kch hot pin xoay quanh v lm cho n tr thnh mt u vo v c pulse o m ca bn sn sng. The PULSIN command found on many popular controllers does this automatically. Lnh PULSIN c tm ra v c dng ph bin hin nay iu khin t ng.

4. Chc nng cc chn : - Echo Output : chn u ra tn hiu phn hi v t cm bin.

- Triger Output : chn u vo kch hot

- Mode : chn ch ( khng c kt ni ch mt)

- b nm chn bn kia : The 5 pins marked "programming pins" are used once only during manufacture to program the Flash memory on the PI5 c ng nhn l "programming pins" ch c s dng mt ln duy nht trong qu trnh sn xut lp trnh cho b nh Flash trn chip PIC16F630. The PIC16F630's programming pins are also used for other functions on the SRF05, so make sure you don't connect anything to these pins, or you will disrupt the modules operation. Cc chn chng trnh ca PIC16F630 cng c s dng cho cc chc nng khc trn SRF05, nn chc chn rng bn khng kt ni bt c ci g vi cc chn, hoc bn s lm gin on hot ng m-un 5. Nguyn tc hot ng ca SRF05:

T gin iu khin ta thy :

SRF05 hot ng ta cn cp mt xung mc cao c rng t nht l 10uS trn chn TRI

sau SRF05 s pht ra mt chu k 8 khi tn hiu siu m tn s 40KHz v tng dng tn hiu phn hi ca n ln mc cao (hoc ng tn hiu kch hot ch 2 ) . sau n ch phn hi, v ngay sau khi pht hin mt vt th n s gim dng phn hi xung. do dng phn hi s l mt xung c rng t l vi khong cch ti vt th. Bng cch o xung , ta hon ton c th tnh ton khong cch theo n v inch / cm hay bt c g khc. Nu khng pht hin vt th th SRF05 s ko dng phn hi xuc mc thp sau 30mS . SRF04 cung cp mt xung phn hi t ln vi khong cch. Nu o rng ca xung bi uS, sau chia cho 58 s cho ta khong cch tnh bng cm, hoc chia cho 148 s cho khong cch atinhs bng inches: uS/58=cm hoc uS/148=inches. SRF05 c th c kch hot nhanh chng vi mi 50mS, hay 20 ln / s. Bn nn i 50ms trc xung kch hot k tip, ngay c khi SRF05 pht hin vt th gn v xung phn hi ngn hn. iu ny m bo rng siu m beep tt hn v khng lm sai lch tn hiu phn hi trong ln o tip theo c bit SRF05 ch c th nhn xung trn chn TRI ti a 20 Hz,cho nn vic kch xung trn chn TRI phi ph hp th SRF05 mi hot ng chnh xc.

6. Tnh ton v xc nh khong cch :

Sng siu m c truyn i trong khng kh vi vn tc 343 m/s. Nu mt cm bin pht ra sng siu m v thu v cc sng phn x ng thi, o c khong thi gian t lc pht ra ti lc thu v, th my tnh c th xc nh c qung ng m sng di chuyn trong khng gian. Qung ng di chuyn ca sng = 2 ln khong cch t cm bin ti chng ngi vt theo hng pht ca sng siu m. khong cch t cm bin ti chng ngi vt s c tnh theo nguyn l TOF

d = eq \s\don1(\f(v.t,2)) ( Time Of Flight )

Trong : d- khong cch cn o v- vn tc sng siu m trong mi trng truyn sng

t: thi gian t lc sng c pht i n lc sng c ghi nhn li

5- sai s v hiu chnh cm bin :

a- sai s :

hin tng c cho(crosstalk) ca cm bin.

Hin tng forecasting :

III. KHI IU KHIN ATMEGA8.1. S chn ATMEGA8 :

Bn c th thy chip ny gm 28 chn, trng c cc chn c ghi l PB0(chn 14), PB1(chn 15),,PB7(chn 10), l cc chn ca PORTB. PORT l khi nim ch cc ng xut nhp. Trong AVR, PORT c th giao tip theo 2 hng (bi directional), c th dng xut hoc nhn thng tin, mi PORT c 8 chn. Chip Atmega8 c 3 PORT c tn tng ng l PORTB, PORTC v PORTD (mt s chip AVR khc c 4 hoc 6 PORT). PORT c coi l ca ng then cht ca vi iu khin.

Trong AVR, mi PORT lin quan n 3 thanh ghi (8 bits) c tn tng ng l DDRx, PINx, v PORTx vi x l tn ca PORT, mi bit trong thanh ghi tng ng vi mi chn ca PORT. Trong trng hp ca Atmega8 x l B, C hoc D. V d chng ta quan tm n PORTB th 3 thanh ghi tng ng c tn l DDRB, PINB v PORTB, trong 2 thanh ghi PORTB v PINB c ni trc tip vi cc chn ca PORTB, DDRB l thanh ghi iu khin hng ( Input hoc Output). Vit gi tr 1 vo mt bit trong thanh ghi DDRB th chn tng ng ca PORTB s l chn xut (Output), ngc li gi tr 0 xc lp chn tng ng l ng nhp. Sau khi vit gi tr iu khin vo DDRB, vic truy xut PORTB c thc hin thng qua 2 thanh ghi PINB v PORTB.

Quay li vi 2 dng code ca chng ta, dng u: LDI R16, 0xFF, vi LDI LoaD Immediately, dng lnh c ngha l load gi tr 0xFF vo thanh ghi R16, R16 l tn 1 thanh ghi trong b nh ca AVR, 0xFF l 1 hng s c dng thp lc phn, k hiu 0x ni ln iu , bn cng c th dng k hiu khc l $ ch 1 s thp lc phn, v d &FF, v 0xFF=255(thp phn)=0B11111111 (nh phn). Nh th sau dng u thanh ghi R16 c gi tr l 11111111 (nh phn). Dng th 2: OUT DDRB, R16 ngha l xut gi tr t thanh ghi R16 ra thanh ghi DDRB, tm li sau 2 dng trn gi tr DDRB nh sau:

11111111

C th bn s hi ti sao chng khng s dng 1 dng duy nht l LDI DDRB, 0xFF hay OUT DDRB, 0xFF, chng ta khng th v lnh LDI ch cho php thc hin trn cc thanh ghi R16,R31 v lnh OUT khng thc hin c vi cc hng s.

V v DDRB=11111111 nn trong trng hp ny tt c cc chn ca PORTB sn sng cho vic xut d liu. Lc ny thanh ghi PINB khng c tc dng, thanh ghi PORTB s l thanh ghi xut, ghi gi tr vo thanh ghi ny s tc ng n cc chn ca PORTB.1.2. T chc ca ATMega8 ni ring, AVR ni chung.

C cu trc Harvard, trong ng truyn cho b nh d liu (data memory bus) v ng truyn cho b nh chng trnh (program memory bus) c tch ring. Data memory bus ch c 8 bit v c kt ni vi hu ht cc thit b ngoi vi, vi register file. Trong khi program memory bus c rng 16 bits v ch phc v cho instruction registers. Hnh 1 m t cu trc b nh ca AVR.

B nh chng trnh (Program memory): L b nh Flash lp trnh c, trong cc chip AVR c (nh AT90S1200 hay AT90S2313) b nh chng trnh ch gm 1 phn l Application Flash Section nhng trong cc chip AVR mi chng ta c thm phn Boot Flash setion. Boot section s c kho st trong cc phn sau, trong bi ny khi ni v b nh chng trnh, chng ta t hiu l Application section. Thc cht, application section bao gm 2 phn: phn cha cc instruction (m lnh cho hot ng ca chip) v phn cha cc vector ngt (interrupt vectors). Cc vector ngt nm phn u ca application section (t a ch 0x0000) v di n bao nhiu ty thuc vo loi chip. Phn cha instruction nm lin sau , chng trnh vit cho chip phi c load vo phn ny.

B nh d liu (data memory): y l phn cha cc thanh ghi quan trng nht ca chip, vic lp trnh cho chip phn ln l truy cp b nh ny. B nh d liu trn cc chip AVR c ln khc nhau ty theo mi chip, tuy nhin v c bn phn b nh ny c chia thnh 5 phn.2.1 B nh d liu.

Bao gm 32 thanh ghi c tn gi l register file (RF), hay General Purpose Rgegister GPR, hoc n gin l cc Thanh ghi. Tt c cc thanh ghi ny u l cc thanh ghi 8 bits nh trong hnh 2.

Hnh 2. Thanh ghi 8 bits.

Tt c cc chip trong h AVR u bao gm 32 thanh ghi Register File c a ch tuyt i t 0x0000 n 0x001F. Mi thanh ghi c th cha gi tr dng t 0 n 255 hoc cc gi tr c du t -128 n 127 hoc m ASCII ca mt k t no Cc thanh ghi ny c t tn theo th t l R0 n R31. Chng c chia thnh 2 phn, phn 1 bao gm cc thanh ghi t R0 n R15 v phn 2 l cc thanh ghi R16 n R31. Cc thanh ghi ny c cc c im sau:

c truy cp trc tip trong cc instruction.

Cc ton t, php ton thc hin trn cc thanh ghi ny ch cn 1 chu k xung clock.

Register File c kt ni trc tip vi b x l trung tm CPU ca chip.

Chng l ngun cha cc s hng trong cc php ton v cng l ch cha kt qu tr li ca php ton.

2.2 Vng Nh

Vng nh I/O l ca ng giao tip gia CPU v thit b ngoi vi. Tt c cc thanh ghi iu khin, trng thica thit b ngoi vi u nm y. Xem li v d trong bi 1, trong ti c cp v vic iu khin cc PORT ca AVR, mi PORT lin quan n 3 thanh ghi DDRx, PORTx v PINx, tt c 3 thanh ghi ny u nm trong vng nh I/O. Xa hn, nu mun truy xut cc thit b ngoi vi khc nh Timer, chuyn i Analog/Digital, giao tip USARTu thc hin thng qua vic iu khin cc thanh ghi trong vng nh ny.

Vng nh I/O c th c truy cp nh SRAM hay nh cc thanh ghi I/O. Nu s dng instruction truy xut SRAM truy xut vng nh ny th a ch ca chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi I/O th a ch ca chng c tnh t 0x0000 n 0x003F. 2.3 RAM tnh, ni (internal SRAM).

L vng khng gian cho cha cc bin (tm thi hoc ton cc) trong lc thc thi chng trnh, vng ny tng t cc thanh RAM trong my tnh nhng c dung lng kh nh (khong vi KB, ty thuc vo loi chip).

2.4 RAM ngoi (external SRAM).

Cc chip AVR cho php ngi s dng gn thm cc b nh ngoi cha bin, vng ny thc cht ch tn ti khi no ngi s dng gn thm b nh ngoi vo chip

2.5 EEPROM (Electrically Ereasable Programmable ROM)

l mt phn quan trng ca cc chip AVR mi, v l ROM nn b nh ny khng b xa ngay c khi khng cung cp ngun nui cho chip, rt thch hp cho cc ng dng lu tr d liu. Nh trong hnh 1, phn b nh EEPROM c tch ring v c a ch tnh t 0x0000.

3. Cu trc bn trong ca ATMEGA8

Hnh . Cu trc bn trong ATmega 8.

ATmega c 32 thanh ghi trong Register File c kt ni trc tip vi Arithmetic Logic Unit -ALU (ALU cng c xem l CPU ca AVR) bng 2 line, v th ALU c th truy xut trc tip cng lc 2 thanh ghi RF ch trong 1 chu k xung clock. (vng c khoanh trn mu trong hnh 4).

Cc instruction c cha trong b nh chng trnh Flash memory di dng cc thanh ghi 16 bit. B nh chng trnh c truy cp trong mi chu k xung clock v 1 instruction cha trong program memory s c load vo trong instruction register, instruction register tc ng v la chn register file cng nh RAM cho ALU thc thi. Trong lc thc thi chng trnh, a ch ca dng lnh ang thc thi c quyt nh bi mt b m chng trnh PC (Program counter). chnh l cch thc hot ng ca AVR.

AVR c u im l hu ht cc instruction u c thc thi trong 1 chu k xung clock, v vy c th ngun clock ln nht cho AVR c th nh hn 1 s vi iu khin khc nh PIC nhng thi gian thc thi vn nhanh hn

IV. KHI HIN TH.1. Chc Nng chn LCD.

S ChnTnChc Nng

1VssChn ni t cho LCD, khi thit k mch ta ni chn ny vi GND ca mch iu

khin

2VddChn cp ngun cho LCD, khi thit k mch ta ni chn ny vi VCC=5V ca mch

iu khin

3Veeiu khin tung phn ca LCD

4RSChn chn thanh ghi (Register select). Ni chn RS vi logic 0 (GND) hoc logic

1 (VCC) chn thanh ghi.

+ Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR ca LCD ( ch ghi -

write) hoc ni vi b m a ch ca LCD ( ch c - read)

+ Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu DR bn trong LCD.

5R/WChn chn ch c/ghi (Read/Write). Ni chn R/W vi logic 0 LCD hot

ng ch ghi, hoc ni vi logic 1 LCD ch c

6EChn cho php (Enable). Sau khi cc tn hiu c t ln bus DB0-DB7, cc lnh

ch c chp nhn khi c 1 xung cho php ca chn E.

+ ch ghi: D liu bus s c LCD chuyn vo(chp nhn) thanh ghi bn

trong n khi pht hin mt xung (high-to-low transition) ca tn hiu chn E.

+ ch c: D liu s c LCD xut ra DB0-DB7 khi pht hin cnh ln (low-

to-high transition) chn E v c LCD gi bus n khi no chn E xung mc

thp.

7-14BD0-BD7Tm ng ca bus d liu dng trao i thng tin vi MPU. C 2 ch s

dng 8 ng bus ny :

+ Ch 8 bit : D liu c truyn trn c 8 ng, vi bit MSB l bit DB7.

+ Ch 4 bit : D liu c truyn trn 4 ng t DB4 ti DB7, bit MSB l DB7

Chi tit s dng 2 giao thc ny c cp phn sau

2. S khi LCD

Hinh: S khi ca LCD

2.1 Cc thanh ghiChp HD44780 c 2 thanh ghi quan trng. Thanh ghi IR: iu khin LCD. Ngui dng phi ra lnh thng qua ung bus tn hiu, mi lnh uc nh cung cp qui nh r rang. Ngi dung ch vic cung cp a ch lnh bng cch np vo thanh ghi IR. Ngha l, khi ta np vo thanh ghi IR mt chui 8 bit, chp HD44780 s tra bng m

lnh ti a ch m IR cung cp v thc hin lnh Thanh ghi DR dung cha d liu 8 bit ghi vao RAM DDRAM hoc CG RAM. Hoc dung cha d liu t hai vng RAM gi ra MPU. Ngha l, khi MPU ghi thng tin vo DR, mch ni bn trong chp s t ng ghi thng tin ny vo DDRAM hoc CGRAM. Hoc khi thng tin v a ch c ghi vo IR, d liu a ch ny trong vng RAM ni caHD44780 s c chuyn ra DR truyn cho MPU.

2.2 C bo bn BFHi thc hin cc hot ng bn trong chp, mch ni bn trong cn mt khong thi gian hon tt. Khi ang thc thi cc hot ng bn trong chip nh th, LCD b qua mi giao tip vi bn ngoi v bt c BF(thng qua chn DB7 khi c thit lp RS=0, R/W=1) ln bo cho MPU bit n ang bn. D nhin,

khi xong vic, n s t c BF li mc 0.2.3 B m a ch AC : (Address Counter)

Nh trong s khi, thanh ghi IR khng trc tip kt ni vi vng RAM (DDRAM v CGRAM) m

thng qua b m a ch AC. B m ny li ni vi 2 vng RAM theo kiu r nhnh. Khi mt a ch

lnh c np vo thanh ghi IR, thng tin c ni trc tip cho 2 vng RAM nhng vic chn la vng

RAM tng tc c bao hm trong m lnh.

Sau khi ghi vo (c t) RAM, b m AC t ng tng ln (gim i) 1 n v v ni dung ca AC c

xut ra cho MPU thng qua DB0-DB6 khi c thit lp RS=0 v R/W=1 (xem bng tm tt RS - R/W).

Lu : Thi gian cp nht AC khng c tnh vo thi gian thc thi lnh m c cp nht sau khi c

BF ln mc cao (not busy), cho nn khi lp trnh hin th, bn phi delay mt khong tADDkhong 4uS-

5uS (ngay sau khi BF=1) trc khi np d liu mi. Xem thm hnh bn di.

2.4 Vng RAM hin th DDRAM : (Display Data RAM)

y l vng RAM dng hin th, ngha l ng vi mt a ch ca RAM l mt k t trn mn hnh v

khi bn ghi vo vng RAM ny mt m 8 bit, LCD s hin th ti v tr tng ng trn mn hnh mt k t

c m 8 bit m bn cung cp. Hnh sau y s trnh by r hn mi lin h ny

Vng RAM ny c 80x8 bit nh, ngha l cha c 80 k t m 8 bit. Nhng vng RAM cn li

khng dng cho hin th c th dng nh vng RAM a mc ch.

Lu l truy cp vo DDRAM, ta phi cung cp a ch cho AC theo m HEX

2.5 Vng ROM cha k t CGROM: Character Generator ROM

Vng ROM ny dng cha cc mu k t loi 5x8 hoc 5x10 im nh/k t, v nh a ch bng

8 bit. Tuy nhin, n ch c 208 mu k t 5x8 v 32 mu k t kiu 5x10 (tng cng l 240 thay v

28= 256 mu k t). Ngi dng khng th thay i vng ROM ny.

Hnh 5 : Mi lin h gia a ch ca ROM v d liu to mu k t.

2.6 Vng RAM cha k t ha CGRAM: (Character Generator RAM)

Nh trn bng m k t, nh sn xut dnh vng c a ch byte cao l 0000 ngi dng c th to cc mu k t ha ring. Tuy nhin dung lng vng ny rt hn ch: Ta ch c th to 8 k t loi 5x8 im nh, hoc 4 k t loi 5x10 im nh. ghi vo CGRAM, hy xem hnh 6 bn di

Hnh 6 : Mi lin h gia a ch ca CGRAM, d liu ca CGRAM, v m k t.

PHN III: NI DUNG THI CNGI. S NGUYN L

II. CODE LP TRNH CHOVDK: /*****************************************************

This program was produced by the

CodeWizardAVR V2.03.9 Standard

Automatic Program Generator

Copyright 1998-2008 Pavel Haiduc, HP InfoTech s.r.l.

http://www.hpinfotech.com

Project :

Version :

Date : 11/25/2010

Author : Bui Cong TuanCompany :

Comments:

Chip type : ATmega8

Program type : Application

AVR Core Clock frequency: 4.000000 MHz

Memory model : Small

External RAM size : 0

Data Stack size : 256

*****************************************************/

#include

#include

#define Signal_Output PORTC.0

#define Signal_status DDRC.0 // 0 = In & 1 = Out

#define Signal_Input PINC.0

// Alphanumeric LCD Module functions

#asm

.equ __lcd_port=0x12 ;PORTD

#endasm

#include

//Child program

void lcd_putint(unsigned int so, unsigned char x, unsigned char y); //Display interger number

void lcd_putnum(unsigned char So, unsigned char x, unsigned char y); //Display char number

unsigned int read_from_sensor();

// Declare your global variables here

unsigned int Distance; //Store distance value =Wide_of_pulse/58 cm; wide_of_pulse/148 Inch. 3-400 cm

unsigned int Wide_of_pulse; volatile unsigned char TimerStatus;

unsigned int TempI;

unsigned char TempC;

interrupt [TIM0_OVF] void timer0_ovf_isr(void)

{

// Reinitialize Timer 0 value

TCNT0=0x28;

// Place your code here

TimerStatus=1;

}

void main(void)

{

// Declare your local variables here

PORTB=0x00;

DDRB=0x00;

PORTC=0x00;

DDRC=0xff;

PORTD=0x00;

DDRD=0xFF;

TCCR0=0x01;

TCNT0=0x28;

// Analog Comparator initialization

// Analog Comparator: Off

// Analog Comparator Input Capture by Timer/Counter 1: Off

ACSR=0x80;

SFIOR=0x00;

// Global enable interrupts

#asm("sei")

// LCD module initialization

lcd_init(16);

//*** sensor initial ***

Signal_status = 1; // out

Signal_Output = 1;

delay_ms(35);

Signal_status = 0; // In

Signal_Output = 0;

delay_ms(10);

while (1)

{

// Place your code here

lcd_gotoxy(0,0);

lcd_putsf("Distant measure");

//Wide_of_pulse = 0; //Reset counter

Wide_of_pulse = read_from_sensor();

Distance = Wide_of_pulse/58; //cm

lcd_putint(Distance,5,1);

lcd_putsf("Cm");

delay_ms(1000);

if (TempC