1 system-on-chip (soc) testing an introduction and overview of ieee 1500 standard testability method...

18
1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

Upload: claribel-simon

Post on 13-Jan-2016

212 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

1

System-on-Chip (SoC) Testing

An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-

based ICs

Page 2: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

2

What is a SoC?

Technological advances allow electronic systems that earlier occupied one or more boards onto a single IC. The attending advantages are:

Higher performanceLower Power consumptionSmaller volume and weight

Typically, heterogeneous, containing a mix of:Digital logicMemories of different formats and typesAnalog circuitsEmbedded cores

Page 3: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

3

What is a core?Large, reusable building blocksReuse speeds up design, brings in external expertise.Typical core functions:

CPUs and DSPsSerial interfacesModules for interconnect standards, e.g. PC, USB, IEEE 1394 (Firewire), and for graphics computation, e.g. MPEG and JPEGMemories

Core Types:Soft (RTL code)Firm (netlist)hard (layout)

Page 4: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

4

Core Providers vs. Core Users

Cores have changed the nature of components used in system design:

In traditional system-on-board design provided components were ICs, designed, manufactured, and tested by the provider. Users could assume components to be fault-free and needed to test only interconnect between the components.In SoC, components are cores (soft, firm, or hard) that are not yet manufactured or tested for defects.

Page 5: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

5

New Testing Issues in SoCs

Core user responsible for manufacturing and testing the SoCHowever, this is not possible without the assistance of core provider because core design is hidden for IP reasons.Typically, core provider assists by delivering pre-defined tests with the core.The problem that faced the SoC designer was how to apply these tests at the core boundaries.

Page 6: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

6

IEEE 1500 Standard for Embedded Core Test*

Stated Purpose: Reduce test cost through improved automation, promote good design-for-test (DFT) technique, and improve test quality through improved access. Scalable standard architecture for test reuse and integration for embedded cores and associated circuitry.Only defined for digital circuitry.Has serial and parallel test-access mechanisms (TAMs) and an instruction set for testing cores, SoC interconnect, and circuitry.Provides features to isolate and protect cores

•http://grouper.ieee.org/groups/1500/index.html. See also, E. J. Marinissen et al., Journal of Electronic Testing: Theory and Applications (JETTA), 18, 365-383, 2002.

Page 7: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

7

Generic Test Access Architecture

Architecture components

SourceSinkTAMsWrapper

Source/sink can be external or internal to the chip.

Page 8: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

8

Overview of Wrapper Architecture

Page 9: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

9

Wrapper Instructions

Page 10: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

10

Timing: WIR shift, then WIR Update

Page 11: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

11

Wrapper Boundary Cells

For Core Input For Core Output

Page 12: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

12

Wrapper Serial Bypass Example

Page 13: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

13

Wrapper External Test Mode

Page 14: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

14

Core Test Language (CTL)Purpose: Support all information the core provider needs to give for embedding the core in a SoC.Requirement: Patterns, which contain bulk of the test data, are reusable without any modification.

CTL Components

Page 15: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

15

SoC Test ChallengesCore Test

Providing DfT inside cores and test patterns to linked by SoC designer to chip-level test patterns sources and sinks that may be on-chip (BIST) or off-chip (ATE)

Core Test Access: Problems relate to deep embedding of cores and their large I/O pins compared to chip I/O pins. Sophisticated TAMs provide the solution.SoC Level Test: How to integrate individual core tests and tests for interconnect? The solution take the form of test scheduling strategies.

Page 16: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

16

Two Compliance Levels

1. Unwrapped Cores: Bare core - no wrapper - but must have a CTL program for core test at the bare-core level, which can be used to design a “1500-wrapped” core.

2. Wrapped Cores: IEEE 1500 wrapper + CTL program.

Page 17: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

17

Example Core and Wrapper

Page 18: 1 System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

18

Instruction Decoding for Serial and Parallel Tests