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Enhancing Testability And Yield Of KGD in 2.5/3D ICs Through The Use Of
Die-level Traceability And Analysis
November, 2012
PDF Solutions, Inc
1
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Ideally, all 3D ICs Yield 100%! IC System modeling capable of :
Perfectly determines allowable spec ranges for all key component die characteristics. For both functional and speed / power tests. Across the full range of process variability
All key component die characteristics are known and can be accurately tested
And, no defects during 3D IC assembly
2D vs. 2.5D vs. 3D ICs 101 Clive Maxfield EE Times Design
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How to investigate, understand, and even predict 3D IC yield losses?
Need the ability to correlate component die test data with 3D IC failure data
For that we need a DB with step-to-step Die-Level Traceability capability
But, what to do when 3D ICs fail?
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Aligning Dice to IC’s in the Database
Component Die 3D IC
Product A DieID X
DieID for component die A DieID for component die B
In order to align component die data with IC test data, need the following key indexes • Product, DieID (for each component die) • DieIDs (for all component die IDs, for each 3D IC)
Product B DieID Y
Pseudo – DieID can be created from Lot / Wafer / DieX / DieY
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What other data is in the Database? Fab
• Equipment History: Machine ID, Chamber, Date / Time, … at each Process step • Metrology: Film Thickness, Critical Dimension, Sheet Resistance, … • Defect: Inspection data
Wafer Test • PCM/WAT: Process Control Monitor structures in scribe lanes
• Simple transistors, resistors, chains, …. • Scribe CV: Characterization Vehicle – in scribe lane
• More complex structures to characterize circuit, device and process. • Wafer Sort
• Bin, Parametric Assembly Data
• Equipment History: Machine ID, Date / Time, … at each Process step
• Metrology: Wafer Thickness, … • Material: Interposer ID, …
Final Test • Bin, Parametric
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dataPOWER Analysis Ready Database
Analysis
Reports
PCM, Sort Final Test
Defect
Vendor
Test
Bitmap
Vendor
Metrology Equip History
Events
Fab
FDC (Equip Sensor)
Fab Equip
Data Extraction Automated data retrieval Data aligned across the different data types Data is Analysis Ready
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So, what can I learn from this data?
Limits lines allow determination of IC Yield improvement , if Wafer Sort Limits are modified
Would tightening Wafer Sort spec limits increase IC yield? How much would IC Yield improve? How much additional Die Yield loss would there be?
Regression Analysis: IC Final Test Bin / Parametric correlation to Die-Level Wafer Sort
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Can I predict IC yield loss, from CV/PCM data?
PSA (Product Sensitivity Analysis): Correlate die-level PCM test structure data to average / median for ICs containing surrounding product die
Determine whether IC yield loss can be predicted by PCM or CV structure tests Corollary question: Can PCM spec limits be loosened without increasing IC yield loss
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Which equipment is responsible for IC yield loss? Equipment commonality analysis: Relationship between IC yield and
Equipment History data
3D IC assembly equipment commonality Component die process equipment commonality
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CV® Infrastructure: Types of CV Test Chips
CV® test chips
NiSi Module
Parametric Module
SRAM Module
Device Layout
Systematic Defects
Custom Modules
Leakage characterization
PADS PADS PADS M6 s&c > > > < <
^ ^ V5 chain < < < M5 s&c > >
^ ^ V4 chain M4 s&c > > > < <
^ ^ V3 chain < < < M3 s&c > >
^ ^ V2 chain M2 s&c > > > < <
^ ^ V1 chain < < < M1 s&c > >
^ ^ C chain < < PO s&c > ̂ > ̂ < < PO s&c
< < < AA s&c > ̂ > ̂ < < < AA s&c
Layer M6 V5 M5 V4 M4 V3 M3 V2 M2 V1 M1 C PO AA
Stackable CV: Systematic and
Random Defectivity
xFEOL CV: Device, Lkg,
Variability
60µm minimum
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Scal
able
(e.g
. 3.9
mm
)
Mass Production & Yield Ramp
Yield Ramp & Technology Development
xScribe CV Device, Yield,
Parametric, Leakage
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Scribe CV™ Overview
Family of Scribe CV (SCV): • Yield SCV & Device SCV
Typical area for each is ~65um x 6000um, but adjustable
Typical PCM scribe structure: 9 die tested in ~15 min per wafer
Scribe CV™ Yield SCV: 150 die tested in ~4 min
per wafer* Device SCV: 100 die tested in ~12 min
per wafer
60µm minimum
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Product
Die
Scal
able
(e.g
. 3.9
mm
)
Scribe CV Test pattern – 150
die PCM 9 die
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Scribe CV Example: Yield SCV Diagnosis of Wafer Excursion
Thin scratches can be difficult to detect and find conclusive matching using conventional 9 point PCM sampling
Scribe CV has excellent spatial coverage to catch such issues
Product Bin x Fail SCV Contact Opens
Problem layer for yield excursion
identified
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Scribe CV Comparison to Typical PCM
Two to three orders of magnitude more information per Si area per test time for xScribe CV® vs. PCM
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Data
Scribe CV Test and Analysis Flow Scribe CV system includes tester hardware, on-chip tester, data post-process unit
pdFasTest
wafer
pad
DUT 1 DUT 2 DUT 3 DUT 4 DUT N
On- chip
Tester
probes pdFasTest Hardware
PDF xScribe content package
… Design
Of Exp’ts
On-chip Tester Behavior Model
dataPOWER database
Client Analysis or
WAT System
Optional YA-FDC i-Diagnostic
YA-FDC YA-FDC EOL drill down
Client DUT
Test Data PostProcessor
Summarized data • Analyzed summary • DOE model results
Client EDA readable data
dataPOWER Analysis
Summary Database
Workflow Report
Integrated design of pdFasTest, scribe CV, and dataPOWER analysis enables orders of magnitude more information
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Summary
Die-Level-Traceability (DLT) database 3D IC test data Component die genealogy and test data Scribe CV test data Fab WIP and Metrology data Assembly Equipment/Material History Sort Data Final Test
Automated retrieval capabilities to easily extract and align data
Analysis capability to understand the causes of yield loss
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Enhancing Testability and Yield of KGD in 2.5D / 3D ICs through the analysis data from die-level traceability database Mike Alperin, dataPOWER Product Manager, Volume Manufacturing Solutions Marketing, PDF SOLUTIONS
Stacking die to create 2.5D and 3D ICs may introduce yield losses due to subtle timing, power and thermal mechanisms not adequately accounted for in the IC system design.
To enhance KGD testability and yields, it may be necessary to empirically correlate IC system characteristics to component die product and wafer scribe Characterization Vehicle (CV) parametric distributions. CV structure correlations are then used to isolate design and process problems.
In order to establish these correlations, a Die-Level-Traceability (DLT) database is needed that contains IC test data, component die genealogy information / test data, CV test data and even fab WIP / metrology data. In addition, automated retrieval and analysis capabilities are needed to easily extract and align all the needed data, then perform the required analysis.
A system for establishing these IC yield relationships on First Si and then monitoring them during ramp and volume production will be demonstrated.
Abstract